74LVQ02 [FAIRCHILD]
Low Voltage Quad 2-Input NOR Gate; 低电压四2输入或非门
| 型号： | 74LVQ02 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Quad 2-Input NOR Gate |
| 文件： | 总6页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1998
74LVQ02
Low Voltage Quad 2-Input NOR Gate
General Description
The LVQ02 contains four 2-input NOR gates.
Features
n Ideal for low power/low noise 3.3V applications
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Guaranteed pin-to-pin skew AC performance
n Guaranteed incident wave switching into 75Ω
Ordering Code:
Order Number
74LVQ02SC
74LVQ02SJ
Package Number
M14A
Package Description
14-Lead (0.150" Wide) Molded Small Outline Integrated Circuit, SOIC JEDEC
14-Lead Small Outline Package, SOIC EIAJ
M14D
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Assignment for
SOIC JEDEC and EIAJ
DS011342-1
DS011342-2
Pin Descriptions
Pin Names
An, Bn
On
Description
Inputs
Outputs
© 1998 Fairchild Semiconductor Corporation
DS011342
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Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
)
Supply Voltage (VCC
)
=
VI −0.5V
−20 mA
+20 mA
LVQ
2.0V to 3.6V
0V to VCC
0V to VCC
=
VI VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
DC Output Diode Current (IOK
)
Operating Temperature (TA)
74LVQ
=
VO −0.5V
−20 mA
+20 mA
−40˚C to +85˚C
=
VO VCC + 0.5V
Minimum Input Edge Rate (∆V/∆t)
VIN from 0.8V to 2.0V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
@
VCC 3.0V
125 mV/ns
±
50 mA
or Sink Current (IO
DC VCC or Ground Current
(ICC or IGND
)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be op-
erated at these limits. The parametric values defined in the Electrical Charac-
teristics tables are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for ac-
tual device operation.
±
)
200 mA
Storage Temperature (TSTG
DC Latch-Up Source or
Sink Current
)
−65˚C to +150˚C
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
±
100 mA
DC Electrical Characteristics
VCC
=
=
Symbol
Parameter
TA +25˚C
TA −40˚C to +85˚C
Units
Conditions
(V)
3.0
3.0
Typ
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
1.5
1.5
2.0
0.8
2.0
0.8
V
V
VOUT 0.1V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
or VCC − 0.1V
=
IOUT −50 µA
VOH
Minimum High Level
Output Voltage
3.0
3.0
2.99
2.9
2.9
V
V
=
VIN VIL or VIH (Note 3)
2.58
2.48
=
IOH −12 mA
=
IOUT 50 µA
VOL
Maximum Low Level
Output Voltage
3.0
3.0
0.002
0.1
0.1
V
V
=
VIN VIL or VIH (Note 3)
0.36
0.44
=
IOL 12 mA
=
±
±
1.0
IIN
Maximum Input
Leakage Current
3.6
0.1
µA
VI VCC, GND
=
VOLD 0.8V Max (Note 5)
IOLD
IOHD
ICC
Minimum Dynamic (Note 4)
Output Current
3.6
3.6
3.6
36
mA
mA
µA
=
VOHD 2.0V Min (Note 5)
−25
20.0
=
Maximum Quiescent
Supply Current
2.0
VIN VCC
or GND
VOLP
VOLV
VIHD
VILD
Quiet Output
3.3
3.3
3.3
3.3
0.6
−0.7
1.7
1.0
−1.0
2.0
V
V
V
V
(Notes 6, 7)
Maximum Dynamic VOL
Quiet Output
Minimum Dynamic VOL
(Notes 6, 7)
(Notes 6, 8)
(Notes 6, 8)
Maximum High Level
Dynamic Input Voltage
Maximum Low Level
Dynamic Input Voltage
1.7
0.8
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V ), 0V to threshold (V ),
ILD IHD
=
f
1 MHz.
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2
AC Electrical Characteristics
=
=
TA −40˚C to +85˚C
VCC
(V)
TA +25˚C
Symbol
Parameter
Units
=
=
CL 50 pF
CL 50 pF
Min
1.5
1.5
1.5
1.5
Typ
6.0
5.0
6.0
5.0
1.0
1.0
Max
10.6
7.5
Min
Max
12.0
8.0
tPLH
Propagation Delay
2.7
1.0
1.0
1.0
1.0
±
3.3 0.3
ns
tPHL
Propagation Delay
2.7
10.6
7.5
12.0
8.0
±
3.3 0.3
ns
ns
tOSHL,
tOSLH
Output to Output Skew (Note 9)
Data to Output
2.7
1.5
1.5
±
3.3 0.3
1.5
1.5
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (t
) or LOW to HIGH (t
). Parameter guaranteed by design.
OSHL
OSLH
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
20
Units
pF
Conditions
=
VCC Open
CIN
CPD (Note 10)
Note 10: is measured at 10 MHz.
=
pF
VCC 3.3V
C
PD
3
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead (0.150" Wide) Molded Small Outline Integrated Circuit, SOIC JEDEC
Package Number M14A
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package, SOIC EIAJ
Package Number M14D
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to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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