74LS163FC [FAIRCHILD]
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| 型号： | 74LS163FC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 暂无描述 计数器 |
| 文件： | 总10页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1986
Revised April 2000
DM74LS161A • DM74LS163A
Synchronous 4-Bit Binary Counters
The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous applications without addi-
tional gating. Instrumental in accomplishing this function
are two count-enable inputs and a ripple carry output.
General Description
These synchronous, presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs. The DM74LS161A and DM74LS163A are 4-bit
binary counters. The carry output is decoded by means of
a NOR gate, thus preventing spikes during the normal
counting mode of operation. Synchronous operation is pro-
vided by having all flip-flops clocked simultaneously so that
the outputs change coincident with each other when so
instructed by the count-enable inputs and internal gating.
This mode of operation eliminates the output counting
spikes which are normally associated with asynchronous
(ripple clock) counters. A buffered clock input triggers the
four flip-flops on the rising (positive-going) edge of the
clock input waveform.
Both count-enable inputs (P and T) must be HIGH to count,
and input T is fed forward to enable the ripple carry output.
The ripple carry output thus enabled will produce a high-
level output pulse with a duration approximately equal to
the high-level portion of the QA output. This high-level over-
flow ripple carry pulse can be used to enable successive
cascaded stages. HIGH-to-LOW level transitions at the
enable P or T inputs may occur, regardless of the logic
level of the clock.
These counters feature a fully independent clock circuit.
Changes made to control inputs (enable P or T or load) that
will modify the operating mode have no effect until clocking
occurs. The function of the counter (whether enabled, dis-
abled, loading, or counting) will be dictated solely by the
conditions meeting the stable set-up and hold times.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse, regardless of the levels of the enable
input. The clear function for the DM74LS161A is asynchro-
nous; and a low level at the clear input sets all four of the
flip-flop outputs LOW, regardless of the levels of clock,
load, or enable inputs. The clear function for the
DM74LS163A is synchronous; and a low level at the clear
inputs sets all four of the flip-flop outputs LOW after the
next clock pulse, regardless of the levels of the enable
inputs. This synchronous clear allows the count length to
be modified easily, as decoding the maximum count
desired can be accomplished with one external NAND
gate. The gate output is connected to the clear input to
synchronously clear the counter to all low outputs.
Features
■ Synchronously programmable
■ Internal look-ahead for fast counting
■ Carry output for n-bit cascading
■ Synchronous counting
■ Load control line
■ Diode-clamped inputs
■ Typical propagation time, clock to Q output 14 ns
■ Typical clock frequency 32 MHz
■ Typical power dissipation 93 mW
Ordering Code:
Order Number Package Number
Package Description
DM74LS161AM
DM74LS161AN
DM74LS163AM
DM74LS163AN
M16A
N16E
M16A
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation
DS006397
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Connection Diagram
Logic Diagram
DM74LS163A
The DM74LS161A is similar, however, the clear buffer is connected directly to the flip-flops.
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2
Parameter Measurement Information
Switching Time Waveforms
The input pulses are supplied by generators having the following characteristics:
PRR ≤ 1 MHz, duty cycle ≤ 50%, Z ≈ 50Ω, t ≤ 10 ns, t ≤ 10 ns.
OUT
R
F
Vary PRR to measure f
.
MAX
Outputs Q and carry are tested at t
where t is the bit time when all outputs are LOW.
N+16 N
D
V
= 1.5V.
REF
Switching Time Waveforms
The input pulses are supplied by generators having the following characteristics:
PRR ≤ 1 MHz, duty cycle ≤ 50%, Z ≈ 50Ω, t ≤ 6 ns, t ≤ 6 ns. Vary PRR to measure f .
MAX
OUT
R
F
Enable P and enable T setup times are measured at t
.
N+0
V
= 1.3V.
REF
3
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Timing Diagram
LS161A, LS163A Synchronous Binary Counters
Typical Clear, Preset, Count and Inhibit Sequences
Sequence:
(1) Clear outputs to zero
(2) Preset to binary twelve
(3) Count to thirteen, fourteen, fifteen, zero, one, and two
(4) Inhibit
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4
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
Storage Temperature Range
0°C to +70°C
−65°C to +150°C
DM74LS161A Recommended Operating Conditions
Symbol
Parameter
Min
4.75
2
Nom
Max
Units
V
VCC
VIH
VIL
Supply Voltage
5
5.25
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency (Note 2)
Clock Frequency (Note 3)
V
0.8
−0.4
8
V
IOH
IOL
mA
mA
MHz
MHz
fCLK
0
0
25
20
tW
Pulse Width
(Note 2)
Clock
Clear
20
20
25
25
20
25
25
20
30
30
0
6
9
ns
ns
Pulse Width
(Note 3)
Clock
Clear
tSU
Setup Time
(Note 2)
Data
8
Enable P
Load
17
15
ns
ns
Setup Time
(Note 3)
Data
Enable P
Load
tH
Hold Time
(Note 2)
Data
−3
−3
ns
ns
Others
Data
0
Hold Time
(Note 3)
5
Others
5
tREL
Clear Release Time (Note 2)
Clear Release Time (Note 3)
Free Air Operating Temperature
20
25
0
ns
ns
°C
TA
70
Note 2: C = 15 pF, R = 2 kΩ, T = 25°C and V = 5.5V.
L
L
A
CC
Note 3: C = 50 pF, R = 2 kΩ, T = 25°C and V = 5.5V.
L
L
A
CC
5
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DM74LS161A Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
= Min, I = −18 mA
Min
Max
Units
(Note 4)
V
V
Input Clamp Voltage
HIGH Level
V
V
V
V
V
−1.5
V
V
I
CC
I
= Min, I = Max
OH
CC
OH
2.7
3.4
Output Voltage
LOW Level
= Max, V = Min
IH
IL
V
= Min, I = Max
OL
OL
CC
0.35
0.25
0.5
Output Voltage
= Max, V = Min
V
IL
IH
I
= 4 mA, V = Min
0.4
0.2
0.2
0.2
0.1
40
OL
CC
I
I
I
Input Current @ Max
Input Voltage
V
= Max
Enable T
Clock
I
CC
V = 7V
I
mA
Load
Others
Enable T
Clock
HIGH Level
V
= Max
IH
IL
CC
Input Current
V = 2.7V
40
I
µA
Load
40
Others
Enable T
Clock
20
LOW Level
V
= Max
−0.8
−0.8
−0.8
−0.4
−100
31
CC
Input Current
V = 0.4V
I
mA
Load
Others
I
I
I
Short Circuit Output Current
V
V
V
= Max (Note 5)
= Max (Note 6)
= Max (Note 7)
−20
mA
mA
mA
OS
CC
CC
CC
Supply Current with Outputs HIGH
Supply Current with Outputs LOW
18
19
CCH
CCL
32
Note 4: All typicals are at V = 5V, T = 25°C.
CC
A
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 6: I
Note 7: I
is measured with the load HIGH, then again with the load LOW, with all other inputs HIGH and all outputs OPEN.
CCH
CCL
is measured with the clock input HIGH, then again with the clock input LOW, with all other inputs LOW and all outputs OPEN.
DM74LS161A Switching Characteristics
at VCC = 5V and T = 25°C
A
From (Input)
R = 2 kΩ
L
Symbol
Parameter
To (Output)
C
= 15 pF
C
= 50 pF
Units
L
L
Min
25
Max
Min
20
Max
f
t
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
MHz
ns
MAX
Clock to
Ripple Carry
Clock to
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PHL
25
30
22
27
24
27
14
15
28
30
38
27
38
30
38
27
27
45
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
Ripple Carry
Clock to Any Q
(Load HIGH)
Clock to Any Q
(Load HIGH)
Clock to Any Q
(Load LOW)
Clock to Any Q
(Load LOW)
Enable T to
Ripple Carry
Enable T to
Ripple Carry
Clear to
Any Q
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6
DM74LS163A Recommended Operating Conditions
Symbol
Parameter
Min
4.75
2
Nom
Max
Units
V
V
V
V
Supply Voltage
5
5.25
CC
IH
IL
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency (Note 8)
Clock Frequency (Note 9)
Pulse Width
V
0.8
−0.4
8
V
I
I
f
mA
mA
MHz
MHz
OH
OL
0
0
25
CLK
20
t
Clock
Clear
20
20
25
25
20
25
25
20
30
30
0
6
9
W
ns
ns
(Note 8)
Pulse Width
Clock
Clear
(Note 9)
t
Setup Time
Data
8
SU
(Note 8)
Enable P
Load
17
15
ns
ns
Setup Time
(Note 9)
Data
Enable P
Load
t
t
Hold Time
Data
−3
−3
H
ns
ns
(Note 8)
Others
Data
0
Hold Time
5
(Note 9)
Others
5
Clear Release Time (Note 8)
Clear Release Time (Note 9)
Free Air Operating Temperature
20
25
0
ns
ns
°C
REL
T
70
A
Note 8: C = 15 pF, R = 2 kΩ, T = 25°C and V = 5V.
L
L
A
CC
Note 9: C = 50 pF, R = 2 kΩ, T = 25°C and V = 5V.
L
L
A
CC
DM74LS163A Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
(Note 10)
Symbol
Parameter
Conditions
= Min, I = −18 mA
Min
Max
Units
V
V
Input Clamp Voltage
HIGH Level
V
V
V
V
V
−1.5
V
V
I
CC
CC
I
= Min, I = Max
OH
OH
2.7
3.4
Output Voltage
LOW Level
= Max, V = Min
IH
IL
V
= Min, I = Max
OL
OL
CC
0.35
0.25
0.5
Output Voltage
= Max, V = Min
V
IL
IH
I
= 4 mA, V = Min
0.4
0.2
0.2
0.2
0.1
40
OL
CC
I
I
I
Input Current @ Max
Input Voltage
V
= Max
CC
Enable T
Clock, Clear
Load
I
V = 7V
I
mA
Others
HIGH Level
V
= Max
CC
Enable T
Load
IH
IL
Input Current
V = 2.7V
40
I
µA
Clock, Clear
Others
40
20
LOW Level
V
= Max
Enable T
Clock, Clear
Load
−0.8
−0.8
−0.8
−0.4
−100
31
CC
Input Current
V = 0.4V
I
mA
Others
I
I
I
Short Circuit Output Current
V
V
V
= Max (Note 11)
= Max (Note 12)
= Max (Note 13)
−20
mA
mA
mA
OS
CC
CC
CC
Supply Current with Outputs HIGH
Supply Current with Outputs LOW
18
18
CCH
32
CCL
Note 10: All typicals are at V = 5V, T = 25°C.
CC
A
Note 11: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 12: I
Note 13: I
is measured with the load HIGH, then again with the load LOW, with all other inputs HIGH and all outputs OPEN.
CCH
CCL
is measured with the clock input HIGH, then again with the clock input LOW, with all other inputs LOW and all outputs OPEN.
7
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DM74LS163A Switching Characteristics
at VCC = 5V and T = 25°C
A
R
= 2 kΩ
From (Input)
L
C
= 15 pF
C = 50 pF
L
Symbol
Parameter
To (Output)
Units
L
Min
25
Max
Min
20
Max
f
t
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
MHz
ns
MAX
Clock to
Ripple Carry
Clock to
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PHL
25
30
22
27
24
27
14
15
28
30
38
27
38
30
38
27
27
45
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
Ripple Carry
Clock to Any Q
(Load HIGH)
Clock to Any Q
(Load HIGH)
Clock to Any Q
(Load LOW)
Clock to Any Q
(Load LOW)
Enable T to
Ripple Carry
Enable T to
Ripple Carry
Clear to Any Q
(Note 14)
Note 14: The propagation delay clear to output is measured from the clock input transition.
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8
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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