74LCX541WM_08
更新时间:2024-09-18 12:53:17
品牌:FAIRCHILD
描述:Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
74LCX541WM_08 概述
Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs 低电压与5V容限输入和输出的八路缓冲器/线路驱动器
74LCX541WM_08 数据手册
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PDF下载February 2008
74LCX541
Low Voltage Octal Buffer/Line Driver
with 5V Tolerant Inputs and Outputs
Features
General Description
■ 5V tolerant input and outputs
The LCX541 is an octal buffer/line driver designed to be
employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers. The LCX541 is a
non inverting option of the LCX540.
■ 2.3V–3.6V V specifications provided
CC
■ 6.5ns t max (V = 3.3V), 10µA I max
PD
CC
CC
■ Power-down high impedance inputs and outputs
(1)
This device is similar in function to the LCX244 while
providing flow-through architecture (inputs on opposite
side from outputs). This pinout arrangement makes this
device especially useful as an output port for micropro-
cessors, allowing ease of layout and greater PC board
density.
■ Supports live insertion/withdrawal
■
24 mA output drive (V = 3.0V)
CC
■ Implements proprietary noise/ EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance
– Human body model > 2000V
The LCX541 is designed for low voltage applications
with capability of interfacing to a 5V signal environment.
The LCX541 is fabricated with an advanced CMOS
technology to achieve high speed operation while
maintaining CMOS low power dissipation.
– Machine model > 200V
■ Leadless DQFN package
Note:
1. To ensure the high impedance state during power up
or down, OE should be tied to V through a pull-up
CC
resistor: the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
Ordering Information
Package
Order Number
74LCX541WM
74LCX541SJ
Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M20D
(2)
74LCX541BQX
MLP20B 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 4.5mm
74LCX541MSA
74LCX541MTC
MSA20
MTC20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
Connection Diagrams
Logic Symbol
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
IEEE/IEC
&
OE1
OE2
EN
20
19
18
17
16
15
14
13
12
11
1
2
OE1
VCC
OE2
O0
I0
I1
3
I0
I1
I2
I3
I4
I5
I6
I7
O0
O1
O2
O3
O4
O5
O6
O7
4
I2
I3
I4
I5
O1
O2
O3
O4
5
6
7
8
I6
I7
GND
O5
O6
9
10
O7
Truth Table
Pad Assignment for DQFN
VCC
20
OE1
1
Inputs
Outputs
OE
L
OE
L
I
O
n
1
2
19
18
17
16
15
14
13
12
I0
I1
I2
I3
I4
I5
I6
I7
2
3
4
5
6
7
8
9
OE2
O0
O1
O2
O3
O4
O5
O6
H
X
X
L
H
H
X
Z
Z
L
X
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
10
11
GND O7
(Top View)
Pin Descriptions
Pin Names
Description
3-STATE Output Enable Inputs
Inputs
OE , OE
1
2
I –I
0
7
O –O
Outputs
0
7
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Conditions
Value
Units
V
Supply Voltage
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +7.0
V
V
V
CC
V
DC Input Voltage
I
V
DC Output Voltage
Output in 3-STATE
Output in HIGH or LOW State
V < GND
O
(3)
–0.5 to V + 0.5
CC
I
DC Input Diode Current
DC Output Diode Current
–50
–50
mA
mA
IK
I
I
I
V < GND
O
OK
V
> V
+50
O
CC
I
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±50
mA
mA
mA
°C
O
±100
CC
I
±100
GND
T
–65 to +150
STG
(4)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Conditions
Min.
2.0
1.5
0
Max.
3.6
Units
V
Supply Voltage
Operating
V
CC
Data Retention
3.6
V
Input Voltage
5.5
V
V
I
V
Output Voltage
HIGH or LOW State
3-STATE
0
V
CC
O
0
5.5
±24
±12
±8
I
/I
Output Current
V
V
V
= 3.0V–3.6V
= 2.7V–3.0V
= 2.3V–2.7V
mA
OH OL
CC
CC
CC
T
Free-Air Operating Temperature
Input Edge Rate
–40
0
85
°C
A
∆t/∆V
V
= 0.8V–2.0V, V = 3.0V
10
ns/V
IN
CC
Notes:
3. I Absolute Maximum Rating must be observed.
O
4. Unused inputs must be held HIGH or LOW. They may not float.
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
3
DC Electrical Characteristics
T = –40°C to +85°C
A
Symbol
Parameter
V
(V)
Conditions
Min.
1.7
Max.
Units
CC
V
HIGH Level Input Voltage
2.3–2.7
2.7–3.6
2.3–2.7
2.7–3.6
2.3–3.6
2.3
V
IH
2.0
V
V
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
V
V
IL
I
I
I
I
I
I
I
I
I
I
= –100µA
= –8mA
= –12mA
= –18mA
= –24mA
= 100µA
= 8mA
V
– 0.2
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
CC
1.8
2.2
2.4
2.2
2.7
3.0
V
LOW Level Output Voltage
2.3–3.6
2.3
0.2
0.6
V
OL
2.7
= 12mA
= 16mA
= 24mA
0.4
3.0
0.4
0.55
±5.0
10
I
I
I
Input Leakage Current
2.3–3.6
0
0 ≤ V ≤ 5.5V
µA
µA
µA
I
I
Power-Off Leakage Current
Quiescent Supply Current
V or V = 5.5V
I O
OFF
CC
2.3–3.6
V = V or GND
10
I
CC
(5)
3.6V ≤ V , V ≤ 5.5V
±10
500
I
O
∆I
Increase in I per Input
2.3–3.6
V
= V = 0.6V
µA
CC
CC
IH
CC
AC Electrical Characteristics
T = –40°C to +85°C, R = 500Ω
A
L
V
= 3.3V ± 0.3V,
V
= 2.7V,
V
= 2.5V ± 0.2V,
CC
CC
CC
C = 50pF
C = 50pF
C = 30pF
L
L
L
Symbol
Parameter
Propagation Delay
Output Enable Time
Output Disable Time
Output to Output Skew
Min.
1.5
Max.
6.5
Min.
Max.
7.5
Min.
1.5
Max. Units
t
t
t
t
, t
1.5
1.5
1.5
7.8
10.5
9.0
ns
ns
ns
ns
PHL PLH
, t
1.5
8.5
9.5
1.5
PZL PZH
, t
1.5
7.5
8.5
1.5
PLZ PHZ
(6)
, t
1.0
OSHL OSLH
Notes
5. Outputs disabled or 3-STATE only.
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (t
) or LOW-to-HIGH (t
).
OSHL
OSLH
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
4
Dynamic Switching Characteristics
T = 25°C
A
Symbol
Parameter
V
(V)
Conditions
Typical
0.8
Units
CC
V
Quiet Output Dynamic Peak V
3.3
C = 50 pF, V = 3.3V, V = 0V
V
OLP
OL
L
IH
IL
2.5
3.3
2.5
C = 30 pF, V = 2.5V, V = 0V
0.6
L
IH
IL
V
Quiet Output Dynamic Valley V
C = 50 pF, V = 3.3V, V = 0V
–0.8
–0.6
V
OLV
OL
L
IH
IL
C = 30 pF, V = 2.5V, V = 0V
L
IH
IL
Capacitance
Symbol
Parameter
Conditions
Typical Units
C
C
C
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
V
V
V
= Open, V = 0V or V
CC
7
8
pF
pF
pF
IN
CC
CC
CC
I
= 3.3V, V = 0V or V
CC
OUT
PD
I
= 3.3V, V = 0V or V , f = 10 MHz
25
I
CC
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
5
AC Loading and Waveforms (Generic for LCX Family)
V
CC
OPEN
GND
t
t
t
, t
PLH PHI
500Ω
TEST
, t
PZH PHZ
DUT
SIGNAL
V
, t
PZL PLZ
I
C
L
500Ω
Figure 1. AC Test Circuit (C includes probe and jig capacitance)
L
Test
Switch
t
, t
Open
PLH PHL
t
, t
6V at V = 3.3 ± 0.3V
CC
PZL PLZ
V
x 2 at V = 2.5 ± 0.2V
CC
CC
t
, t
GND
PZH PHZ
V
CC
V
CC
DATA
IN
OUTPUT
V
mi
V
V
mi
CONTROL
GND
GND
t
t
pxx
pxx
t
t
PLZ
PZL
DATA
OUT
DATA
OUT
mo
V
mo
V
X
V
OL
3-STATE Output High Enable and
Disable Times for Logic
Waveform for Inverting and
Non-Inverting Functions
t
V
W
CC
DATA
V
V
mi
CC
CONTROL
IN
IN
V
GND
mi
GND
t
S
t
H
t
rec
V
CC
CONTROL
INPUT
V
mi
GND
V
CLOCK
mi
t
S
t
PHL
t
rec
t
PLH
V
MR
OR
CLEAR
V
mi
V
mo
OUTPUT
mo
Setup Time, Hold Time and
Recovery Time for Logic
Propagation Delay, Pulse Width and
t
Waveforms
rec
t
t
f
r
V
CC
OUTPUT
CONTROL
V
mi
GND
V
V
OH
OL
t
t
90%
90%
10%
PZH
PHZ
ANY
OUTPUT
V
V
OH
Y
DATA
OUT
10%
V
mo
t
and t
fall
rise
3-STATE Output Low Enable and
Disable Times for Logic
Figure 2. Waveforms (Input Characteristics; f = 1MHz, t = t = 3ns)
r
f
V
CC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
1.5V
2.5V ± 0.2V
V
V
V
/ 2
/ 2
mi
CC
V
1.5V
mo
CC
V
V
+ 0.3V
– 0.3V
V
+ 0.3V
V
+ 0.15V
– 0.15V
x
y
OL
OL
OL
V
V
V
– 0.3V
V
OH
OH
OH
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
6
Schematic Diagram (Generic for LCX Family)
Input Stage
P2
P1
V
CC
Data
ESD
P5
X1
D2 N+/P–
V
DD
N1
N2
P4
GTO™
Output
Input Stage
D6
N+/P–
P3
N5
Enable
N4
ESD
D4 N+/P–
N3
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
7
Tape and Reel Specification
Tape Format for DQFN
Package
Designator
Tape
Section
Number
Cavities
Cavity
Status
Cover Tape
Status
BQX
Leader (Start End)
Carrier
125 (typ)
3000
Empty
Filled
Sealed
Sealed
Sealed
Trailer (Hub End)
75 (typ)
Empty
Tape Dimensions inches (millimeters)
Reel Dimensions inches (millimeters)
Tape Size
A
B
C
D
N
W1
W2
12mm
13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4)
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
8
Physical Dimensions
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
PIN ONE
INDICATOR
10
0.65
0.51
0.35
1.27
1.27
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10
C
0.30
0.10
SEATING PLANE
0.75
0.25
X 45°
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
GAGE PLANE
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.25
8°
0°
D) CONFORMS TO ASME Y14.5M-1994
1.27
0.40
SEATING PLANE
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
(1.40)
DETAIL A
SCALE: 2:1
Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
9
Physical Dimensions (Continued)
Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
10
Physical Dimensions (Continued)
Figure 5. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
11
Physical Dimensions (Continued)
Figure 6. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
12
Physical Dimensions (Continued)
Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
13
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global
subsidiaries, and is not intended to be an exhaustive list of all such trademarks.
ACEx®
PDP-SPM™
SupreMOS™
FPS™
Power220®
SyncFET™
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
FRFET®
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
®
Global Power ResourceSM
Green FPS™
Green FPS™e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
The Power Franchise®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™
UHC®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
®
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
FAST®
Ultra FRFET™
UniFET™
VCX™
OPTOPLANAR®
FastvCore™
®
FlashWriter® *
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I33
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.0
www.fairchildsemi.com
14
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74LCX541_08 | FAIRCHILD | Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs | 获取价格 | |
74LCX543 | FAIRCHILD | Low Voltage Octal Registered Transceiver with 5V Tolerant Inputs and Outputs | 获取价格 | |
74LCX543CW | FAIRCHILD | Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 8-Bit, True Output, CMOS | 获取价格 | |
74LCX543MSA | FAIRCHILD | Low Voltage Octal Registered Transceiver with 5V Tolerant Inputs and Outputs | 获取价格 | |
74LCX543MSA | TI | LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, EIAJ TYPE2, PLASTIC, SSOP-24 | 获取价格 | |
74LCX543MSA | ROCHESTER | 暂无描述 | 获取价格 | |
74LCX543MSA | ONSEMI | 低压八路注册收发器(5V容差输入和输出) | 获取价格 | |
74LCX543MSAX | FAIRCHILD | Single 8-bit Bus Transceiver | 获取价格 |
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