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74LCX16244MTD_NL [FAIRCHILD]

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74LCX16244MTD_NL
型号： 74LCX16244MTD_NL
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
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February 1994  
Revised May 2005  
74LCX16244  
Low Voltage 16-Bit Buffer/Line Driver  
with 5V Tolerant Inputs and Outputs  
General Description  
Features  
■ 5V tolerant inputs and outputs  
The LCX16244 contains sixteen non-inverting buffers with  
3-STATE outputs designed to be employed as a memory  
and address driver, clock driver, or bus oriented transmit-  
ter/receiver. The device is nibble controlled. Each nibble  
has separate 3-STATE control inputs which can be shorted  
together for full 16-bit operation.  
■ 2.3V to 3.6V VCC specifications provided  
■ 4.5 ns tPD max, 10 A ICCQ max  
■ Power down high impedance inputs and outputs  
■ Supports live insertion/withdrawal (Note 1)  
The LCX16244 is designed for low voltage (2.5 or 3.3V)  
■
24 mA output drive (VCC 3.0V)  
VCC applications with capability of interfacing to a 5V signal  
■ Uses patented noise/EMI reduction circuitry  
■ Latch-up performance exceeds 500 mA  
■ ESD performance:  
environment.  
The LCX16244 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Human body model 2000V  
Machine model 200V  
■ Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA)  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to V  
through a pull-up resistor: the minimum value or the  
CC  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74LCX16244G  
(Note 2)(Note 3)  
BGA54A  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
74LCX16244MEA  
(Note 3)  
MS48A  
MTD48  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LCX16244MTD  
(Note 3)  
Note 2: Ordering code “G” indicates Trays.  
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
GTO is a trademark of Fairchild Semiconductor Corporation.  
© 2005 Fairchild Semiconductor Corporation  
DS012000  
www.fairchildsemi.com  
Connection Diagrams  
Pin Descriptions  
Pin Names  
Description  
Pin Assignment for SSOP and TSSOP  
OEn  
Output Enable Input (Active LOW)  
I0–I15  
O0–O15  
NC  
Inputs  
Outputs  
No Connect  
FBGA Pin Assignments  
1
2
3
4
5
6
A
B
C
D
E
F
O0  
O2  
NC  
O1  
OE1  
NC  
OE2  
NC  
NC  
I1  
I0  
I2  
O4  
O3  
VCC  
GND  
GND  
GND  
VCC  
NC  
VCC  
GND  
GND  
GND  
VCC  
NC  
I3  
I4  
O6  
O5  
I5  
I6  
O8  
O7  
I7  
I8  
O10  
O12  
O14  
O9  
I9  
I10  
I12  
I14  
G
H
O11  
O13  
I11  
I13  
J
O15  
NC  
OE4  
OE3  
NC  
I15  
Truth Tables  
Inputs  
Outputs  
O0–O3  
OE1  
I0–I3  
L
L
L
H
X
L
H
Z
Pin Assignment for FBGA  
H
Inputs  
Inputs  
Inputs  
Outputs  
O4–O7  
OE2  
I4–I7  
L
L
L
H
X
L
H
Z
H
Outputs  
O8–O11  
OE3  
I8–I11  
L
L
L
H
X
L
H
Z
H
(Top Thru View)  
Outputs  
O12–O15  
OE4  
I12–I15  
L
L
L
H
X
L
H
Z
H
H
L
X
Z
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
High Impedance  
www.fairchildsemi.com  
2
Functional Description  
The LCX16244 contains sixteen non-inverting buffers with  
3-STATE standard outputs. The device is nibble (4 bits)  
controlled with each nibble functioning identically, but inde-  
pendent of the other. The control pins can be shorted  
together to obtain full 16-bit operation. The 3-STATE out-  
puts are controlled by an Output Enable (OEn) input for  
each nibble. When OEn is LOW, the outputs are in 2-state  
mode. When OEn is HIGH, the outputs are in the high  
impedance mode, but this does not interfere with entering  
new data into the inputs.  
Logic Diagram  
3
www.fairchildsemi.com  
Absolute Maximum Ratings(Note 4)  
Symbol  
VCC  
VI  
Parameter  
Supply Voltage  
Value  
Conditions  
Units  
0.5 to 7.0  
0.5 to 7.0  
0.5 to 7.0  
V
V
DC Input Voltage  
VO  
DC Output Voltage  
Output in 3-STATE  
V
0.5 to VCC 0.5 Output in HIGH or LOW State (Note 5)  
IIK  
DC Input Diode Current  
DC Output Diode Current  
50  
50  
VI GND  
VO GND  
VO VCC  
mA  
mA  
IOK  
50  
IO  
DC Output Source/Sink Current  
DC Supply Current per Supply Pin  
DC Ground Current per Ground Pin  
Storage Temperature  
50  
mA  
mA  
mA  
C
ICC  
100  
IGND  
TSTG  
100  
65 to 150  
Recommended Operating Conditions (Note 6)  
Symbol  
Parameter  
Min  
2.0  
1.5  
0
Max  
3.6  
3.6  
5.5  
VCC  
5.5  
24  
Units  
VCC  
Supply Voltage  
Operating  
V
V
V
Data Retention  
VI  
Input Voltage  
VO  
Output Voltage  
HIGH or LOW State  
3-STATE  
0
0
IOH/IOL  
Output Current  
VCC 3.0V 3.6V  
VCC 2.7V 3.0V  
VCC 2.3V 2.7V  
12  
mA  
8
TA  
Free-Air Operating Temperature  
40  
0
85  
C
t/ V  
Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V  
10  
ns/V  
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated  
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-  
mended Operating Conditions” table will define the conditions for actual device operation.  
Note 5: I Absolute Maximum Rating must be observed.  
O
Note 6: Unused inputs must be held HIGH or LOW. They may not float.  
DC Electrical Characteristics  
V
T
40 C to 85 C  
Min Max  
CC  
A
Symbol  
Parameter  
Conditions  
Units  
(V)  
2.3 2.7  
2.7 3.6  
2.3 2.7  
2.7 3.6  
2.3 3.6  
2.3  
V
V
V
HIGH Level Input Voltage  
1.7  
2.0  
IH  
V
V
LOW Level Input Voltage  
HIGH Level Output Voltage  
0.7  
IL  
0.8  
I
100  
A
V
CC  
0.2  
OH  
OH  
I
8 mA  
1.8  
2.2  
2.4  
2.2  
OH  
I
12 mA  
18 mA  
24 mA  
2.7  
V
V
OH  
I
3.0  
OH  
I
3.0  
OH  
V
LOW Level Output Voltage  
I
100  
8 mA  
A
2.3 3.6  
2.3  
0.2  
0.6  
0.4  
0.4  
0.55  
5.0  
5.0  
OL  
OL  
I
OL  
I
12 mA  
16 mA  
24 mA  
2.7  
OL  
I
3.0  
OL  
I
3.0  
OL  
I
I
Input Leakage Current  
0
0
V
V
V
5.5V  
5.5V  
2.3 3.6  
2.3 3.6  
A
A
A
I
I
3-STATE Output Leakage  
OZ  
O
V
or V  
IL  
I
IH  
I
Power-Off Leakage Current  
V or V  
O
5.5V  
0
10  
OFF  
I
www.fairchildsemi.com  
4
DC Electrical Characteristics (Continued)  
V
T
40 C to 85 C  
CC  
A
Symbol  
Parameter  
Conditions  
V or GND  
CC  
Units  
(V)  
Min  
Max  
20  
I
Quiescent Supply Current  
V
2.3 3.6  
2.3 3.6  
2.3 3.6  
CC  
I
A
A
3.6V V , V  
5.5V (Note 7)  
20  
I
O
I
Increase in I per Input  
V
V 0.6V  
CC  
500  
CC  
CC  
IH  
Note 7: Outputs disabled or 3-STATE only.  
AC Electrical Characteristics  
T
40 C to 85 C, R  
500  
A
L
V
3.3V 0.3V  
50 pF  
V
2.7V  
V
2.5 0.2V  
C 30 pF  
L
CC  
CC  
CC  
Symbol  
Parameter  
Units  
C
C
50 pF  
L
L
Min  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
Max  
4.5  
4.5  
5.5  
5.5  
5.4  
5.4  
1.0  
1.0  
Min  
Max  
5.2  
5.2  
6.3  
6.3  
5.7  
5.7  
Min  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
Max  
5.4  
5.4  
7.2  
7.2  
6.5  
6.5  
t
Propagation Delay  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
PHL  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
Data to Output  
PLH  
Output Enable Time  
PZL  
PZH  
PLZ  
Output Disable Time  
PHZ  
OSHL  
OSLH  
Output to Output Skew (Note 8)  
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The  
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t  
) or LOW-to-HIGH (t  
).  
OSLH  
OSHL  
Dynamic Switching Characteristics  
V
T
25 C  
CC  
A
Symbol  
Parameter  
Conditions  
Unit  
V
(V)  
3.3  
2.5  
3.3  
2.5  
Typical  
0.8  
V
V
Quiet Output Dynamic Peak V  
C
C
C
C
50 pF, V  
3.3V, V  
0V  
0V  
0V  
0V  
OLP  
OL  
L
L
L
L
IH  
IL  
30pF, V  
2.5V, V  
0.6  
IH  
IL  
Quiet Output Dynamic Valley V  
50 pF, V  
30pF, V  
3.3V, V  
2.5V, V  
0.8  
OLV  
OL  
IH  
IL  
V
0.6  
IH  
IL  
Capacitance  
Symbol  
Parameter  
Conditions  
Typical  
Units  
pF  
C
Input Capacitance  
Output Capacitance  
Power Dissipation Capacitance  
V
V
V
Open, V 0V or V  
CC  
7
8
IN  
CC  
CC  
CC  
I
C
C
3.3V, V 0V or V  
CC  
pF  
OUT  
PD  
I
3.3V, V 0V or V , f 10 MHz  
20  
pF  
I
CC  
5
www.fairchildsemi.com  
AC LOADING and WAVEFORMS Generic for LCX Family  
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)  
Test  
PLH, tPHL  
PZL, tPLZ  
Switch  
Open  
t
t
6V at VCC 3.3 0.3V  
VCC x 2 at VCC 2.5 0.2V  
tPZH,tPHZ  
GND  
3-STATE Output High Enable and  
Waveform for Inverting and Non-Inverting Functions  
Disable Times for Logic  
Setup Time, Hold Time and Recovery Time for Logic  
Propagation Delay. Pulse Width and trec Waveforms  
trise and tfall  
3-STATE Output Low Enable and  
Disable Times for Logic  
FIGURE 2. Waveforms  
(Input Characteristics; f =1MHz, tR = tF = 3ns)  
VCC  
Symbol  
3.3V 0.3V  
1.5V  
2.7V  
1.5V  
2.5V 0.2V  
VCC/2  
Vmi  
Vmo  
Vx  
1.5V  
1.5V  
VCC/2  
VOL 0.3V  
VOH 0.3V  
VOL 0.3V  
VOH 0.3V  
VOL 0.15V  
VOH 0.15V  
Vy  
www.fairchildsemi.com  
6
Schematic Diagram Generic for LCX Family  
7
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
Package Number BGA54A  
www.fairchildsemi.com  
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
Package Number MS48A  
9
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Package Number MTD48  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
www.fairchildsemi.com  
10  

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