74LCX112SJX [FAIRCHILD]
J-K-Type Flip-Flop ; J- K型触发器\n型号: | 74LCX112SJX |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | J-K-Type Flip-Flop
|
文件: | 总9页 (文件大小:101K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
June 1998
Revised February 2001
74LCX112
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop
with 5V Tolerant Inputs
General Description
Features
■ 5V tolerant inputs
The LCX112 is a dual J-K flip-flop. Each flip-flop has inde-
pendent J, K, PRESET, CLEAR, and CLOCK inputs with Q,
Q outputs. These devices are edge sensitive and change
state on the negative going transition of the clock pulse.
Clear and preset are independent of the clock and accom-
plished by a low logic level on the corresponding input.
LCX devices are designed for low voltage (3.3V or 2.5)
operation with the added capability of interfacing to a 5V
signal environment.
■ 2.3V–3.6V VCC specifications provided
■ 7.5 ns tPD max (VCC = 3.3V), 10 µA ICC max
■ Power down high impedance inputs and outputs
■ ±24 mA output drive (VCC = 3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
The 74LCX112 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Human body model > 2000V
Machine model > 2000V
Ordering Code:
Order Number Package Number
Package Description
74LCX112M
M16A
M16D
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX112SJ
74LCX112MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
J1, J2, K1, K2
CP1, CP2
Description
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
C
D1, CD2
D1, SD2
Q1, Q2, Q1, Q2
S
© 2001 Fairchild Semiconductor Corporation
DS012424
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Truth Table
(Each half)
Inputs
CP
Outputs
SD
CD
J
K
Q
Q
L
H
L
H
L
L
X
X
X
X
X
X
X
X
X
H
L
L
H
H
H
H
H
H
H
H
H
h
l
h
h
l
QO
L
QO
H
h
H
L
H
H
H
H
l
l
QO
QO
QO
QO
H
X
X
H(h) = HIGH Voltage Level
L(l) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Clock Transition
QO(QO) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Symbol
VCC
VI
Parameter
Supply Voltage
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to VCC + 0.5
−50
Conditions
Units
V
DC Input Voltage
V
VO
DC Output Voltage
Output in HIGH or LOW State (Note 2)
V
IIK
DC Input Diode Current
DC Output Diode Current
VI < GND
mA
IOK
−50
V
V
O < GND
O > VCC
mA
+50
IO
DC Output Source/Sink Current
DC Supple Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±50
mA
mA
mA
°C
ICC
±100
IGND
TSTG
±100
−65 to 150
Recommended Operating Conditions (Note 3)
Symbol
Parameter
Min
2.0
1.5
0
Max
3.6
3.6
5.5
VCC
±24
±12
±8
Units
VCC
Supply Voltage
Operating
V
Data Retention
VI
Input Voltage
Output Voltage
Output Current
V
V
VO
HIGH or LOW State
0
I
OH/IOL
V
V
V
CC = 3.0V − 3.6V
CC = 2.7V − 3.0V
CC = 2.3V − 2.7V
mA
TA
Free-Air Operating Temperature
−40
85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V−2.0V, VCC = 3.0V
0
10
ns/V
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 2: IO Absolute Maximum rating must be observed.
Note 3: Unused Inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
TA = 40°C to +85°C
Symbol
VIH
Parameter
Conditions
Units
(V)
2.3 − 2.7
2.7 − 3.6
2.3 − 2.7
2.7 − 3.6
2.3 − 3.6
2.3
Min
1.7
2.0
Max
HIGH Level Input Voltage
V
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
0.7
VOH
I
I
I
I
I
I
OH = −100µA
OH = -8 mA
OH = −12 mA
OH = −18 mA
OH = −24 mA
OL = 100µA
VCC - 0.2
1.8
2.7
2.2
V
V
3.0
2.4
3.0
2.2
VOL
LOW Level Output Voltage
2.3 − 3.6
2.3
0.6
0.2
0.4
0.4
0.55
±5.0
10
IOL = 8mA
I
I
I
OL = 12 mA
OL = 16 mA
OL = 24 mA
2.7
3.0
3.0
II
Input Leakage Current
0 ≤ II ≤ 5.5V
2.3 − 3.6
0
µA
µA
µA
µA
µA
IOFF
ICC
Power-Off Leakage Current
Quiescent Supply Current
VI or VO = 5.5V
VI = VCC or GND
3.6V ≤ VI ≤ 5.5V
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
10
±10
500
∆ICC
Increase in ICC per Input
VIH = VCC −0.6V
3
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AC Electrical Characteristics
T
A = 40°C to 85°C, RL = 500Ω
CC = 2.7V
L = 50 pF
Max
V
CC = 3.3V ± 0.3V
CL=50 pF
V
VCC = 2.5V ± 0.2V
CL=30 pF
Symbol
Parameters
Units
C
Min
Max
Min
Min
150
1.5
1.5
1.5
1.5
4.0
2.0
Max
fMAX
Maximum Clock Frequency
Propagation Delay
CPn to Qn or Qn
150
1.5
1.5
1.5
1.5
2.5
1.5
150
1.5
1.5
1.5
1.7
2.5
1.5
MHz
ns
tPHL
tPLH
tPHL
tPLH
tS
7.5
7.5
7.0
7.0
8.0
8.0
8.0
8.0
9.0
9.0
8.4
8.4
Propagation Delay
CDn or SDn to Qn or Qn
Setup Time
ns
ns
ns
tH
Hold Time
tW
Pulse Width CP
3.3
3.3
4.0
ns
tW
Pulse Width (CD, SD
)
3.3
2.0
3.3
2.5
4.0
4.5
ns
ns
tREC
tOSHL
tOSLH
Recovery Time
Output to Output Skew
(Note 4)
1.0
1.0
ns
Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
VCC
TA = 25°C
Symbol
VOLP
Parameter
Conditions
Units
(V)
3.3
2.5
3.3
2.5
Typical
0.8
Quiet Output Dynamic Peak VOL
C
C
C
C
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
V
V
0.6
VOLV
Quiet Output Dynamic Valley VOL
−0.8
−0.6
Capacitance
Symbol
Parameter
Conditions
CC = Open, VI = 0V or VCC
Typical
Units
pF
CIN
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
V
V
V
7
8
COUT
CPD
CC = 3.3V, VI = 0V or VCC
pF
CC = 3.3V, VI = 0V or VCC, f = 10 MHz
25
pF
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4
AC Loading and Waveforms Generic for LCX Family
FIGURE 1. AC Test Circuit
(CL includes probe and jig capacitance)
Test
Switch
tPLH, tPHL
tPZL, tPLZ
Open
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH,tPHZ
GND
3-STATE Output Low Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold TIme and Recovery TIme for Logic
Propagation Delay, Pulse Width and trec Waveforms
3-STATE Output High Enable and
Disable TImes for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Pulse Characteristics; f=1MHz, tr=tf=3ns)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
2.5V ± 0.2V
VCC/2
Vmi
Vmo
Vx
1.5V
1.5V
VCC/2
V
OL + 0.3V
V
OL + 0.3V
VOL + 0.15V
Vy
V
OH − 0.3V
V
OH − 0.3V
VOH − 0.15V
5
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Schematic Diagram Generic for LCX Family
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6
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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