74F899PC [FAIRCHILD]
暂无描述;
FAIRCHILD SEMICONDUCTOR 
February 1989
Revised August 1999
74F899
9-Bit Latchable Transceiver
with Parity Generator/Checker
General Description
Features
■ Latchable transceiver with output sink of 24 mA at the
The 74F899 is a 9-bit to 9-bit parity transceiver with trans-
parent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit
data busses in either direction. It has a guaranteed current
sinking capability of 24 mA at the A-bus and 64 mA at the
B-bus.
A-bus and 64 mA at the B-bus
■ Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A
■ Independent latch enables for A-to-B and B-to-A
directions
The 74F899 features independent latch enables for the
A-to-B direction and the B-to-A direction, a select pin for
ODD/EVEN parity, and separate error signal output pins for
checking parity.
■ Select pin for ODD/EVEN parity
■ ERRA and ERRB output pins for parity checking
■ Ability to simultaneously generate and check parity
■ May be used in systems applications in place of the
74F543 and 74F280
■ May be used in system applications in place of the
74F657 and 74F373 (no need to change T/R to check
parity)
Ordering Code:
Order Number Package Number
Package Description
74F899SC
74F899QC
M28B
V28A
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignment for SOIC
Pin Assignment for PCC
Logic Symbol
© 1999 Fairchild Semiconductor Corporation
DS010195
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Input Loading/Fan-Out
HIGH/LOW
Input IIH/IIL
Pin Names
Description
U.L.
Output IOH/IOL
HIGH/LOW
1.0/1.0
A0–A7
B0–B7
APAR
BPAR
Data Inputs/
Data Outputs
20 µA/−0.6 mA
−3 mA/24 mA
20 µA/−0.6 mA
−12 mA/64 mA
20 µA/−0.6 mA
−3 mA/24 mA
20 µA/−0.6 mA
−12 mA/64 mA
20 µA/−0.6 mA
150/40
Data Inputs/
Data Outputs
A Bus Parity
Input/Output
B Bus Parity
Input/Output
Parity Select Input
1.0/1.0
600/106.6
1.0/1.0
150/40
1.0/1.0
600/106.6
1.0/1.0
ODD/EVEN
GBA, GAB
SEL
Output Enable Inputs
Mode Select Input
Latch Enable Inputs
Error Signal Outputs
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
LEA, LEB
ERRA, ERRB
Pin Descriptions
Pin Names
A0–A7
Description
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
B0–B7
APAR, BPAR
ODD/EVEN
GBA, GAB
SEL
ODD/EVEN Parity Select, Active LOW for EVEN Parity
Output Enables for A or B Bus, Active LOW
Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode
Latch Enables for A and B Latches, HIGH for Transparent Mode
LEA, LEB
ERRA, ERRB
Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs
Functional Description
The 74F899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
•
•
Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
•
Bus A (B) communicates to Bus B (A), parity is gener-
ated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B[0:7] (A[0:7]) can be checked
and monitored by ERRB (ERRA).
Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function
Table).
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2
Function Table
Inputs
Operation
GAB GBA SEL LEA LEB
H
H
H
L
X
L
X
L
X
H
Busses A and B are 3-STATE.
Generates parity from B[0:7] based on O/E (Note 1). Generated parity → APAR.
Generated parity checked against BPAR and output as ERRB.
H
L
L
H
H
Generates parity from B[0:7] based on O/E. Generated parity → APAR. Generated
parity checked against BPAR and output as ERRB. Generated parity also fed back
through the A latch for generate/check as ERRA.
H
H
H
L
L
L
L
H
H
X
X
H
L
Generates parity from B latch data based on O/E. Generated parity → APAR.
Generated parity checked against latched BPAR and output as ERRB.
H
H
BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked against
BPAR and output as ERRB.
BPAR/B[0:7] → APAR/A[0:7]
Feed-through mode. Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check as ERRA.
L
L
H
H
L
L
H
H
L
Generates parity for A[0:7] based on O/E. Generated parity → BPAR. Generated parity
checked against APAR and output as ERRA.
H
Generates parity from A[0:7] based on O/E. Generated parity → BPAR. Generated
parity checked against APAR and output as ERRA. Generated parity also fed back
through the B latch for generate/check as ERRB.
L
L
H
H
L
L
X
L
Generates parity from A latch data based on O/E. Generated parity → BPAR.
Generated parity checked against latched APAR and output as ERRA.
H
H
APAR/A[0:7] → BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as ERRA.
APAR/A[0:7] → BPAR/B[0:7]
L
H
H
H
H
Feed-through mode. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check as ERRB.
H = HIGH Voltage Level
Note 1: O/E = ODD/EVEN
L = LOW Voltage Level
X = Immaterial
Functional Block Diagram
3
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 3)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 3)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
3-STATE Output
−0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
Twice the Rated IOL (mA)
4000V
ESD Last Passing Voltage (Min)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
2.0
V
Recognized as a
HIGH Signal
IH
V
Input LOW Voltage
0.8
V
V
Recognized as a
LOW Signal
IL
V
V
Input Clamp Diode Voltage
−1.2
Min
I
I
I
I
I
I
I
= −18 mA
CD
IN
Output HIGH
Voltage
10% V
2.5
2.4
2.0
2.7
2.7
= −1 mA
= −3 mA
OH
CC
CC
CC
CC
CC
CC
OH
OH
OH
OH
OH
OL
10% V
10% V
5% V
V
V
= −15 mA (B , BPAR)
n
= −1 mA
= −3 mA
= 20 mA
5% V
V
Output LOW
Voltage
10% V
0.5
OL
(A , APAR, ERRA, ERRB)
n
5% V
0.55
0.55
I
= 24 mA
OL
CC
(A , APAR, ERRA, ERRB)
n
10% V
I
= 64 mA (B , BPAR)
OL n
CC
V
V
Input Threshold Voltage
1.45
1.0
V
V
±0.1V, Sweep Edge Rate must be > 1V/50 ns
Observed on “quiet” output during
TH
Negative Ground Bounce
Voltage
OLV
simultaneous switching of remaining outputs
Observed on “quiet” output during
V
Positive Ground Bounce
Voltage
OLP
1.0
V
simultaneous switching of remaining outputs
I
I
Input Low Current
Input HIGH
−0.6
mA
µA
Max
Max
V
V
V
= 0.5V
= 2.7V
= 7.0V
IL
IN
IN
IN
IH
5.0
Current
I
Input HIGH Current
Breakdown Test
BVI
7.0
0.5
50
µA
mA
µA
V
Max
Max
Max
0.0
(ODD/EVEN, GBA, GAB, SEL, LEA, LEB)
V = 5.5V
IN
I
I
Input HIGH Current
Breakdown (I/O)
Output HIGH
BVIT
CEX
(A , B , A
, B
)
PAR
n
n
PAR
V
= V
OUT
CC
Leakage Current
Input Leakage
Test
V
I
= 1.9 µA
ID
ID
4.75
All Other Pins Grounded
V = 150 mV
IOD
I
Output Leakage
Circuit Current
Input Low Current
Output Leakage Current
Current
OD
3.75
−0.6
70
µA
mA
µA
0.0
All Other Pins Grounded
I
I
I
Max
Max
V
V
= 0.5V
= 2.7V
IL
IN
IH+
OZH
I/O
(A , B , APAR, BPAR)
n
n
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4
DC Electrical Characteristics (Continued)
V
Symbol
Parameter
Output Leakage
Min
Typ
Max
Units
Conditions
CC
I
I
I
V
= 0.5V
IL+
I/O
−650
−150
µA
Max
Max
Current
(A , B , APAR, BPAR)
OZL
OS
n
n
Output Short-Circuit Current
−60
V
= 0V
OUT
mA
(A , APAR, ERRA, ERRB)
n
−100
−225
500
155
210
Max
0.0V
Max
Max
V
V
V
V
= 0V (B , BPAR)
OUT
OUT
n
I
I
I
Bus Drainage Test
µA
mA
mA
= 5.25V
ZZ
Power Supply Current
Power Supply Current
132
178
= HIGH
CCH
CCL
O
O
= LOW, GAB = LOW,
GBA = HIGH, V = LOW
IL
I
Power Supply Current
160
190
mA
Max
V
= HIGH Z
CCZ
O
AC Electrical Characteristics
T
= +25°C
T
= 0°C to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Figure
Number
Symbol
Parameter
Units
C
L
Min
4.0
4.0
7.5
7.5
7.5
7.5
Typ
7.5
Max
Min
4.0
4.0
7.5
7.5
7.5
7.5
Max
t
Propagation Delay
A , APAR to B , BPAR
13.0
13.0
17.0
17.0
17.0
17.0
14.0
14.0
18.0
18.0
18.0
18.0
PLH
ns
ns
ns
Figure 1
Figure 2
Figure 3
t
t
t
t
t
8.5
PHL
PLH
PHL
PLH
PHL
n
n
Propagation Delay
A , B to BPAR, APAR
12.0
12.5
12.0
12.5
n
n
Propagation Delay
A , B to ERRA, ERRB
n
n
t
t
Propagation Delay
4.5
4.5
7.5
8.0
11.0
11.0
4.5
4.5
12.0
12.0
PLH
PHL
ns
ns
ns
ns
Figure 4
Figure 5
Figure 6
Figure 7
ODD/EVEN to ERRA, ERRB
Propagation Delay
t
t
t
t
t
t
t
t
t
t
4.5
4.5
5.5
5.5
9.5
9.7
3.0
3.0
7.5
8.5
11.5
11.5
13.0
13.0
17.5
17.5
10.0
10.0
4.5
4.5
5.5
5.5
7.5
7.5
3.0
3.0
12.5
12.5
14.0
14.0
18.0
18.0
11.0
11.0
PLH
PHL
ODD/EVEN to APAR, BPAR
Propagation Delay
9.0
PLH
PHL
9.5
APAR, BPAR to ERRA, ERRB
LEA/LEB to
13.0
PLH
PHL
ERRA /ERRB
Propagation Delay
6.0
7.0
PLH
PHL
ns
ns
ns
Figure 10
Figure 11
Figure 11
SEL to APAR, BPAR
Propagation Delay
3.5
3.5
3.5
3.5
1.0
1.0
7.0
8.0
6.5
7.5
4.5
6.5
10.0
10.0
10.0
10.0
10.0
10.0
3.5
3.5
3.5
3.5
1.0
1.0
11.0
11.0
11.0
11.0
11.0
11.0
PLH
PHL
LEB to A , APAR
n
t
t
Propagation Delay
PLH
PHL
LEA to B , BPAR
n
t
t
Output Enable Time
PZH
PZL
Figure 8,
Figure 9
ns
GBA or GAB to A ,
n
APAR or B , BPAR
n
t
t
Output Disable Time
1.0
1.0
4.0
4.0
7.0
7.0
1.0
1.0
8.0
8.0
PHZ
PLZ
Figure 8,
Figure 9
ns
ns
GBA or GAB to A ,
n
APAR or B , BPAR
n
t (H)
Setup Time, HIGH or LOW
5.0
5.0
0
1.6
1.8
5.0
5.0
0
S
Figure 12,
Figure 13
t (L)
A , B to LEA, LEB
n n
S
t
t
t
(H)
(L)
Hold Time, HIGH or LOW
A , B to LEA, LEB
−1.7
−1.5
2.0
H
H
Figure 12,
Figure 13
ns
ns
0
0
n
n
Pulse Width for LEA, LEB
6.0
6.0
Figure 14
W
5
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AC Path
A , APAR → B , BPAR
n
n
(B , BPAR → A , APAR)
n
n
FIGURE 1.
A
→ BPAR
n
(B → APAR)
n
FIGURE 2.
A
→ ERRA
n
(B → ERRB)
n
FIGURE 3.
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6
AC Path (Continued)
O/E → ERRA
O/E → ERRB
FIGURE 4.
O/E → BPAR
(O/E → APAR)
FIGURE 5.
APAR → ERRA
(BPAR → ERRB)
FIGURE 6.
7
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AC Path (Continued)
FIGURE 7.
ZH, HZ
FIGURE 8.
ZL, LZ
FIGURE 9.
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8
AC Path (Continued)
SEL → BPAR
(SEL → APAR)
FIGURE 10.
LEA → BPAR, B[0:7]
(LEB → APAR, A[0:7])
FIGURE 11.
TS(H), TH(H)
LEA → APAR, A[0:7]
(LEB → BPAR, B[0:7])
FIGURE 12.
9
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AC Path (Continued)
TS(L), TH(L)
LEA → APAR, A[0:7]
(LEB → BPAR, B[0:7])
FIGURE 13.
FIGURE 14.
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10
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M28B
11
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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