74F00SJX [FAIRCHILD]

Quad 2-Input NAND Gate; 四路2输入与非门
74F00SJX
型号: 74F00SJX
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Quad 2-Input NAND Gate
四路2输入与非门

栅极 触发器 逻辑集成电路 光电二极管
文件: 总5页 (文件大小:64K)
中文:  中文翻译
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December 1994  
Revised September 2000  
74F00  
Quad 2-Input NAND Gate  
General Description  
This device contains four independent gates, each of which  
performs the logic NAND function.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F00SC  
74F00SJ  
74F00PC  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Unit Loading/Fan Out  
Input IIH/IIL  
U.L.  
Pin Names  
Description  
Output IOH/IOL  
HIGH/LOW  
1.0/1.0  
An, Bn  
On  
Inputs  
Outputs  
20 µA/0.6 mA  
1 mA/20 mA  
50/33.3  
© 2000 Fairchild Semiconductor Corporation  
DS009454  
www.fairchildsemi.com  
Absolute Maximum Ratings(Note 1)  
Recommended Operating  
Conditions  
Storage Temperature  
65°C to +150°C  
Ambient Temperature under Bias  
Junction Temperature under Bias  
VCC Pin Potential to Ground Pin  
Input Voltage (Note 2)  
55°C to +125°C  
55°C to +150°C  
0.5V to +7.0V  
Free Air Ambient Temperature  
Supply Voltage  
0°C to +70°C  
+4.5V to +5.5V  
0.5V to +7.0V  
Input Current (Note 2)  
30 mA to +5.0 mA  
Voltage Applied to Output  
in HIGH State (with VCC = 0V)  
Standard Output  
0.5V to VCC  
3-STATE Output  
0.5V to +5.5V  
Note 1: Absolute maximum ratings are values beyond which the device  
may be damaged or have its useful life impaired. Functional operation  
under these conditions is not implied.  
Current Applied to Output  
in LOW State (Max)  
twice the rated IOL (mA)  
4000V  
Note 2: Either voltage limit or current limit is sufficient to protect inputs.  
ESD Last Passing Voltage (Min)  
DC Electrical Characteristics  
VCC  
Symbol  
VIH  
Parameter  
Input HIGH Voltage  
Min  
Typ  
Max  
Units  
Conditions  
2.0  
V
V
V
V
Recognized as a HIGH Signal  
Recognized as a LOW Signal  
VIL  
Input LOW Voltage  
Input Clamp Diode Voltage  
Output HIGH  
0.8  
VCD  
VOH  
1.2  
Min  
Min  
I
I
I
I
IN = −18 mA  
OH = −1 mA  
OH = −1 mA  
OL = 20 mA  
10% VCC  
5% VCC  
2.5  
2.7  
Voltage  
VOL  
Output LOW  
10% VCC  
0.5  
5.0  
7.0  
50  
V
Min  
Max  
Max  
Max  
Voltage  
IIH  
Input HIGH  
µA  
µA  
µA  
V
V
V
IN = 2.7V  
IN = 7.0V  
OUT = VCC  
Current  
IBVI  
ICEX  
VID  
IOD  
Input HIGH Current  
Breakdown Test  
Output HIGH  
Leakage Current  
Input Leakage  
Test  
I
ID = 1.9 µA  
All other pins grounded  
IOD = 150 mV  
All other pins grounded  
4.75  
V
0.0  
0.0  
Output Leakage  
Circuit Current  
Input LOW Current  
Output Short-Circuit Current  
Power Supply Current  
Power Supply Current  
V
3.75  
µA  
IIL  
0.6  
150  
2.8  
mA  
mA  
mA  
mA  
Max  
Max  
Max  
Max  
V
V
V
V
IN = 0.5V  
OUT = 0V  
O = HIGH  
O = LOW  
IOS  
ICCH  
ICCL  
60  
1.9  
6.8  
10.2  
AC Electrical Characteristics  
TA = +25°C  
TA = −55°C to +125°C  
TA = 0°C to +70°C  
V
CC = +5.0V  
V
CC = +5.0V  
L = 50 pF  
Max  
V
CC = +5.0V  
L = 50 pF  
Max  
Symbol  
Parameter  
Units  
C
L = 50 pF  
C
C
Min  
2.4  
1.5  
Typ  
3.7  
3.2  
Max  
5.0  
Min  
2.0  
1.5  
Min  
2.4  
1.5  
tPLH  
tPHL  
Propagation Delay  
An, Bn to On  
7.0  
6.5  
6.0  
5.3  
ns  
4.3  
www.fairchildsemi.com  
2
Physical Dimensions inches (millimeters) unless otherwise noted  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
Package Number M14A  
3
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package Number M14D  
www.fairchildsemi.com  
4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Package Number N14A  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
5
www.fairchildsemi.com  

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