74ALVC245WM [FAIRCHILD]
Low Voltage Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs; 低电压双向收发器具有3.6V容限输入和输出
| 型号： | 74ALVC245WM |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs |
| 文件： | 总7页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2001
Revised March 2005
74ALVC245
Low Voltage Bidirectional Transceiver
with 3.6V Tolerant Inputs and Outputs
General Description
Features
■ 1.65V to 3.6V VCC supply operation
The ALVC245 contains eight non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus ori-
ented applications. The T/R input determines the direction
of data flow. The OE input disables both the A and B ports
by placing them in a high impedance state.
■ 3.6V tolerant inputs and outputs
■ Power-off high impedance inputs and outputs
■ Supports Live Insertion and Withdrawal (Note 1)
■ tPD
The 74ALVC245 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
3.4 ns max for 3.0V to 3.6V VCC
3.9 ns max for 2.3V to 2.7V VCC
6 ns max for 1.65V to 1.95V VCC
The 74ALVC245 is fabricated with an advanced CMOS
technology to achieve high-speed operation while main-
taining low CMOS power dissipation.
■ Uses patented Quiet Series noise/EMI reduction
circuitry
■ Latchup conforms to JEDEC JED78
■ ESD performance:
Human body model 2000V
Machine model 200V
Note 1: To ensure the high impedance state during power up and power
down, OE should be tied to V
through a pull up resistor. The minimum
CC
n
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Package
Order Number
Package Description
Number
74ALVC245WM
74ALVC245MTC
M20B
MTC20
MTC20
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ALVC245MTCX_NL
(Note 2)
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 2: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
Pin Descriptions
Pin Names
Description
OE
Output Enable Input (Active LOW)
Transmit/Receive Input
T/R
A0–A7
B0–B7
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500647
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Connection Diagram
Truth Table
Inputs
Outputs
OE T/R
L
L
L
H
X
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
H
HIGH Z State on A0–A7, B0–B7 (Note 3)
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
Note 3: Unused bus terminals during HIGH Z State must be held HIGH or
LOW.
Logic Diagram
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2
Absolute Maximum Ratings(Note 4)
Recommended Operating
Conditions (Note 6)
Supply Voltage (VCC
)
0.5V to 4.6V
0.5V to 4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO) (Note 5)
0.5V to VCC 0.5V
Operating
1.65V to 3.6V
0V to VCC
DC Input Diode Current (IIK
VI 0V
)
Input Voltage (VI)
50 mA
50 mA
50 mA
Output Voltage (VO)
0V to VCC
DC Output Diode Current (IOK
VO 0V
)
Free Air Operating Temperature (TA)
Minimum Input Edge Rate ( t/ V)
VIN 0.8V to 2.0V, VCC 3.0V
40 C to 85 C
DC Output Source/Sink Current
(IOH/IOL
10 ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
)
DC VCC or GND Current per
Supply Pin (ICC or GND)
100 mA
Storage Temperature Range (TSTG
)
65 C to 150 C
Note 5: I Absolute Maximum Rating must be observed, limited to 4.6V.
O
Note 6: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
V
CC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
V
V
V
HIGH Level Input Voltage
1.65 - 1.95 0.65 x V
IH
CC
2.3 - 2.7
2.7 - 3.6
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
1.65 - 3.6
1.65
1.7
2.0
V
LOW Level Input Voltage
HIGH Level Output Voltage
0.35 x V
0.7
IL
CC
V
V
0.8
I
I
I
I
100
A
V
- 0.2
OH
OH
OH
OH
OH
CC
4 mA
6 mA
1.2
2.0
1.7
2.2
2.4
2
2.3
12 mA
2.3
2.7
3.0
I
I
I
I
I
24 mA
3.0
OH
OL
OL
OL
OL
V
LOW Level Output Voltage
100
A
1.65 - 3.6
1.65
0.2
0.45
0.4
0.7
0.4
0.55
5.0
10
OL
4 mA
6 mA
2.3
V
12 mA
2.3
2.7
I
24 mA
3.0
OL
I
I
I
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
0
0
V
V
3.6V
3.6V
3.6
A
A
A
A
I
I
3.6
OZ
CC
O
V
V
or GND, I
O
0
3.6
10
I
CC
I
Increase in I per Input
V
V
CC
0.6V
3 - 3.6
750
CC
CC
IH
3
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AC Electrical Characteristics
T
40 C to 85 C, R
500
A
L
C
50 pF
C
30 pF
L
L
Symbol
Parameter
Units
V
3.3V 0.3V
V
2.7V
Max
V
2.5V 0.2V
V
CC
1.8V 0.15V
CC
CC
CC
Min
1.3
1.6
1.7
Max
3.4
5.5
5.5
Min
Min
1.0
2.0
0.8
Max
3.5
6.0
4.8
Min
Max
6.0
8.6
8.0
t
t
t
, t
Propagation Delay
3.9
6.3
5.3
1.5
2.7
1.5
ns
ns
ns
PHL PLH
, t
Output Enable Time
Output Disable Time
PZL PZH
, t
PLZ PHZ
Capacitance
T
25 C
A
Symbol
Parameter
Conditions
Units
V
Typical
CC
C
Input Capacitance
Input/ Output Capacitance
Power Dissipation Capacitance
Control
V
V
f
0V or V
3.3
3.3
3.3
2.5
1.8
3.3
2.5
1.8
3
6
IN
I
CC
pF
C
A or B Ports
0V or V
I/O
PD
I
CC
C
Outputs Enabled
10 MHz, C
0 pF
0 pF
30
27
25
0
L
L
pF
Outputs Disabled
f
10 MHz, C
0
0
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4
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
SWITCH
Open
VL
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f 1MHz; tr tf 2ns; Z0 50
)
VCC
Symbol
3.3V 0.3V
1.5V
2.7V
1.5V
2.5V 0.2V
VCC/2
1.8V 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
1.5V
VCC/2
VCC/2
VOL 0.3V
VOH 0.3V
6V
VOL 0.3V
VOH 0.3V
6V
VOL 0.15V
VOH 0.15V
VCC*2
VOL 0.15V
VOH 0.15V
VCC*2
VY
VL
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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