74AC273 [FAIRCHILD]
Octal D-Type Flip-Flop; 八D型触发器
| 型号： | 74AC273 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal D-Type Flip-Flop |
| 文件： | 总10页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised August 2000
74AC273 • 74ACT273
Octal D-Type Flip-Flop
General Description
Features
■ Ideal buffer for microprocessor or memory
■ Eight edge-triggered D-type flip-flops
■ Buffered common clock
The AC273 and ACT273 have eight edge-triggered D-type
flip-flops with individual D-type inputs and Q outputs. The
common buffered Clock (CP) and Master Reset (MR) input
load and reset (clear) all flip-flops simultaneously.
■ Buffered, asynchronous master reset
■ See 377 for clock enable version
■ See 373 for transparent latch version
■ See 374 for 3-STATE version
The register is fully edge-triggered. The state of each D-
type input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s Q
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
■ Outputs source/sink 24 mA
■ 74ACT273 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC273SC
74AC273SJ
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC273MTC
74AC273PC
74ACT273SC
74ACT273SJ
74ACT273MTC
74ACT273PC
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M20B
M20D
MTC20
N20A
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS009954
www.fairchildsemi.com
Pin Descriptions
Mode Select-Function Table
Pin Names
Description
Data Inputs
Master Reset
Inputs
Outputs
Operating Mode
D0–D7
MR
MR CP Dn
Qn
Reset (Clear)
Load ‘1'
L
H
H
X
X
H
L
L
H
L
CP
Clock Pulse Input
Data Outputs
Q0–Q7
Load ‘0'
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
± 50 mA
VCC @ 3.3V, 4.5V, 5.5V for AC
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
± 50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
(PDIP)
)
−65°C to +150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V for ACT
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
VOUT = 0.1V
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.1
2.1
3.15
3.85
0.9
2.25
2.75
1.5
3.15
3.85
0.9
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
VOUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
VIN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
OH = −12 mA
V
V
OH = −24 mA
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
I
OUT = 50 µA
0.1
0.1
VIN = VIL or VIH
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
I
I
I
OL = 12 mA
V
OL = 24 mA
OL = 24 mA (Note 2)
IIN
Maximum Input
5.5
±0.1
±1.0
µA
VI = VCC, GND
(Note 4)
IOLD
Leakage Current
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
OLD = 1.65V Max
VOHD = 3.85V Min
IN = VCC
IOHD
−75
ICC
V
5.5
4.0
40.0
µA
(Note 4)
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
3
www.fairchildsemi.com
AC Electrical Characteristics for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 5)
3.3
Units
Min
90
Typ
125
175
7.0
5.5
7.0
5.0
7.0
5.0
Max
Min
fMAX
Maximum Clock
75
125
3.0
2.5
3.5
2.5
3.5
2.5
MHz
ns
Frequency
5.0
140
4.0
3.0
4.0
3.0
4.0
3.0
tPLH
tPHL
tPHL
Propagation Delay
Clock to Output
Propagation Delay
Clock to Output
Propagation Delay
MR to Output
3.3
12.5
9.0
14.0
10.0
14.5
11.0
14.0
10.5
5.0
3.3
13.0
10.0
13.0
10.0
ns
5.0
3.3
ns
5.0
Note 5: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for AC
VCC
(V)
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Guaranteed Minimum
C
L = 50 pF
C
Symbol
Parameter
Units
(Note 6)
3.3
Typ
3.5
tS
Setup Time, HIGH or LOW
Data to CP
5.5
4.0
6.0
4.5
0
ns
ns
ns
5.0
2.5
tH
Hold Time, HIGH or LOW
Data to CP
3.3
−2.0
−1.0
3.5
0
5.0
1.0
5.5
4.0
1.0
6.0
4.5
tW
Clock Pulse Width
HIGH or LOW
3.3
5.0
2.5
tW
MR Pulse Width
HIGH or LOW
Recovery Time
MR to CP
3.3
5.0
3.3
5.0
2.0
1.5
1.5
1.0
5.5
4.0
3.5
2.0
6.0
4.5
4.5
3.0
ns
ns
trec
Note 6: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
www.fairchildsemi.com
4
DC Electrical Characteristics for ACT
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
VOUT = 0.1V
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
1.5
2.0
0.8
0.8
4.4
5.4
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
1.5
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 7)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
OL = 24 mA
OL = 24 mA (Note 7)
IIN
Maximum Input
Leakage Current
Maximum
5.5
5.5
±0.1
±1.0
µA
VI = VCC, GND
VI = VCC − 2.1V
ICCT
0.6
1.5
mA
ICC/Input
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 8)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
OLD = 1.65V Max
VOHD = 3.85V Min
IN = VCC
or GND
−75
V
5.5
4.0
40.0
µA
Note 7: All outputs loaded; thresholds on input associated with output under test.
Note 8: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for ACT
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 9)
2.0
Units
Min
Typ
Max
Min
fMAX
Maximum Clock Frequency
Propagation Delay
CP to Qn
125
189
110
MHz
ns
tPLH
tPHL
tPHL
5.0
5.0
1.5
6.5
7.0
8.5
9.0
1.5
9.0
8.5
Propagation Delay
MR to Qn
1.5
1.5
ns
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
5
www.fairchildsemi.com
AC Operating Requirements for ACT
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Guaranteed Minimum
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 10)
Typ
tS
Setup Time, HIGH or LOW
Dn to CP
5.0
5.0
5.0
1.0
−0.5
2.0
3.5
3.5
1.5
4.0
ns
ns
ns
tH
Hold Time, HIGH or LOW
Dn to CP
1.5
tW
Clock Pulse Width
HIGH or LOW
4.0
tW
MR Pulse Width
HIGH or LOW
Recovery Time
MR to CP
5.0
5.0
1.5
0.5
4.0
3.0
4.0
3.0
ns
ns
tW
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
VCC = OPEN
CIN
Input Capacitance
4.5
pF
CPD
Power Dissipation Capacitance for AC
Power Dissipation Capacitance for ACT
50.0
40.0
pF
VCC = 5.0V
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
www.fairchildsemi.com
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
9
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.fairchildsemi.com
10
相关型号：
74AC273DC
AC SERIES, OCTAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20
TI
74AC273LC
AC SERIES, OCTAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20
TI
74AC273LCT
D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74AC273LCTR
D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74AC273LCX
D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74AC273LCXR
D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明