74AC191FCXR [FAIRCHILD]
暂无描述;
| 型号： | 74AC191FCXR |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 暂无描述 计数器 时钟 |
| 文件： | 总10页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised November 1999
74AC191
Up/Down Counter with Preset and Ripple Clock
General Description
Features
The AC191 is a reversible modulo 16 binary counter. It fea-
tures synchronous counting and asynchronous presetting.
The preset feature allows the AC191 to be used in pro-
grammable dividers. The Count Enable input, the Terminal
Count output and the Ripple Clock output make possible a
variety of methods of implementing multistage counters. In
the counting modes, state changes are initiated by the ris-
ing edge of the clock.
■ ICC reduced by 50%
■ High speed—133 MHz typical count frequency
■ Synchronous counting
■ Asynchronous parallel load
■ Cascadable
■ Outputs source/sink 24 mA
Ordering Code:
Order Number Package Number
Package Description
74AC191SC
74AC191SJ
74AC191MTC
74AC191PC
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
Count Enable Input
Clock Pulse Input
CE
CP
P0–P3
Parallel Data Inputs
Asynchronous Parallel Load Input
Up/Down Count Control Input
Flip-Flop Outputs
PL
U /D
Q0–Q3
RC
Ripple Clock Output
TC
Terminal Count Output
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009940
www.fairchildsemi.com
RC Truth Table
Inputs
Outputs
RC
PL
CE
TC
CP
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
= Clock Pulse
(Note 1)
H
H
H
L
L
H
X
X
H
X
L
X
X
X
H
H
H
Note 1: TC is generated internally
X
Functional Description
The AC191 is a synchronous up/down counter. The AC191
is organized as a 4-bit binary counter. It contains four edge-
triggered flip-flops with internal gating and steering logic to
provide individual preset, count-up and count-down opera-
tions.
ripple through to the last stage before the clock goes HIGH.
There is no such restriction on the HIGH state duration of
the clock, since the RC output of any device goes HIGH
shortly after its CP input goes HIGH.
The configuration shown in Figure 3 avoids ripple delays
and their associated restrictions. The CE input for a given
stage is formed by combining the TC signals from all the
preceding stages. Note that in order to inhibit counting an
enable signal must be included in each carry gate. The
simple inhibit scheme of Figure 1 and Figure 2 doesn't
apply, because the TC output of a given stage is not
affected by its own CE.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired number.
When the Parallel Load (PL) input is LOW, information
present on the Parallel Load inputs (P0–P3) is loaded into
the counter and appears on the Q outputs. This operation
overrides the counting functions, as indicated in the Mode
Select Table.
A HIGH signal on the CE input inhibits counting. When CE
is LOW, internal state changes are initiated synchronously
by the LOW-to-HIGH transition of the clock input. The
direction of counting is determined by the U/D input signal,
as indicated in the Mode Select Table. CE and U/D can be
changed with the clock in either state, provided only that
the recommended setup and hold times are observed.
Mode Select Table
Inputs
U/D
Mode
PL
H
CE
L
CP
L
H
X
X
Count Up
Two types of outputs are provided as overflow/underflow
indicators. The terminal count (TC) output is normally
LOW. It goes HIGH when the circuits reach zero in the
count down mode or 15 in the count up mode. The TC out-
put will then remain HIGH until a state change occurs,
whether by counting or presetting or until U/D is changed.
The TC output should not be used as a clock signal
because it is subject to decoding spikes.
H
L
Count Down
L
X
X
X
Preset (Asyn.)
No Change (Hold)
H
H
State Diagram
The TC signal is also used internally to enable the Ripple
Clock (RC) output. The RC output is normally HIGH. When
CE is LOW and TC is HIGH, RC output will go LOW when
the clock next goes LOW and will stay LOW until the clock
goes HIGH again. This feature simplifies the design of mul-
tistage counters, as indicated in Figure 1 and Figure 2. In
Figure 1, each RC output is used as the clock input for the
next higher stage. This configuration is particularly advan-
tageous when the clock source has a limited drive capabil-
ity, since it drives only the first stage. To prevent counting in
all stages it is only necessary to inhibit the first stage, since
a HIGH signal on CE inhibits the RC output pulse, as indi-
cated in the RC Truth Table. A disadvantage of this config-
uration, in some applications, is the timing skew between
state changes in the first and last stages. This represents
the cumulative delay of the clock as it ripples through the
preceding stages.
A method of causing state changes to occur simulta-
neously in all stages is shown in Figure 2. All clock inputs
are driven in parallel and the RC outputs propagate the
carry/borrow signals in ripple fashion. In this configuration
the LOW state duration of the clock must be long enough to
allow the negative-going edge of the carry/borrow signal to
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2
Functional Description (continued)
FIGURE 1. N-Stage Counter Using Ripple Clock
FIGURE 2. Synchronous N-Stage Counter Using Ripple Carry/Borrow
FIGURE 3. Synchronous N-Stage Counter with Parallel Gated Carry/Borrow
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
2.0V to 6.0V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC + 0.5V
Output Voltage (VO)
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Operating Temperature (TA)
−40°C to +85°C
DC Output Diode Current (IOK
)
Minimum Input Edge Rate (∆V/∆t)
V
V
O = −0.5V
−20 mA
+20 mA
V
IN from 30% to 70% of VCC
O = VCC + 0.5V
VCC @ 3.3V 4.5V, 5.5V
125 mV/ns
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
or Sink Current (IO)
±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Note 2: Absolute maximum ratings are those values beyond which dam-
age to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its
power supply, temperature, output/input loading variables. Fairchild does
not recommend operation of FACT circuits outside databook specifica-
tions.
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
140°C
DC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
Guaranteed Limits
Minimum HIGH Level
Input Voltage
1.5
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
V
OUT = 0.1V
2.25
2.75
1.5
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
2.56
3.86
4.86
2.46
3.76
4.76
VIN = VIL or VIH
I
I
I
OH −12 mA
OH = −24 mA
OH.= −24 mA (Note 3)
VOL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
V
V
I
OUT = 50 µA
0.1
0.1
0.36
0.36
0.36
0.44
0.44
0.44
VIN = VIL or VIH
I
I
I
OL = 12 mA
OL = 24 mA
OL = 24 mA (Note 3)
IIN
Maximum Input
5.5
±0.1
±1.0
µA
VI = VCC, GND
(Note 5)
IOLD
Leakage Current
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
VOLD = 1.65V Max
VOHD = 3.85V Min
VIN = VCC
IOHD
−75
ICC
5.5
4.0
40.0
µA
(Note 5)
or GND
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
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4
AC Electrical Characteristics
VCC
C
L = 50 pF
T
A = −40°C to +85°C
L = 50 pF
Max
Symbol
Parameter
T
A = +25°C
C
Units
(V)
(Note 6)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Min
70
Typ
105
133
8.5
6.0
8.5
6.0
10.5
7.5
10.5
7.5
7.5
5.5
7.0
5.0
7.0
5.0
6.5
5.0
6.5
5.0
7.0
5.0
7.0
5.0
6.5
5.0
8.0
5.5
7.5
5.5
9.5
5.5
8.0
6.0
Max
Min
fMAX
Maximum Count
65
85
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Frequency
90
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Propagation Delay
CP to Qn
2.0
1.5
2.5
1.5
3.5
2.5
4.0
2.5
2.5
2.0
2.5
1.5
2.5
1.5
2.0
1.5
2.5
1.5
2.5
1.5
2.0
1.5
2.0
1.5
2.5
2.0
2.5
1.5
3.5
2.0
3.0
2.0
15.0
11.0
14.5
10.5
18.0
12.0
17.5
12.5
12.0
9.5
1.5
1.5
2.0
1.5
2.5
1.5
3.0
2.0
2.0
1.0
2.0
1.0
1.5
1.0
1.5
1.0
2.0
1.0
2.0
1.0
1.5
1.0
1.5
1.0
2.0
1.0
1.5
1.0
2.5
1.0
2.0
1.5
16.0
12.0
16.0
11.5
20.0
14.0
19.0
13.5
13.5
10.5
12.5
9.5
Propagation Delay
CP to Qn
Propagation Delay
CP to TC
Propagation Delay
CP to TC
Propagation Delay
CP to RC
Propagation Delay
CP to RC
11.5
8.5
Propagation Delay
CE to RC
12.0
8.5
13.5
9.5
Propagation Delay
CE to RC
11.0
8.0
12.5
9.0
Propagation Delay
U /D to RC
12.5
9.0
14.5
10.0
13.5
10.0
13.5
9.5
Propagation Delay
U /D to RC
12.0
8.5
Propagation Delay
U /D to TC
11.5
8.5
Propagation Delay
U /D to TC
11.0
8.5
12.5
9.5
Propagation Delay
13.5
9.5
15.5
10.5
14.5
10.5
17.5
10.5
15.5
11.0
Pn to Qn
Propagation Delay
Pn to Qn
13.0
9.5
Propagation Delay
PL to Qn
14.5
9.5
Propagation Delay
PL to Qn
13.5
10.0
Note 6: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
5
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AC Operating Requirements
VCC
T
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
L = 50 pF
C
C
Symbol
Parameter
(V)
(Note 7)
3.3
Units
Typ
Guaranteed Minimum
tS
tH
tS
tH
tS
tH
Setup Time, HIGH or LOW
1.0
0.5
3.0
2.0
0.5
1.0
6.0
4.0
−0.5
0
3.0
2.5
1.0
1.0
7.0
4.5
−0.5
0
ns
ns
ns
ns
ns
ns
Pn to PL
5.0
Hold Time, HIGH or LOW
Pn to PL
3.3
−1.5
−0.5
3.0
5.0
Setup Time, LOW
CE to CP
3.3
5.0
1.5
Hold Time, LOW
CE to CP
3.3
−4.0
−2.5
4.0
5.0
Setup Time, HIGH or LOW
U/D to CP
3.3
8.0
5.5
0
9.0
6.5
0
5.0
2.5
Hold Time, HIGH or LOW
U/D to CP
3.3
−5.0
−3.0
5.0
0.5
0.5
tW
PL Pulse Width, LOW
3.3
5.0
3.3
5.0
3.3
5.0
2.0
1.0
3.5
1.0
3.5
3.0
0
4.0
1.0
4.0
4.0
0
ns
ns
ns
tW
CP Pulse Width, LOW
2.0
2.0
trec
Recovery Time
PL to CP
−0.5
−1.0
0
0
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
pF
V
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
75.0
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6
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M16A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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