74AC14MTCX_NL [FAIRCHILD]
Hex Inverter with Schmitt Trigger Input; 六反相器带施密特触发器输入
| 型号： | 74AC14MTCX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Hex Inverter with Schmitt Trigger Input |
| 文件： | 总9页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised September 2005
74AC14 • 74ACT14
Hex Inverter with Schmitt Trigger Input
General Description
Features
The 74AC14 and 74ACT14 contain six inverter gates each with
a Schmitt trigger input. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free output sig-
nals. In addition, they have a greater noise margin than conven-
tional inverters.
I
reduced by 50%
CC
Outputs source/sink 24 mA
74ACT14 has TTL-compatible inputs
The 74AC14 and 74ACT14 have hysteresis between the posi-
tive-going and negative-going input thresholds (typically 1.0V)
which is determined internally by transistor ratios and is essen-
tially insensitive to temperature and supply voltage variations.
Ordering Code:
Package
Order Number
Package Description
Number
74AC14SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC14SCX_NL
(Note 1)
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC14SJ
M14D
MTC14
MTC14
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC14MTC
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC14MTCX_NL
(Note 1)
74AC14PC
N14A
M14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT14SC
74ACT14MTC
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MTC14
MTC14
74ACT14MTCX_NL
(Note 1)
74ACT14PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009917
www.fairchildsemi.com
Logic Symbol
Connection Diagram
IEEE/IEC
Function Table
Pin Descriptions
Input
Output
Pin Names
Description
I
Inputs
Outputs
A
L
O
H
L
n
O
n
H
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Supply Voltage (V
)
0.5V to 7.0V
CC
DC Input Diode Current (I )
IK
Supply Voltage (V
)
CC
V
V
0.5V
20 mA
20 mA
I
I
AC
2.0V to 6.0V
4.5V to 5.5V
V
0.5V
CC
ACT
DC Input Voltage (V )
0.5V to V
0.5V to V
0.5V
I
CC
CC
Input Voltage (V )
0V to V
0V to V
I
CC
CC
DC Output Diode Current (I
)
OK
Output Voltage (V )
O
V
V
0.5V
20 mA
20 mA
0.5V
O
O
Operating Temperature (T )
40 C to 85 C
A
V
0.5V
CC
DC Output Voltage (V )
O
DC Output Source
or Sink Current (I )
50 mA
50 mA
O
Note 2: Absolute maximum ratings are those values beyond which damage to the
device may occur. The databook specifications should be met, without exception, to
ensure that the system design is reliable over its power supply, temperature, and out-
put/input loading variables. Fairchild does not recommend operation of FACT cir-
cuits outside databook specifications.
DC V or Ground Current
CC
per Output Pin (I or I
)
GND
CC
Storage Temperature (T
)
65 C to 150 C
STG
Junction Temperature (T )
J
PDIP
140 C
DC Electrical Characteristics for AC
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Minimum HIGH Level
Units
Conditions
50 A45
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
5.5
5.5
Typ
Guaranteed Limits
V
2.99
4.49
5.49
2.9
2.9
4.4
5.4
I
OH
OUT
Output Voltage
4.4
5.4
V
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
1.0
2.2
3.2
3.9
0.5
0.9
1.1
1.2
1.4
1.6
0.3
0.4
0.5
75
I
I
I
I
12
24 mA
24 mA (Note )
50
OH
V
V
OH
OH
V
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
A
OL
OUT
0.1
0.1
0.36
0.36
0.36
0.1
I
I
I
12
24 mA
OL
V
A
V
OL
OL
24 mA (Note )
V , GND
CC
I
(Note )
Maximum Input Leakage Current
Maximum Positive
V
IN
I
V
V
V
V
2.2
T
T
T
T
Worst Case
Worst Case
Worst Case
Worst Case
1.65V Max
t
A
Threshold
3.2
3.9
Minimum Negative
Threshold
0.5
t
A
A
A
0.9
V
V
V
1.1
Maximum Hysteresis
Minimum Hysteresis
1.2
H(MAX)
H(MIN)
1.4
1.6
0.3
0.4
0.5
I
I
I
Minimum Dynamic
Output Current (Note )
Maximum Quiescent
Supply Current
mA
mA
A
V
V
V
OLD
OHD
CC
OLD
OHD
IN
75
3.85V Min
2.0
20.0
V
CC
(Note )
or GND
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
3
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AC Electrical Characteristics for AC
V
T
25 C
T
40 C to 85 C
50 pF
Min Max
CC
A
A
Symbol
Parameter
C
50 pF
C
Units
(V)
(Note )
3.3
L
L
Min
1.5
1.5
1.5
1.5
Typ
Max
13.5
10.0
11.5
8.5
t
t
Propagation Delay
Propagation Delay
9.5
7.0
7.5
6.0
1.5
1.5
1.5
1.5
15.0
11.0
13.0
9.5
PLH
PHL
ns
ns
5.0
3.3
5.0
Note 6: Voltage Range 3.3 is 3.3V 0.3V
Voltage Range 5.0 is 5.0V 0.5V
DC Electrical Characteristics for ACT
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Minimum HIGH Level
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
V
V
V
2.0
2.0
0.8
0.8
2.0
2.0
0.8
0.8
V
0.1V
0.1V
0.1V
0.1V
50
IH
OUT
V
V
V
Input Voltage
1.5
or V
CC
Maximum LOW Level
Input Voltage
1.5
V
IL
OUT
1.5
or V
CC
Minimum HIGH Level
Output Voltage
4.49
5.49
434
5.4
4.4
5.4
I
A
OH
OUT
V
V or V
IL IH
IN
OH
OH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
I
24 mA
24 mA (Note 7)
V
Maximum LOW Level
Output Voltage
0.001
0.001
50
A
OL
OUT
0.1
0.1
V
V
or V
IH
IN
OL
OL
IL
4.5
5.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
5.5
5.5
5.5
0.36
0.36
0.1
1.4
1.6
0.4
0.5
2.0
2.0
0.8
0.8
0.44
0.44
1.0
1.4
1.6
0.4
0.5
2.0
2.0
0.8
0.8
1.5
75
I
I
24 mA
24 mA (Note 7)
V , GND
CC
I
Maximum Input Leakage Current
Maximum Hysteresis
A
V
IN
I
V
V
V
V
T
T
T
T
Worst Case
Worst Case
Worst Case
Worst Case
H(MAX)
A
V
V
V
V
Minimum Hysteresis
H(MIN)
A
A
A
Maximum Positive
Threshold
t
t
Minimum Negative
Threshold
I
I
I
I
Maximum I /Input
CC
0.6
mA
mA
mA
A
V
V
V
V
V
CC
2.1V
CCT
OLD
OHD
CC
I
Minimum Dynamic
Output Current (Note 8)
Maximum Quiescent
Supply Current
1.65V Max
3.85V Min
OLD
OHD
IN
75
2.0
20.0
V
CC
or GND
Note 7: All outputs loaded; thresholds on input associated with output under test.
Note 8: Maximum test duration 2.0 ms, one output loaded at a time.
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4
AC Electrical Characteristics for ACT
V
T
25 C
T
40 C to 85 C
50 pF
Min Max
CC
A
A
Symbol
Parameter
C
50 pF
C
Units
(V)
(Note 9)
5.0
L
L
Min
Typ
Max
t
t
Propagation Delay
Data to Output
3.0
8.0
10.0
3.0
11.0
ns
ns
PLH
PHL
Propagation Delay
Data to Output
5.0
3.0
8.0
10.0
3.0
11.0
Note 9: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
C
Input Capacitance
4.5
25.0
80
pF
V
V
OPEN
5.0V
IN
CC
Power Dissipation Capacitance for AC
for ACT
PD
pF
CC
5
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
www.fairchildsemi.com
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION
As used herein:
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
2. A critical component is any component of a life support
device or system whose failure to perform can be reason-
ably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of terms
Datasheet Identification Product Status
Definition
Advance Information
Formative or In Design This datasheet contains the design specifications for product develop-
ment. Specifications may change in any manner without notice.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains preliminary data, and supplementary data will
be published at a later date. Fairchild Semiconductor reserves the right
to make changes at any time without notice in order to improve design.
No Identification Needed
Obsolete
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice in order
to improve design.
This datasheet contains specifications on a product that has been dis-
continued by Fairchild Semiconductor. The datasheet is printed for ref-
erence information only.
9
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相关型号：
74AC14PC_NL
Inverter, AC Series, 6-Func, 1-Input, CMOS, PDIP14, 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-14
FAIRCHILD
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