74ABT899CSC [FAIRCHILD]
9-Bit Latchable Transceiver with Parity Generator/Checker; 9位闭锁收发器奇偶校验发生器/校验器
| 型号： | 74ABT899CSC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 9-Bit Latchable Transceiver with Parity Generator/Checker |
| 文件： | 总16页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1992
Revised January 1999
74ABT899
9-Bit Latchable Transceiver
with Parity Generator/Checker
■ Ability to simultaneously generate and check parity
General Description
■ May be used in systems applications in place of the
543 and 280
The ABT899 is a 9-bit to 9-bit parity transceiver with trans-
parent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit
data busses in either direction.
■ May be used in system applications in place of the
657 and 373 (no need to change T/R to check parity)
■ Guaranteed output skew
The ABT899 features independent latch enables for the A-
to-B direction and the B-to-A direction, a select pin for
ODD/EVEN parity, and separate error signal output pins for
checking parity.
■ Guaranteed multiple output switching specifications
■ Output switching specified for both 50 pF and
250 pF loads
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
Features
■ Latchable transceiver with output sink of 64 mA
■ Guaranteed latchup protection
■ Option to select generate parity and check or
■ High impedance glitch free bus loading during entire
“feed-through” data/parity in directions A-to-B or B-to-A
power up and power down cycle
■ Independent latch enables for A-to-B and B-to-A
■ Nondestructive hot insertion capability
directions
■ Disable time less than enable time to avoid bus
■ Select pin for ODD/EVEN parity
contention
■ ERRA and ERRB output pins for parity checking
Ordering Code:
Order Number Package Number
Package Description
74ABT899CSC
74ABT899CMSA
74ABT899CQC
M28B
MSA28
V28A
28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body
28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pin Assignment for
SOIC and SSOP
Connection Diagrams
Pin Assignment
for PLCC
© 1999 Fairchild Semiconductor Corporation
DS011509.prf
www.fairchildsemi.com
Pin Descriptions
Functional Description
The ABT899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
Pin Names
Descriptions
A0–A7
B0–B7
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
•
•
•
Bus A (B) communicates to Bus B (A), parity is gener-
ated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B[0:7] (A[0:7]) can be checked
and monitored by ERRB (ERRA).
APAR, BPAR A and B Bus Parity Inputs/Outputs
ODD/EVEN
GBA, GAB
SEL
ODD/EVEN Parity Select,
Active LOW for EVEN Parity
Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
Output Enables for A or B Bus,
Active LOW
Select Pin for Feed-Through or
Generate Mode, LOW for Generate
Mode
Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function
Table below).
LEA, LEB
Latch Enables for A and B Latches,
HIGH for Transparent Mode
ERRA, ERRB Error Signals for Checking Generated
Parity with Parity In, LOW if Error
Occurs
Function Table
Inputs
Operation
GAB GBA SEL LEA LEB
H
H
H
L
X
L
X
L
X
H
Busses A and B are 3-STATE.
Generates parity from B[0:7] based on O/E (Note 1). Generated parity → APAR.
Generated parity checked against BPAR and output as ERRB.
H
L
L
H
H
Generates parity from B[0:7] based on O/E. Generated parity → APAR. Gener-
ated parity checked against BPAR and output as ERRB. Generated parity also
fed back through the A latch for generate/check as ERRA.
H
H
H
L
L
L
L
H
H
X
X
H
L
H
H
Generates parity from B latch data based on O/E. Generated parity → APAR.
Generated parity checked against latched BPAR and output as ERRB.
BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked
against BPAR and output as ERRB.
BPAR/B[0:7] → APAR/A[0:7]
Feed-through mode. Generated parity checked against BPAR and output as
ERRB. Generated parity also fed back through the A latch for generate/check as
ERRA.
L
L
H
H
L
L
H
H
L
Generates parity for A[0:7] based on O/E. Generated parity → BPAR. Gener-
ated parity checked against APAR and output as ERRA.
H
Generates parity from A[0:7] based on O/E. Generated parity → BPAR. Gener-
ated parity checked against APAR and output as ERRA. Generated parity also
fed back through the B latch for generate/check as ERRB.
L
L
H
H
L
L
X
L
Generates parity from A latch data based on O/E. Generated parity → BPAR.
Generated parity checked against latched APAR and output as ERRA.
H
H
APAR/A[0:7] → BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as
ERRA.
L
H
H
H
H
APAR/A[0:7] → BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as
ERRA. Generated parity also fed back through the B latch for generate/check as
ERRB.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Note 1: O/E = ODD/EVEN
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2
Functional Block Diagram
3
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DC Latchup Source Current
Over Voltage Latchup (I/O)
−500 mA
Absolute Maximum Ratings(Note 2)
10V
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
−65°C to +150°C
−55°C to +125°C
−55°C to +150°C
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
−40°C to +85°C
+4.5V to +5.5V
VCC Pin Potential to
Ground Pin
−0.5V to +7.0V
−0.5V to +7.0V
Minimum Input Edge Rate (∆V/∆t)
Data Input
Input Voltage (Note 3)
Input Current (Note 3)
Voltage Applied to Any Output
in the Disable or Power-
Off State
50 mV/ns
20 mV/ns
−30 mA to +5.0 mA
Enable Input
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to +5.5V
−0.5V to VCC
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
in the HIGH State
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
Recognized HIGH Signal
Recognized LOW Signal
CC
V
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
2.0
V
V
V
V
IH
V
V
V
0.8
IL
−1.2
Min
Min
I
I
I
I
I
= −18 mA (Non I/O Pins)
CD
OH
IN
2.5
2.0
= −3 mA, (A , B , APAR, BPAR)
n n
OH
OH
OL
Voltage
= −32 mA, (A , B , APAR, BPAR)
n n
V
V
Output LOW Voltage
Input Leakage Test
0.55
V
V
Min
0.0
= 64 mA, (A , B , APAR, BPAR)
n n
OL
ID
4.75
= 1.9 µA, (Non-I/O Pins)
ID
All Other Pins Grounded
I
I
I
I
I
Input HIGH Current
5
7
µA
µA
µA
µA
µA
Max
Max
V
V
V
= 2.7V (Non-I/O Pins) (Note 4)
IH
IN
IN
IN
= V (Non-I/O Pins)
CC
Input HIGH Current
Breakdown Test
= 7.0V (Non-I/O Pins)
BVI
BVIT
IL
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
100
−5
50
Max
V
= 5.5V (A , B , APAR, BPAR)
n n
IN
Max
V
V
V
= 0.5V (Non-I/O Pins) (Note 4)
= 0.0V (Non-I/O Pins)
IN
IN
+ I
Output Leakage Current
0V–5.5V
= 2.7V (A , B );
OUT n n
IH
IL
OZH
GAB and GBA = 2.0V
0V–5.5V V = 0.5V (A , B );
OUT
I
+ I
Output Leakage Current
−50
µA
OZL
n
n
GAB and GBA = 2.0V
I
I
I
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
−100
−275
50
mA
µA
µA
Max
Max
0.0V
V
V
V
= 0V (A , B , APAR, BPAR)
n n
OS
CEX
ZZ
OUT
OUT
OUT
= V (A , B , APAR, BPAR)
CC
n
n
100
= 5.5V (A , B , APAR, BPAR);
n n
All Others GND
I
I
I
I
I
Power Supply Current
Power Supply Current
Power Supply Current
250
34
µA
mA
Max
Max
Max
Max
Max
All Outputs HIGH
CCH
CCL
CCZ
CCT
CCD
All Outputs LOW, ERRA/B = HIGH (Note 5)
Outputs 3-STATE All Others at V or GND
250
2.5
0.4
µA
CC
Additional I /Input
mA
V = V − 2.1V All Others at V or GND
I CC CC
CC
Dynamic I
(Note 4)
:
No Load
mA/MHz
Outputs Open
GAB or GBA = GND, LE = HIGH
Non-I/O = GND or V
CC
CC
One bit toggling, 50% duty cycle
Note 4: Guaranteed, but not tested.
Note 5: Add 3.75 mA for each ERR LOW.
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4
DC Electrical Characteristics
(PLCC package)
Conditions
= 50 pF, R = 500Ω
V
Symbol
Parameter
Min
Typ
Max
Units
CC
C
L
L
V
Quiet Output Maximum Dynamic V
0.8
−0.8
3.0
1.1
V
V
V
V
V
5.0
5.0
5.0
5.0
5.0
T
T
T
T
T
= 25°C (Note 6)
= 25°C (Note 6)
= 25°C (Note 8)
= 25°C (Note 7)
= 25°C (Note 7)
OLP
OLV
OHV
IHD
ILD
OL
A
A
A
A
A
V
V
V
V
Quiet Output Minimum Dynamic V
−1.3
2.5
OL
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
2.2
1.8
0.8
0.5
Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V ), 0V to threshold (V ).
ILD
IHD
Guaranteed, but not tested.
Note 8: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and PLCC Package)
T
= +25°C
T = −40°C to +85°C
A
A
V
= +5.0V
= 50 pF
V
= 4.5V–5.5V
CC
CC
Symbol
Parameter
Units
C
C = 50 pF
L
L
Min
1.5
1.5
2.5
2.5
2.5
2.5
Typ
3.0
3.5
5.9
5.8
5.4
5.4
Max
4.8
4.8
9.2
9.2
8.5
8.5
Min
1.5
1.5
2.5
2.5
2.5
2.5
Max
t
t
t
t
t
t
Propagation Delay
A , to B
4.8
4.8
9.2
9.2
8.5
8.5
ns
ns
ns
PLH
PHL
PLH
PHL
PLH
PHL
n
n
Propagation Delay
A , B to BPAR, APAR
n
n
Propagation Delay
A , B to ERRA, ERRB
n
n
t
t
Propagation Delay
1.5
1.5
3.7
3.7
6.0
6.0
1.5
1.5
6.0
6.0
ns
PLH
PHL
APAR, BPAR to ERRA, ERRB
Propagation Delay
t
t
t
t
2.0
2.0
1.8
1.8
4.4
4.4
4.0
4.0
6.9
6.9
6.0
6.0
2.0
2.0
1.8
1.8
6.9
6.9
6.0
6.0
ns
ns
PLH
PHL
PLH
PHL
ODD/EVEN to APAR, BPAR
Propagation Delay
ODD/EVEN to ERRA, ERRB
Propagation Delay
t
t
t
t
t
t
1.5
1.5
1.5
1.5
2.5
2.5
3.8
3.8
3.2
3.2
5.9
5.7
6.0
6.0
4.6
4.6
8.8
8.8
1.5
1.5
1.5
1.5
2.5
2.5
6.0
6.0
4.6
4.6
8.8
8.8
ns
ns
PLH
PHL
PLH
PHL
PLH
PHL
SEL to APAR, BPAR
Propagation Delay
LEA, LEB to B , A
n
n
Propagation Delay
LEA, LEB to BPAR, APAR
Generate Mode
ns
ns
t
t
Propagation Delay
LEA, LEB to BPAR, APAR,
Feed Thru Mode
1.5
1.5
3.6
3.6
5.1
5.1
1.5
1.5
5.1
5.1
PLH
PHL
t
t
Propagation Delay
1.6
1.6
5.4
5.4
8.4
8.4
1.6
1.6
8.4
8.4
ns
ns
PLH
PHL
LEA, LEB to ERRA, ERRB
Output Enable Time
t
t
1.5
1.5
3.6
3.4
6.0
6.0
1.5
1.5
6.0
6.0
PZH
PZL
GBA or GAB to A ,
n
APAR or B , BPAR
n
t
t
Output Disable Time
1.0
1.0
4.0
3.3
6.0
6.0
1.0
1.0
6.0
6.0
ns
ns
PHZ
PLZ
GBA or GAB to A ,
n
APAR or B , BPAR
n
t
t
Propagation Delay
1.5
1.5
3.3
3.8
5.4
5.4
1.5
1.5
5.4
5.4
PLH PHL
APAR to BPAR, BPAR to APAR
5
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AC Electrical Characteristics
(SSOP Package)
T
= +25°C
T = −40°C to +85°C
A
A
V
= +5.0V
= 50 pF
V
= 4.5V–5.5V
CC
CC
Symbol
Parameter
Units
C
C = 50 pF
L
L
Min
1.5
1.5
2.5
2.5
2.5
2.5
Typ
3.0
3.5
5.9
5.8
5.4
5.4
Max
5.3
5.3
9.9
9.9
9.4
9.4
Min
1.5
1.5
2.5
2.5
2.5
2.5
Max
t
t
t
t
t
t
Propagation Delay
A , to B
5.3
5.3
9.9
9.9
9.4
9.4
ns
ns
ns
PLH
PHL
PLH
PHL
PLH
PHL
n
n
Propagation Delay
A , B to BPAR, APAR
n
n
Propagation Delay
A , B to ERRA, ERRB
n
n
t
t
Propagation Delay
1.5
1.5
3.7
3.7
6.5
6.5
1.5
1.5
6.5
6.5
ns
PLH
PHL
APAR, BPAR to ERRA, ERRB
Propagation Delay
t
t
t
t
2.0
2.0
1.8
1.8
4.4
4.4
4.0
4.0
7.4
7.4
6.5
6.5
2.0
2.0
1.8
1.8
7.4
7.4
6.5
6.5
ns
ns
PLH
PHL
PLH
PHL
ODD/EVEN to APAR, BPAR
Propagation Delay
ODD/EVEN to ERRA, ERRB
Propagation Delay
t
t
t
t
t
t
1.5
1.5
1.5
1.5
2.5
2.5
3.8
3.8
3.2
3.2
5.9
5.7
6.5
6.5
5.1
5.1
9.2
9.2
1.5
1.5
1.5
1.5
2.5
2.5
6.5
6.5
5.1
5.1
9.2
9.2
ns
ns
PLH
PHL
PLH
PHL
PLH
PHL
SEL to APAR, BPAR
Propagation Delay
LEA, LEB to B , A
n
n
Propagation Delay
LEA, LEB to BPAR, APAR
Generate Mode
ns
ns
t
t
Propagation Delay
LEA, LEB to BPAR, APAR,
Feed Thru Mode
1.5
1.5
3.6
3.6
5.6
5.6
1.5
1.5
5.6
5.6
PLH
PHL
t
t
t
t
Propagation Delay
1.6
1.6
1.5
1.5
5.4
5.4
3.6
3.4
8.9
8.9
6.5
6.5
1.6
1.6
1.5
1.5
8.9
8.9
6.5
6.5
ns
ns
PLH
PHL
LEA, LEB to ERRA, ERRB
Output Enable Time
PZH
PZL
GBA or GAB to A ,
n
APAR or B , BPAR
n
t
t
Output Disable Time
1.0
1.0
4.0
3.3
6.5
6.5
1.0
1.0
6.5
6.5
ns
ns
PHZ
PLZ
GBA or GAB to A ,
n
APAR or B , BPAR
n
t
t
Propagation Delay
1.5
1.5
3.3
3.8
5.9
5.9
1.5
1.5
5.9
5.9
PLH
PHL
APAR to BPAR, BPAR to APAR
AC Operating Requirements
T
= +25°C
T = −40°C to +85°C
A
A
V
= +5.0V
V
= 4.5V–5.5V
CC
CC
Symbol
Parameter
Units
C
= 50 pF
C = 50 pF
L
L
Min
Max
Min
1.5
1.5
1.0
1.0
3.0
Max
t (H)
Setup Time, HIGH or LOW A ,
1.5
1.5
1.0
1.0
3.0
ns
ns
ns
S
n
t (L)
APAR to LEA or B , BPAR to LEB
n
S
t
t
t
(H)
(L)
Hold Time, HIGH or LOW A ,
n
H
APAR to LEA or B , BPAR to LEB
n
H
(H)
Pulse Width, HIGH
LEA or LEB
W
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6
Extended AC Electrical Characteristics
(SOIC and PLCC Package)
T
= +25°C
T = −40°C to +85°C T = −40°C to +85°C
A A
A
V
= +5.0V
= 50 pF
V
= 4.5V–5.5V
V
= 4.5V–5.5V
CC
CC
CC
C
C
= 250 pF
C = 250 pF
L
L
L
Symbol
Parameter
Units
9 Outputs Switching
(Note 9)
1 Output Switching 9 Outputs Switching
(Note 10) (Note 11)
Min
Typ
Max
Min
Max
Min
Max
f
t
t
t
t
t
t
t
t
Max Toggle Frequency
Propagation Delay
100
MHz
ns
TOGGLE
PLH
1.5
1.5
1.5
1.5
2.5
2.5
6.2
6.2
2.0
2.0
2.0
2.0
3.0
3.0
3.0
3.0
7.2
7.2
2.5
2.5
2.5
2.0
3.5
3.5
9.5
9.5
A
to B
n
PHL
n
Propagation Delay
APAR to BPAR
6.8
8.0
10.0
10.0
13.5
13.5
ns
PLH
6.8
8.0
PHL
Propagation Delay
10.0
10.0
12.5
12.5
12.0
12.0
ns
ns
PLH
A , B to BPAR, APAR
PHL
n
n
Propagation Delay
(Note 13)
(Note 13)
(Note 13)
PLH
A , B to ERRA, ERRB
PHL
n
n
t
t
Propagation Delay
2.0
2.0
9.0
9.0
(Note 13)
ns
PLH
PHL
APAR, BPAR to ERRA, ERRB
Propagation Delay
t
t
t
t
(Note 13)
(Note 13)
2.5
2.5
2.0
2.0
9.9
9.9
8.8
8.8
(Note 13)
(Note 13)
ns
ns
PLH
PHL
PLH
PHL
ODD/EVEN to APAR, BPAR
Propagation Delay
ODD/EVEN to ERRA, ERRB
Propagation Delay
t
t
t
t
t
t
t
t
(Note 13)
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
9.5
9.5
(Note 13)
ns
ns
ns
ns
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
SEL to APAR, BPAR
Propagation Delay
1.5
1.5
1.5
1.5
5.7
5.7
9.5
9.5
7.9
2.5
10.0
10.0
13.0
13.0
LEA, LEB to B , A
7.9
2.5
2.5
2.5
n
n
Propagation Delay
12.0
12.0
11.5
11.5
LEA, LEB to BPAR, APAR
Propagation Delay
(Note 13)
(Note 13)
LEA, LEB to ERRA, ERRB
Output enable time
t
t
1.5
1.5
7.0
7.0
2.0
2.0
8.5
8.5
2.5
2.5
10.5
10.5
PZH
PZL
ns
ns
GBA or GAB to A ,
n
APAR or B , BPAR
n
t
t
Output disable time
1.0
1.0
6.5
6.5
PHZ
PLZ
(Note 12)
(Note 12)
GBA or GAB to A ,
n
APAR or B , BPAR
n
Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load
Note 12: The 3-STATE delay time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Note 13: Not applicable for multiple output switching.
7
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Extended AC Electrical Characteristics
(SSOP Package)
T
= +25°C
T = −40°C to +85°C T = −40°C to +85°C
A A
A
V
= +5.0V
= 50 pF
V
= 4.5V–5.5V
V
= 4.5V–5.5V
CC
CC
CC
C
C
= 250 pF
C
= 250 pF
L
L
L
Symbol
Parameter
Units
9 Outputs Switching
(Note 14)
1 Output Switching 9 Outputs Switching
(Note 15) (Note 16)
Min
Typ
Max
Min
Max
Min
Max
f
Max Toggle Frequency
Propagation Delay
100
MHz
ns
TOGGLE
t
1.5
1.5
1.5
1.5
2.5
2.5
6.7
6.7
2.0
2.0
2.0
2.0
3.0
3.0
3.0
3.0
7.7
7.7
2.5
2.5
2.5
2.0
3.5
3.5
10.1
10.1
10.6
10.6
14.3
14.3
PLH
t
A to B
n n
PHL
t
Propagation Delay
APAR to BPAR
7.3
8.5
ns
PLH
t
7.3
8.5
PHL
t
Propagation Delay
10.7
10.7
13.2
13.2
12.9
12.9
ns
ns
PLH
t
A , B to BPAR, APAR
n n
PHL
t
Propagation Delay
(Note 18)
(Note 18)
(Note 18)
PLH
t
A , B to ERRA, ERRB
PHL
n
n
t
Propagation Delay
2.0
2.0
9.5
9.5
(Note 18)
ns
PLH
t
APAR, BPAR to ERRA, ERRB
Propagation Delay
PHL
t
(Note 18)
(Note 18)
2.5
2.5
2.0
2.0
10.4
10.4
9.3
(Note 18)
(Note 18)
ns
ns
PLH
t
ODD/EVEN to APAR, BPAR
Propagation Delay
PHL
t
PLH
t
9.3
ODD/EVEN to ERRA, ERRB
Propagation Delay
PHL
t
(Note 18)
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
10.0
10.0
8.4
(Note 18)
ns
ns
ns
ns
PLH
t
SEL to APAR, BPAR
Propagation Delay
PHL
t
1.5
1.5
1.5
1.5
6.2
6.2
2.5
10.6
10.6
13.6
13.6
PLH
t
LEA, LEB to B , A
n
8.4
2.5
2.5
2.5
PHL
n
t
Propagation Delay
10.0
10.0
12.5
12.5
12.0
12.0
PLH
t
LEA, LEB to BPAR, APAR
Propagation Delay
PHL
t
(Note 18)
(Note 18)
PLH
t
LEA, LEB to ERRA, ERRB
Output enable time
PHL
t
1.5
1.5
7.5
7.5
2.0
2.0
9.0
9.0
2.5
2.5
11.1
11.1
PZH
t
ns
ns
GBA or GAB to A ,
n
PZL
APAR or B , BPAR
n
t
Output disable time
1.0
1.0
7.0
7.0
PHZ
t
(Note 17)
(Note 17)
GBA or GAB to A ,
n
PLZ
APAR or B , BPAR
n
Note 14: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 15: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 16: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load
Note 17: The 3-STATE delay time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Note 18: Not applicable for multiple output switching.
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8
Skew
(PLCC package) (Note 2)
T
= −40°C to +85°C
T = −40°C to +85°C
A
A
V
= 4.5V–5.5V
V
= 4.5V–5.5V
CC
CC
C
= 50 pF
C = 250 pF
L
L
Symbol
Parameter
Units
9 Outputs Switching
9 Outputs Switching
(Note 19)
Max
(Note 20)
Max
t
Pin to Pin Skew
1.0
2.0
ns
ns
ns
ns
ns
OSHL
(Note 21)
HL Transitions
Pin to Pin Skew
LH Transitions
Duty Cycle
t
1.1
2.0
2.0
3.0
2.1
3.5
3.5
4.0
OSLH
(Note 21)
t
PS
(Note 22)
LH–HL Skew
Pin to Pin Skew
t
OST
(Note 21)
LH/HL Transitions
Device to Device Skew
LH/HL Transitions
t
PV
(Note 23)
Note 19: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 20: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 21: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (t
), LOW to HIGH (t
), or any combination switching LOW to HIGH and/or HIGH to
OSLH
OSHL
LOW (t
). This specification is guaranteed but not tested. Skew applies to propagation delays individually; i.e., A to B separate from LEA to A .
n n n
OST
Note 22: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 23: Propagation delay variation for a given set of conditions (i.e., temperature and V ) from device to device. This specification is guaranteed but not
CC
tested.
Capacitance
Conditions
Symbol
Parameter
Typ
Units
T
= 25°C
A
C
C
Input Pin Capacitance
Output Capacitance
5.0
pF
pF
V
V
= 0V
IN
CC
(Note 24)
11.0
= 5.0V
I/O
CC
Note 24: C is measured at frequency, f = 1 MHz, per MIL-STD-883B, Method 3012.
I/O
9
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AC Path
A , APAR → B , BPAR
n
n
(B , BPAR → A , APAR)
n
n
FIGURE 1.
A
→ BPAR
n
(B → APAR)
n
FIGURE 2.
A
→ ERRA
n
(B → ERRB)
n
FIGURE 3.
O/E → ERRA
O/E → ERRB
FIGURE 4.
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10
AC Path (Continued)
O/E → BPAR
(O/E → APAR)
FIGURE 5.
APAR → ERRA
(BPAR → ERRB)
FIGURE 6.
FIGURE 7.
ZH, HZ
FIGURE 8.
11
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AC Path (Continued)
ZL, LZ
FIGURE 9.
SEL → BPAR
(SEL → APAR)
FIGURE 10.
LEA → BPAR, B[0:7]
(LEB → APAR, A[0:7])
FIGURE 11.
TS(H), TH(H)
LEA → APAR, A[0:7]
(LEB → BPAR, B[0:7])
FIGURE 12.
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12
AC Path (Continued)
TS(L), TH(L)
LEA → APAR, A[0:7]
(LEB → BPAR, B[0:7])
FIGURE 13.
FIGURE 14.
13
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AC Loading
*Includes jig and probe capacitance
V
M = 1.5V
FIGURE 15. Standard AC Test Load
FIGURE 16.
Input Pulse Requirements
Amplitude
Rep. Rate
tW
tr
tf
3.0V
1 MHz
500 ns
2.5 ns 2.5 ns
FIGURE 17. Test Input Signal Requirements
AC Waveforms
FIGURE 18. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 20. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 19. Propagation Delay,
Pulse Width Waveforms
FIGURE 21. Setup Time, Hold Time
and Recovery Time Waveforms
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14
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body
Package Number M28B
28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA28
15
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square
Package Number V28A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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