74ABT374CPC [FAIRCHILD]
Octal D-Type Flip-Flop with 3-STATE Outputs; 八路D型IP- FL佛罗里达州运与三态输出
| 型号： | 74ABT374CPC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal D-Type Flip-Flop with 3-STATE Outputs |
| 文件： | 总11页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1992
Revised November 1999
74ABT374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
Features
The ABT374 is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-STATE outputs for
bus-oriented applications. A buffered Clock (CP) and Out-
put Enable (OE) are common to all flip-flops.
■ Edge-triggered D-type inputs
■ Buffered positive edge-triggered clock
■ 3-STATE outputs for bus-oriented applications
■ Output sink capability of 64 mA, source capability of
32 mA
■ Guaranteed output skew
■ Guaranteed multiple output switching specifications
■ Output switching specified for both 50 pF and 250 pF
loads
■ Guaranteed simultaneous switching, noise level and
dynamic threshold performance
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Non-destructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT374CSC
74ABT374CSJ
74ABT374CMSA
74ABT374CMTC
74ABT374CPC
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MSA20
MTC20
N20A
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
CP
Description
Data Inputs
Clock Pulse Input (Active Rising Edge)
3-STATE Output Enable Input (Active LOW)
3-STATE Outputs
OE
O0–O7
© 1999 Fairchild Semiconductor Corporation
DS011510
www.fairchildsemi.com
Functional Description
Function Table
The ABT374 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When OE is
HIGH, the outputs are in a high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Inputs
OE CP
Internal Outputs
Function
D
L
Q
NC
NC
L
O
Z
H
H
H
H
L
H
H
Hold
Hold
Load
Load
H
L
Z
Z
H
L
H
Z
L
L
Data Available
L
H
L
H
H
Data Available
L
H
H
NC
NC
NC
NC
No Change in Data
No Change in Data
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
−65°C to +150°C
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
−55°C to +125°C
−55°C to +150°C
Free Air Ambient Temperature
Supply Voltage
−40°C to +85°C
+4.5V to +5.5V
V
CC Pin Potential to
Ground Pin
Minimum Input Edge Rate (∆V/∆t)
Data Input
−0.5V to +7.0V
−0.5V to +7.0V
50 mV/ns
20 mV/ns
100mV/ns
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Enable Input
−30 mA to +5.0 mA
Clock Input
Power-Off State
−0.5V to 5.5V
−0.5V to VCC
in the HIGH State
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Latchup Source Current:
−150 mA
OE Pin
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
(Across Comm Operating Range)
Other Pins
−500 mA
Over Voltage Latchup (I/O)
10V
Note 2: Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
VCC
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
VIH
2.0
V
V
V
V
V
V
Recognized HIGH Signal
Recognized LOW Signal
VIL
Input LOW Voltage
0.8
VCD
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
−1.2
Min
Min
Min
Min
I
I
I
I
IN = −18 mA
OH = −3 mA
OH = −32 mA
OL = 64 mA
2.5
2.0
VOL
IIH
Output LOW Voltage
Input HIGH Current
0.55
1
V
V
V
V
V
IN = 2.7V (Note 4)
µA
µA
µA
Max
Max
Max
1
IN = VCC
IBVI
IIL
Input HIGH Current Breakdown Test
Input LOW Current
7
IN = 7.0V
−1
−1
IN = 0.5V (Note 4)
IN = 0.0V
VID
Input Leakage Test
4.75
V
0.0
IID = 1.9 µA, All Other Pins Grounded
IOZH
Output Leakage Current
10
µA
0 − 5.5V
VOUT = 2.7V; OE = 2.0V
IOZL
Output Leakage Current
−10
µA
0 − 5.5V
VOUT = 0.5V; OE = 2.0V
VOUT = 0.0V
IOS
Output Short-Circuit Current
Output High Leakage Current
Bus Drainage Test
−100
−275
50
mA
µA
µA
µA
mA
Max
Max
0.0
ICEX
IZZ
ICCH
ICCL
ICCZ
ICCT
VOUT = VCC
100
50
VOUT = 5.5V; All Others VCC or GND
All Outputs HIGH
Power Supply Current
Power Supply Current
Max
Max
30
All Outputs LOW
Power Supply Current
50
µA
Max
OE = VCC; All Others at VCC or GND
VI = VCC − 2.1V
Additional ICC/Input
Outputs Enabled
2.5
2.5
2.5
mA
mA
mA
Outputs 3-STATE
Outputs 3-STATE
Max
Enable Input VI = VCC − 2.1V
Data Input VI = VCC − 2.1V
All Others at VCC or GND
Outputs OPEN
ICCD
Dynamic ICC
(Note 4)
No Load
mA/
Max
0.30
MHz
OE = GND, (Note 3)
One Bit Toggling, 50% Duty Cycle
Note 3: For 8-bit toggling, ICCD <0.8 mA/MHz.
Note 4: Guaranteed, but not tested.
3
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DC Electrical Characteristics
(SOIC package)
Conditions
VCC
Symbol
Parameter
Min
Typ
Max
Units
C
L = 50 pF, RL = 500Ω
VOLP
VOLV
VOHV
VIHD
VILD
Quiet Output Maximum Dynamic VOL
0.5
−0.9
3.0
0.8
V
V
V
V
V
5.0
5.0
5.0
5.0
5.0
TA = 25°C (Note 5)
TA = 25°C (Note 5)
TA = 25°C (Note 6)
TA = 25°C (Note 7)
TA = 25°C (Note 7)
Quiet Output Minimum Dynamic VOL
−1.3
2.5
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
2.0
1.6
1.3
0.8
Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested.
Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package)
T
A = −55°C to
+125°C
TA = +25°C
TA = −40°C to +85°C
VCC = +5.0V
VCC = 4.5V to 5.5V
VCC = 4.5V to 5.5V
Symbol
Parameter
Units
CL = 50 pF
C
L = 50 pF
C
L = 50 pF
Min
150
2.0
2.0
1.5
1.5
1.5
1.5
Typ
200
3.2
3.3
3.1
3.1
3.6
3.4
Max
Min
150
1.4
2.0
0.8
1.5
1.3
1.0
Max
Min
150
2.0
2.0
1.5
1.5
1.5
1.5
Max
fMAX
Maximum Clock Frequency
Propagation Delay
CP to On
MHz
ns
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
5.0
5.0
5.3
5.3
5.4
5.4
6.6
7.6
5.7
7.2
7.2
7.0
5.0
5.0
5.3
5.3
5.4
5.4
Output Enable Time
ns
ns
Output Disable Time
AC Operating Requirements
T
A = +25°C
CC = +5.0V
L = 50 pF
Max
T
A = −55°C to +125°C
CC = 4.5V to 5.5V
L = 50 pF
Max
T
A = −40°C to +85°C
CC = 4.5V to 5.5V
L = 50 pF
Max
V
V
V
Symbol
Parameter
Units
C
C
C
Min
1.5
1.5
1.0
1.0
3.0
3.0
Min
Min
tS(H)
Setup Time, HIGH
2.5
2.5
2.5
2.5
3.3
3.3
1.0
1.5
1.0
1.0
3.0
3.0
ns
ns
ns
tS(L)
or LOW Dn to CP
Hold Time, HIGH
or LOW Dn to CP
Pulse Width, CP
HIGH or LOW
tH(H)
t
H(L)
tW(H)
tW(L)
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4
Extended AC Electrical Characteristics
(SOIC Package)
T
A = −40°C to +85°C
CC = 4.5V to 5.5V
L = 50 pF
T
A = −40°C to +85°C
CC = 4.5V to 5.5V
T
A = −40°C to +85°C
CC = 4.5V to 5.5V
L = 250 pF
V
V
V
C
CL = 250 pF
C
Symbol
Parameter
Units
8 Outputs Switching
(Note 8)
(Note 9)
8 Outputs Switching
(Note 10)
Min
1.5
1.5
1.5
1.5
1.0
1.0
Max
5.7
5.7
6.2
6.2
5.5
5.5
Min
Max
7.8
7.8
8.0
8.0
Min
2.0
2.0
2.0
2.0
Max
10.0
10.0
10.5
10.5
tPLH
tPHL
tPZH
tPZL
tPHZ
tPZL
Propagation Delay
CP to On
2.0
2.0
2.0
2.0
ns
ns
ns
Output Enable Time
Output Disable Time
(Note 11)
(Note 11)
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11: The 3-STATE delay Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Skew (Note 16)
(SOIC Package)
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 50 pF
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 250 pF
V
V
C
C
Symbol
Parameter
Units
8 Outputs Switching
(Note 12)
8 Outputs Switching
(Note 13)
Max
Max
tOSHL
Pin to Pin Skew
1.0
1.0
1.8
2.0
2.5
1.8
1.8
4.3
4.3
4.6
ns
ns
ns
ns
ns
(Note 14)
tOSLH
HL Transitions
Pin to Pin Skew
LH Transitions
(Note 14)
tPS
Duty Cycle
(Note 13)
tOST
LH–HL Skew
Pin to Pin Skew
LH/HL Transitions
Device to Device Skew
LH/HL Transitions
(Note 14)
tPV
(Note 15)
Note 12: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 13: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (tOST). This specification is guaranteed but not tested.
Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Note 16: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Capacitance
Conditions
Symbol
Parameter
Typ
Units
(TA = 25°C)
CIN
COUT (Note 17)
Input Capacitance
Output Capacitance
5.0
9.0
pF
pF
V
V
CC = 0V
CC = 5.0V
Note 17: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
5
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AC Loading
*Includes jig and probe capacitance
FIGURE 2. VM = 1.5V
FIGURE 1. Standard AC Test Load
Input Pulse Requirements
Amplitude Rep. Rate
3.0V 1 MHz
tw
tr
tf
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MO-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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11
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