74ABT373CMTCX [FAIRCHILD]
8-Bit D-Type Latch ; 8位D类锁存器\n
| 型号： | 74ABT373CMTCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 8-Bit D-Type Latch
|
| 文件： | 总11页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1993
Revised November 1999
74ABT373
Octal Transparent Latch with 3-STATE Outputs
General Description
Features
The ABT373 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
■ 3-STATE outputs for bus interfacing
■ Output sink capability of 64 mA, source capability of
32 mA
■ Guaranteed output skew
■ Guaranteed multiple output switching specifications
■ Output switching specified for both 50 pF and 250 pF
loads
■ Guaranteed simultaneous switching, noise level and
dynamic threshold performance
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down
■ Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT373CSC
74ABT373CSJ
74ABT373CMSA
74ABT373CMTC
74ABT373CPC
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MSA20
MTC20
N20A
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
LE
Description
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-STATE Latch Outputs
OE
O0–O7
© 1999 Fairchild Semiconductor Corporation
DS011547
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Functional Description
Truth Table
The ABT373 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
Inputs
OE
Output
On
LE
Dn
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D
inputs at setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
H
H
L
L
L
H
L
H
L
L
X
X
O
n (no change)
X
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance State
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
−65°C to +150°C
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
−40°C to +85°C
+4.5V to +5.5
V
CC Pin Potential to Ground Pin
Minimum Input Edge Rate (∆V/∆t)
Data Input
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
−0.5V to +7.0V
50 mV/ns
20 mV/ns
−30 mA to +5.0 mA
Enable Input
Power-Off State
−0.5V to +5.5V
−0.5V to VCC
in the HIGH State
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
DC Latchup Source Current:
OE Pin −150 mA
(Across Comm Operating Range) Other Pins −500 mA
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Over Voltage Latchup (I/O)
10V
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
2.0
V
V
V
Recognized HIGH Signal
Recognized LOW Signal
VIL
Input LOW Voltage
0.8
VCD
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
−1.2
Min
Min
Min
Max
Max
Max
0.0
I
I
I
I
IN = −18 mA
OH = −3 mA
OH = −32 mA
OL = 64 mA
2.5
2.0
V
V
VOL
IIH
Output LOW Voltage
Input HIGH Current
0.55
1
V
V
V
V
V
IN = 2.7V (Note 4)
IN = VCC
µA
µA
µA
V
1
IBVI
IIL
Input HIGH Current Breakdown Test
Input LOW Current
7
IN = 7.0V
−1
−1
IN = 0.5V (Note 4)
IN = 0.0V
VID
Input Leakage Test
4.75
I
ID = 1.9 µA
All Other Pins Grounded
IOZH
IOZL
Output Leakage Current
Output Leakage Current
10
µA
µA
0 − 5.5V
0 − 5.5V
V
OUT = 2.7V; OE = 2.0V
−10
V
V
V
V
OUT = 0.5V; OE = 2.0V
OUT = 0.0V
IOS
Output Short-Circuit Current
Output High Leakage Current
Bus Drainage Test
−100
−275
50
mA
µA
µA
µA
mA
Max
Max
0.0
ICEX
IZZ
ICCH
ICCL
ICCZ
OUT = VCC
100
50
OUT = 5.5V; All Others GND
Power Supply Current
Power Supply Current
Max
Max
All Outputs HIGH
All Outputs LOW
30
Power Supply Current
50
µA
Max
OE = VCC
All Others at VCC or GND
VI = VCC − 2.1V
ICCT
Additional ICC/Input
Outputs Enabled
2.5
2.5
2.5
mA
mA
mA
Outputs 3-STATE
Outputs 3-STATE
Max
Enable Input VI = VCC − 2.1V
Data Input VI = VCC − 2.1V
All Others at VCC or GND
Outputs Open, LE = VCC
ICCD
Dynamic ICC
(Note 4)
No Load
mA/
Max
0.12
MHz
OE = GND, (Note 3)
One Bit Toggling, 50% Duty Cycle
Note 3: For 8 bits toggling, ICCD < 0.8 mA/MHz.
Note 4: Guaranteed, but not tested.
3
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DC Electrical Characteristics
(SOIC Package)
Conditions
VCC
Symbol
Parameter
Min
Typ
Max
Units
C
L = 50 pF, RL = 500Ω
VOLP
Quiet Output Maximum Dynamic VOL
0.4
−0.8
3.0
0.8
V
V
V
V
V
5.0
5.0
5.0
5.0
5.0
T
T
T
T
T
A = 25°C (Note 5)
A = 25°C (Note 5)
A = 25°C (Note 6)
A = 25°C (Note 7)
A = 25°C (Note 7)
VOLV
VOHV
VIHD
VILD
Quiet Output Minimum Dynamic VOL
−1.2
2.5
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
2.0
1.7
0.9
0.6
Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested.
Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Packages)
TA = +25°C
TA = −55°C to +125°C
TA = −40°C to +85°C
V
CC = +5.0V
V
CC = 4.5V to 5.5V
VCC = 4.5V to 5.5V
Symbol
Parameter
Units
C
L = 50 pF
CL = 50 pF
CL = 50 pF
Min
1.9
1.9
2.0
2.0
1.5
1.5
2.0
2.0
Typ
2.7
2.8
3.1
3.0
3.1
3.1
3.6
3.4
Max
4.5
4.5
5.0
5.0
5.3
5.3
5.4
5.4
Min
1.0
1.0
1.0
1.5
1.0
1.5
1.7
1.0
Max
Min
1.9
1.9
2.0
2.0
1.5
1.5
2.0
2.0
Max
tPLH
Propagation Delay
6.8
7.0
7.7
7.7
6.7
7.2
8.0
7.0
4.5
4.5
5.0
5.0
5.3
5.3
5.4
5.4
ns
ns
ns
ns
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Dn to On
Propagation Delay
LE to On
Output Enable Time
Output Disable Time
AC Operating Requirements
(SOIC and SSOP Packages)
T
A = +25°C
T
A = −55°C to +125°C
CC = 4.5V to 5.5V
T
A = −40°C to +85°C
VCC = +5.0V
V
VCC = 4.5V to 5.5V
Symbol
Parameter
Units
C
L = 50 pF
C
L = 50 pF
Max
C
L = 50 pF
Min
Typ
Max
Min
100
2.5
2.5
2.5
2.5
Min
Max
fTOGGLE
Max Toggle Frequency
Setup Time, HIGH
or LOW Dn to LE
Hold Time, HIGH
or LOW Dn to LE
Pulse Width,
100
MHz
ns
tS(H)
tS(L)
tH(H)
tH(L)
tW(H)
1.5
1.5
1.0
1.0
1.5
1.5
1.0
1.0
ns
ns
3.0
3.3
3.0
LE HIGH
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4
Extended AC Electrical Characteristics
(SOIC Package)
T
A = −40°C to +85°C
CC = 4.5V to 5.5V
L = 50 pF
T
A = −40°C to +85°C
CC = 4.5V to 5.5V
T
A = −40°C to +85°C
CC = 4.5V to 5.5V
L = 250 pF
V
V
V
C
C
L = 250 pF
C
Symbol
Parameter
Units
8 Outputs Switching
(Note 8)
8 Outputs Switching
(Note 10)
(Note 9)
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.0
1.0
Max
5.2
5.2
5.5
5.5
6.2
6.2
5.5
5.5
Min
2.0
2.0
2.0
2.0
2.0
2.0
Max
Min
2.0
2.0
2.0
2.0
2.0
2.0
Max
9.0
tPLH
Propagation Delay
6.8
6.8
7.5
7.5
8.0
8.0
ns
ns
ns
ns
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPZL
Dn to On
9.0
Propagation Delay
LE to On
9.5
9.5
Output Enable Time
10.5
10.5
Output Disable Time
(Note 11)
(Note 11)
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11: The 3-STATE delay times are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Skew
(SOIC Package)
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 50 pF
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 250 pF
V
V
C
C
Symbol
Parameter
Units
8 Outputs Switching
8 Outputs Switching
(Note 12)
Max
1.0
(Note 13)
Max
1.5
tOSHL (Note 14) Pin to Pin Skew, HL Transitions
OSLH (Note 14) Pin to Pin Skew, LH Transitions
ns
ns
ns
ns
ns
t
1.0
1.5
t
PS (Note 16)
tOST (Note 14)
PV (Note 15)
Duty Cycle, LH–HL Skew
1.4
3.5
Pin to Pin Skew, LH/HL Transitions
Device to Device Skew, LH/HL Transitions
1.5
3.9
t
2.0
4.0
Note 12: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or
HIGH-to-LOW (tOST). This specification is guaranteed but not tested.
Note 15: Propagation delay variation is for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but
not tested.
Note 16: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Capacitance
Conditions
Symbol
Parameter
Typ
Units
(TA = 25°C)
CIN
COUT (Note 17)
Input Capacitance
Output Capacitance
5
9
pF
pF
V
V
CC = 0V
CC = 5.0V
Note 17: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
5
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AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. Test Input Signal Levels
Amplitude Rep. Rate
3.0V 1 MHz
tw
tr
tf
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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11
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相关型号：
74ABT373CSCX_NL
Bus Driver, ABT Series, 1-Func, 8-Bit, True Output, BICMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20
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