74ABT245CSCX_NL [FAIRCHILD]
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| 型号： | 74ABT245CSCX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 暂无描述 |
| 文件： | 总11页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1991
Revised November 1999
74ABT245
Octal Bi-Directional Transceiver with 3-STATE Outputs
General Description
Features
The ABT245 contains eight non-inverting bidirectional buff-
ers with 3-STATE outputs and is intended for bus-oriented
applications. Current sinking capability is 64 mA on both
the A and B ports. The Transmit/Receive (T/R) input deter-
mines the direction of data flow through the bidirectional
transceiver. Transmit (active HIGH) enables data from A
Ports to B Ports; Receive (active LOW) enables data from
B Ports to A Ports. The Output Enable input, when HIGH,
disables both A and B ports by placing them in a HIGH Z
condition.
■ Bidirectional non-inverting buffers
■ A and B output sink capability of 64 mA, source
capability of 32 mA
■ Guaranteed output skew
■ Guaranteed multiple output switching specifications
■ Output switching specified for both 50 pF and 250 pF
loads
■ Guaranteed simultaneous switching, noise level and
dynamic threshold performance
■ Guaranteed latchup protection
■ High impedance glitch-free bus loading during entire
power up and power down cycle
■ Non-destructive hot insertion capability
■ Disable time is less than enable time to avoid bus
contention
Ordering Code:
Order Number Package Number
Package Description
74ABT245CSC
74ABT245CSJ
74ABT245CMSA
74ABT245CMTC
74ABT245CPC
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MSA20
MTC20
N20A
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
OE
Description
Output Enable Input (Active LOW)
Transmit/Receive Input
T/R
A0–A7
B0–B7
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation
DS010945
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Logic Symbol
Truth Table
Inputs
Output
OE
L
T/R
L
Bus B Data to Bus A
Bus A Data to Bus B
HIGH Z State
L
H
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
−40°C to +85°C
+4.5V to +5.5V
V
CC Pin Potential to Ground Pin
Minimum Input Edge Rate (∆V/∆t)
Data Input
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
−0.5V to +7.0V
50 mV/ns
20 mV/ns
−30 mA to +5.0 mA
Enable Input
Power-off State
−0.5V to 5.5V
−0.5V to VCC
in the HIGH State
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
DC Latchup Source Current
Over Voltage Latchup (I/O)
−500 mA
10V
Note 2: Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
2.0
V
V
Recognized HIGH Signal
Recognized LOW Signal
VIL
Input LOW Voltage
0.8
VCD
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
−1.2
V
Min
I
I
I
I
IN = −18 mA (OE, T/R)
OH = −3 mA (An, Bn)
OH = −32 mA (An, Bn)
OL = 64 mA (An, Bn)
2.5
2.0
V
V
V
Min
Min
Min
VOL
IIH
Output LOW Voltage
Input HIGH Current
0.55
1
V
IN = 2.7V (OE, T/R)
IN = VCC (OE, T/R)
µA
Max
1
V
IBVI
IBVIT
IIL
Input HIGH Current Breakdown Test
Input HIGH Current Breakdown Test (I/O)
Input LOW Current
7
µA
µA
Max
Max
V
IN = 7.0V (OE, T/R)
IN = 5.5V (An, Bn)
100
−1
V
V
IN = 0.5V (OE, T/R)
IN = 0.0V (OE, T/R)
µA
Max
0.0
−1
V
VID
Input Leakage Test
4.75
V
I
ID = 1.9 µA (OE, T/R)
All Other Pins Grounded
I
IH + IOZH
Output Leakage Current
Output Leakage Current
10
µA
µA
0 − 5.5V
0 − 5.5V
V
OUT = 2.7V (An, Bn); OE = 2.0V
IIL + I OZL
−10
V
V
V
V
OUT = 0.5V (An, Bn); OE = 2.0V
IOS
ICEX
IZZ
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
−100
−275
50
mA
µA
µA
Max
Max
0.0
OUT = 0.0V (An, Bn)
OUT = V CC (An, Bn)
100
OUT = 5.5V (An, Bn);
All Others GND
All Outputs HIGH
All Outputs LOW
ICCH
ICCL
ICCZ
Power Supply Current
Power Supply Current
50
30
µA
Max
Max
mA
Power Supply Current
50
µA
Max
OE = VCC, T/R = GND or VCC
All Other GND or VCC
VI = V CC − 2.1V
;
ICCT
Additional
I CC/Input
Outputs Enabled
Outputs 3-STATE
2.5
2.5
mA
mA
Max
OE, T/R VI = VCC − 2.1V
Data Input VI = VCC − 2.1V
All Others at VCC or GND.
Outputs Open
Outputs 3-STATE
50
µA
ICCD
Dynamic ICC
No Load
0.1
mA/
Max
MHz
OE = GND, T/R = GND or VCC
One Bit Toggling, 50% Duty Cycle
3
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DC Electrical Characteristics
(SOIC package)
Conditions
VCC
Symbol
Parameter
Min
Typ
Max
Units
C
L = 50 pF, RL = 500Ω
VOLP
VOLV
VOHV
VIHD
VILD
Quiet Output Maximum Dynamic VOL
0.7
−1.0
3.1
1.0
V
V
V
V
V
5.0
5.0
5.0
5.0
5.0
TA = 25°C (Note 3)
TA = 25°C (Note 3)
TA = 25°C (Note 5)
TA = 25°C (Note 4)
TA = 25°C (Note 4)
Quiet Output Minimum Dynamic VOL
−1.3
2.7
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
2.0
1.7
0.9
0.6
Note 3: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 4: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).
Guaranteed, but not tested.
Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP package)
T
A = +25°C
T
A = −55°C to +125°C
CC = 4.5V–5.5V
L = 50 pF
Max
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 50 pF
Max
V
CC = +5V
V
V
Symbol
Parameter
Units
C
L = 50 pF
C
C
Min
1.0
1.0
1.5
1.5
1.0
1.0
Typ
2.1
2.4
3.2
3.7
3.6
3.3
Max
3.6
3.6
6.0
6.0
6.1
5.6
Min
1.0
1.0
1.0
2.0
1.7
1.7
Min
1.0
1.0
1.5
1.5
1.0
1.0
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
Data to Outputs
Output Enable
Time
4.8
4.8
6.7
7.5
7.4
6.5
3.6
3.6
6.0
6.0
6.1
5.6
ns
ns
ns
Output Disable
Time
Extended AC Electrical Characteristics
(SOIC package)
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 250 pF
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 250 pF
−40°C to +85°C
VCC = 4.5V–5.5V
V
V
CL = 50 pF
C
C
Symbol
Parameter
Units
8 Outputs Switching
(Note 6)
1 Output Switching
(Note 7)
8 Outputs Switching
(Note 8)
Min
Typ
Max
Min
Max
Min
Max
fTOGGLE
tPLH
Max Toggle Frequency
Propagation Delay
Data to Outputs
100
MHz
ns
1.5
1.5
1.5
1.5
1.0
1.0
5.0
5.0
6.5
6.5
6.5
5.6
1.5
1.5
2.5
2.5
6.0
6.0
7.5
7.5
2.5
2.5
2.5
2.5
8.5
8.5
tPHL
tPZH
tPZL
Output Enable Time
9.5
ns
ns
11.0
tPHZ
Output Disable Time
(Note 9)
(Note 9)
tPLZ
Note 6: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 7: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 8: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 9: The 3-STATE delays are dominated by the RC network (500Ω, 250 pF) on the output and have been excluded from the datasheet.
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4
Skew
(SOIC package)
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 50 pF
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 250 pF
V
V
C
C
Symbol
Parameter
Units
8 Outputs Switching
(Note 12)
8 Outputs Switching
(Note 13)
Max
Max
tOSHL
Pin to Pin Skew
HL Transitions
Pin to Pin Skew
LH Transitions
Duty Cycle
1.3
1.0
2.0
2.0
2.0
2.3
1.8
3.5
3.5
3.5
ns
ns
ns
ns
ns
(Note 10)
tOSLH
(Note 10)
tPS
(Note 14)
tOST
LH–HL Skew
Pin to Pin Skew
(Note 10)
tPV
LH/HL Transitions
Device to Device Skew
LH/HL Transitions
(Note 11)
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or
HIGH-to-LOW (tOST). The specification is guaranteed but not tested.
Note 11: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)
Note 13: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Capacitance
Conditions
Symbol
Parameter
Typ
Units
T
A = 25°C
CIN
CI/O (Note 15)
Input Capacitance
I/O Capacitance
5.0
pF
pF
V
V
CC = 0V (OE, T/R)
CC = 5.0V (An, Bn)
11.0
Note 15: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
5
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AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. Test Input Signal Levels
Amplitude Rep. Rate
3.0V 1 MHz
tW
tr
tf
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms
for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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11
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