2N6790 [FAIRCHILD]

3.5A, 200V, 0.800 Ohm, N-Channel Power; 3.5A , 200V , 0.800 Ohm的N通道功率
2N6790
型号: 2N6790
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

3.5A, 200V, 0.800 Ohm, N-Channel Power
3.5A , 200V , 0.800 Ohm的N通道功率

晶体 晶体管 功率场效应晶体管 开关 脉冲 局域网
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2N6790  
Data Sheet  
December 2001  
3.5A, 200V, 0.800 Ohm, N-Channel Power  
MOSFET  
Features  
• 3.5A, 200V  
The 2N6790 is an N-Channel enhancement mode silicon  
gate power MOS field effect transistor designed for  
applications such as switching regulators, switching  
converters, motor drivers, relay drivers, and drivers for high  
power bipolar switching transistors requiring high speed and  
low gate drive power. This device can be operated directly  
from an integrated circuit.  
• r = 0.800Ω  
DS(ON)  
• SOA is Power Dissipation Limited  
• Nanosecond Switching Speeds  
• Linear Transfer Characteristics  
• High Input Impedance  
• Majority Carrier Device  
Ordering Information  
• Related Literature  
PART NUMBER  
PACKAGE  
BRAND  
2N6790  
- TB334 “Guidelines for Soldering Surface Mount  
Components to PC Boards”  
2N6790  
TO-205AF  
NOTE: When ordering, include the entire part number.  
Symbol  
D
G
S
Packaging  
JEDEC TO-205AF  
DRAIN  
(CASE)  
SOURCE  
GATE  
©2001 Fairchild Semiconductor Corporation  
2N6790 Rev. B  
2N6790  
o
Absolute Maximum Ratings  
T = 25 C, Unless Otherwise Specified  
C
2N6790  
200  
200  
3.5  
2.25  
14  
20  
3.5  
14  
20  
UNITS  
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
V
V
A
A
A
V
A
A
W
DS  
Drain to Gate Voltage (R  
= 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V  
GS  
DGR  
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I  
D
D
o
T
= 100 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I  
C
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
DM  
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
GS  
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
S
Pulse Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
SM  
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P  
D
o
o
Above T = 25 C, Derate Linearly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
0.16  
-55 to 150  
W/ C  
C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T  
C
J
STG  
Maximum Temperature for Soldering  
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T  
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T  
o
o
300  
260  
C
C
L
pkg  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
o
o
1. T = 25 C to 125 C.  
J
o
Electrical Specifications  
T = 25 C, Unless Otherwise Specified  
C
PARAMETER  
SYMBOL  
BV  
TEST CONDITIONS  
= 0.25mA, V = 0V  
MIN  
TYP  
MAX  
-
UNITS  
V
Drain to Source Breakdown Voltage  
Gate to Threshold Voltage  
I
200  
-
DSS  
GS(TH)  
D
GS  
= V , I = 1.0mA  
V
V
V
V
V
2
-
4
V
GS  
DS  
DS  
GS  
DS D  
Zero-Gate Voltage Drain Current  
I
= 200V, V  
= 0V  
= 0V  
= 0  
-
-
250  
1000  
100  
2.8  
0.800  
1.5  
1.5  
4.5  
600  
300  
80  
µA  
µA  
nA  
V
DSS  
GS  
GS  
DS  
o
= 160V, V  
T
T
= 125 C  
-
-
-
C
C
Gate to Source Leakage Current  
I
=
20V, V  
-
GSS  
Drain to Source On-Voltage (Note 2)  
Drain to Source On Resistance  
V
I
I
I
I
I
= 3.5A, V  
GS  
= 10V  
-
-
DS(ON)  
D
D
D
S
D
r
= 2.25A, V  
= 10V  
= 10V  
-
.5  
DS(ON)  
GS  
GS  
o
= 2.25A, V  
= 125 C  
-
-
Diode Forward Voltage  
Forward Transconductance (Note 2)  
Input Capacitance  
V
= 3.5A, V  
GS  
= 0V  
0.7  
1.5  
200  
60  
15  
-
-
V
SD  
g
= 2.25A, V  
= 5V  
2.25  
S
fs  
DS  
C
V
= 0V, V  
DS  
= 25V  
450  
pF  
pF  
pF  
ns  
ns  
ns  
ns  
W
ISS  
GS  
f = 1MHz  
Output Capacitance  
Reverse-Transfer Capacitance  
Turn-On Delay Time  
Rise Time  
C
150  
OSS  
RSS  
C
40  
-
t
I
= 2.25A  
40  
d(ON)  
D
V
74V, R = 50Ω  
G
GS  
t
-
-
50  
r
Turn-Off Delay Time  
Fall Time  
t
-
-
50  
d(OFF)  
t
-
-
50  
f
Safe Operating Area  
SOA  
V
V
= 160V, I = 125mA  
20  
20  
-
-
-
DS  
DS  
D
= 5.7V, I = 3.5A  
-
-
W
D
o
Thermal Resistance Junction to Case  
Thermal Resistance Junction to Ambient  
R
R
-
6.25  
175  
C/W  
θJC  
o
Free Air Operation  
-
-
C/W  
θJA  
Source to Drain Diode Specifications  
PARAMETER  
Reverse Recovery Time  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
350  
2.3  
MAX  
UNITS  
ns  
o
t
T = 150 C, I  
J
= 3.5A, dl /dt = 100A/µs  
SD  
-
-
rr  
SD  
o
Reverse Recovered Charge  
NOTES:  
Q
TJ = 150 C, I  
= 3.5A, dl /dt = 100A/µs  
SD  
µC  
RR  
SD  
2. Pulse test: pulse width 300µs, duty cycle 2%.  
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).  
©2001 Fairchild Semiconductor Corporation  
2N6790 Rev. B  
2N6790  
Typical Performance Curves Unless Otherwise Specified  
1.2  
1.0  
0.8  
5
4
3
0.6  
0.4  
2
1
0
0.2  
0
25  
50  
75  
100  
125  
150  
0
25  
50  
75  
100  
125  
150  
o
o
T
, CASE TEMPERATURE ( C)  
T , CASE TEMPERATURE ( C)  
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE  
TEMPERATURE  
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs  
CASE TEMPERATURE  
2
1.0  
0.5  
0.2  
P
DM  
0.1  
0.1  
t
1
0.05  
t
2
NOTES:  
DUTY FACTOR: D = t /t  
0.02  
0.01  
1
2
PEAK T = P  
J
x Z  
θJC  
x Z  
x R + T  
θJC C  
SINGLE PULSE  
-4  
DM  
θJC  
0.01  
-5  
10  
-3  
10  
-2  
10  
10  
0.1  
1
10  
T , RECTANGULAR PULSE DURATION (s)  
1
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE  
50  
8V  
10V  
OPERATION IN THIS AREA  
LIMITED BY r  
DS(ON)  
12  
8
80µs PULSE TEST  
10µs  
10  
1
7V  
100µs  
1.0ms  
V
= 6V  
GS  
10ms  
4
5V  
100ms  
o
T
T
= 25 C  
C
J
= MAX RATED  
DC  
0.1  
4V  
SINGLE PULSE  
0
0.05  
0
25  
50  
75  
100  
1
10  
100  
1000  
V
, DRAIN TO SOURCE (V)  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
DS  
FIGURE 4. FORWARD BIAS SAFE OPERATING AREAS  
FIGURE 5. OUTPUT CHARACTERISTICS  
©2001 Fairchild Semiconductor Corporation  
2N6790 Rev. B  
2N6790  
Typical Performance Curves Unless Otherwise Specified (Continued)  
12  
16  
12  
8
o
V
> I  
D(ON)  
x r MAX  
DS(ON)  
80µs PULSE TEST  
25 C  
10V  
9V  
8V  
DS  
o
-55 C  
80µs PULSE TEST  
V
= 7V  
o
GS  
8
125 C  
6V  
4
5V  
4V  
4
0
0
2
4
6
8
0
2
4
6
8
10  
V
, DRAIN TO SOURCE VOLTAGE (V)  
V
GS  
, GATE TO SOURCE VOLTAGE (V)  
DS  
FIGURE 6. SATURATION CHARACTERISTICS  
FIGURE 7. TRANSFER CHARACTERISTICS  
1.5  
1.0  
0.5  
0
2.2  
1.8  
1.4  
1.0  
0.6  
0.2  
PULSE DURATION = 2.0µs  
I
= 2A  
D
o
INITIAL T = 25 C  
J
V
= 10V  
GS  
V
= 10V  
GS  
V
= 20V  
GS  
0
5
10  
I , DRAIN CURRENT (A)  
15  
20  
-40  
0
40  
80  
120  
150  
o
T , JUNCTION TEMPERATURE ( C)  
D
J
FIGURE 8. DRAINTO SOURCE ON RESISTANCE vs GATE  
VOLTAGE AND DRAIN CURRENT  
FIGURE 9. NORMALIZED DRAINTO SOURCE ON  
RESISTANCE vs JUNCTION TEMPERATURE  
1.25  
1.15  
1.05  
0.95  
1000  
800  
600  
400  
200  
0
V
= 0V, f = 1MHz  
GS  
ISS  
C
C
C
= C  
+ C  
GS  
GD  
= C  
GD  
RSS  
OSS  
= C  
+ C  
GD  
DS  
C
ISS  
0.85  
0.75  
C
OSS  
C
RSS  
-40  
0
40  
80  
120  
160  
0
10  
20  
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
30  
40  
50  
o
T , JUNCTION TEMPERATURE ( C)  
V
J
FIGURE 10. NORMALIZED DRAINTO SOURCE BREAKDOWN  
VOLTAGE vs JUNCTION TEMPERATURE  
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE  
©2001 Fairchild Semiconductor Corporation  
2N6790 Rev. B  
2N6790  
Typical Performance Curves Unless Otherwise Specified (Continued)  
2
5.0  
4.25  
3.75  
10  
o
T
= -55 C  
80µs PULSE TEST  
J
o
T
= 25 C  
J
o
T
= 25 C  
J
o
T
= 150 C  
J
o
T
= 125 C  
3.0  
2.25  
1.50  
J
10  
o
T
= 150 C  
J
0.75  
0
o
T
= 25 C  
J
1
0
2
4
6
8
10  
12  
14  
0
1
2
3
4
I , DRAIN CURRENT (A)  
V
, SOURCE TO DRAIN VOLTAGE (V)  
D
SD  
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT  
FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE  
20  
I
= 7A  
D
V
= 160V  
= 100V  
= 40V  
DS  
15  
10  
V
DS  
V
DS  
5
0
0
4
8
12  
16  
20  
Q ,TOTAL GATE CHARGE (nC)  
g
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE  
©2001 Fairchild Semiconductor Corporation  
2N6790 Rev. B  
2N6790  
Test Circuits and Waveforms  
V
DS  
BV  
DSS  
L
t
P
V
DS  
I
VARY t TO OBTAIN  
P
AS  
+
-
V
DD  
R
REQUIRED PEAK I  
AS  
G
V
DD  
V
GS  
DUT  
t
P
I
AS  
0V  
0
0.01Ω  
t
AV  
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT  
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS  
t
t
ON  
OFF  
t
d(OFF)  
t
d(ON)  
t
t
f
r
R
L
V
DS  
90%  
90%  
+
V
DD  
10%  
10%  
R
G
0
0
-
DUT  
90%  
50%  
V
GS  
50%  
PULSE WIDTH  
10%  
V
GS  
FIGURE 17. SWITCHING TIME TEST CIRCUIT  
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS  
V
DS  
(ISOLATED  
SUPPLY)  
CURRENT  
REGULATOR  
V
DD  
Q
SAME TYPE  
AS DUT  
g(TOT)  
V
GS  
12V  
BATTERY  
0.2µF  
Q
gd  
50kΩ  
0.3µF  
Q
gs  
D
S
V
DS  
G
DUT  
0
0
I
G(REF)  
0
V
I
DS  
G(REF)  
I
CURRENT  
SAMPLING  
RESISTOR  
I
CURRENT  
SAMPLING  
RESISTOR  
G
D
FIGURE 19. GATE CHARGE TEST CIRCUIT  
FIGURE 20. GATE CHARGE WAVEFORMS  
©2001 Fairchild Semiconductor Corporation  
2N6790 Rev. B  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is  
not intended to be an exhaustive list of all such trademarks.  
â
SMART START™  
STAR*POWER™  
Stealth™  
VCX™  
FAST  
ACEx™  
Bottomless™  
CoolFET™  
OPTOLOGIC™  
OPTOPLANAR™  
PACMAN™  
FASTr™  
FRFET™  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
SyncFET™  
GlobalOptoisolator™  
GTO™  
HiSeC™  
ISOPLANAR™  
LittleFET™  
MicroFET™  
MicroPak™  
MICROWIRE™  
CROSSVOLT™  
DenseTrench™  
DOME™  
POP™  
Power247™  
PowerTrenchâ  
QFET™  
EcoSPARK™  
E2CMOSTM  
TinyLogic™  
QS™  
EnSignaTM  
TruTranslation™  
UHC™  
QT Optoelectronics™  
Quiet Series™  
SILENTSWITCHERâ  
FACT™  
FACT Quiet Series™  
UltraFETâ  
STAR*POWER is used under license  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER  
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD  
DOES NOT ASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OFANY PRODUCT  
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT  
RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION.  
As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant into  
the body, or (b) support or sustain life, or (c) whose  
failure to perform when properly used in accordance  
with instructions for use provided in the labeling, can be  
reasonably expected to result in significant injury to the  
user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or  
In Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
Rev. H4  

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