29F53 [FAIRCHILD]
8-Bit Registered Transceiver; 8位寄存收发器型号: | 29F53 |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | 8-Bit Registered Transceiver |
文件: | 总8页 (文件大小:72K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
April 1988
Revised August 1999
29F52•29F53
8-Bit Registered Transceiver
General Description
Features
The 29F52 and 29F53 are 8-bit registered transceivers.
Two 8-bit back to back registers store data flowing in both
directions between two bidirectional buses. Separate clock,
clock enable and 3-STATE output enable signals are pro-
vided for each register. The A0–A7 output pins are guaran-
■ 8-bit registered transceivers
■ Separate clock, clock enable and 3-STATE output
enable provided for each register
■ AMD Am2952/2953 functional equivalents
■ Both inverting and non-inverting options available
■ 24-Pin slimline package
teed to sink 24 mA while the B0–B7 output pins are
designed for 64 mA.
The 29F53 is an inverting option of the 29F52. Both trans-
ceivers are AMD Am2952/2953 functional equivalents.
Ordering Code:
Order Number Package Number
Package Description
29F52SC
M24B
N24C
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
29F52SPC
29F53SPC
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
29F52
29F53
IEEE/IEC
29F53
IEEE/IEC
29F52
© 1999 Fairchild Semiconductor Corporation
DS009606
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Connection Diagrams
Pin Assignment for DIP and SOIC
Pin Assignment for DIP
29F53
29F52
Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
3.5/1.083
A0–A7
A-Register Inputs/
70 µA/0.65 mA
−3 mA/24 mA (20 mA)
70 µA/0.65 mA
B-Register 3-STATE Outputs
B Register Inputs/
150/40 (33.3)
3.5/1.083
B0–B7
A-Register 3-STATE Outputs
Output Enable A-Register
600/106.6 (80)
1.0/1.0
−12 mA/64 mA (48 mA)
20 µA/−0.6 mA
OEA
CPA
CEA
A-Register Clock
1.0/1.0
1.0/1.0
20 µA/−0.6 mA
20 µA/−0.6 mA
A-Register Clock Enable
Output Enable B-Register
B-Register Clock
1.0/1.0
1.0/1.0
1.0/1.0
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
OEB
CPB
B-Register Clock Enable
CEB
Output Control
Register Function Table
(Applies to A or B Register)
Internal
Y-Output
29F52 29F53
Inputs
Internal
OE
Function
Function
Hold Data
Load Data
Q
X
L
D
X
L
CP
X
CE
H
Q
NC
L
H
L
L
Z
L
Z
H
L
Disable Outputs
Enable Outputs
N
L
H
H
H
N
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance
N = LOW-to-HIGH Transition
NC = No Change
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2
Block Diagrams
29F52
3
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Block Diagrams (continued)
29F53
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4
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
−1.2
Min
Min
I
I
I
I
I
I
I
I
= −18 mA (Non I/O Pins)
CD
OH
IN
10% V
10% V
10% V
5% V
2.5
2.4
2.0
2.7
2.7
= −1 mA (A )
n
CC
CC
CC
CC
CC
CC
CC
OH
OH
OH
OH
OH
OL
OL
Voltage
= −3 mA (A , B )
n n
V
= −15 mA (B )
n
= −1 mA (A )
n
5% V
= −3 mA (A , B )
n n
V
Output LOW
10% V
10% V
0.5
0.55
20
= 24 mA (A )
n
OL
V
Min
Max
Max
Voltage
= 64 mA (B )
n
I
Input HIGH Current
Input HIGH Current
Breakdown Test
µA
µA
V
= 2.7V (Non-I/O Pins)
IH
IN
I
BVI
100
1.0
V
= 7.0V (Non-I/O Pins)
IN
I
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
BVIT
mA
Max
V
= 5.5V (A , B )
n n
IN
I
−0.6
70
mA
µA
µA
mA
Max
Max
Max
Max
V
V
V
V
V
V
V
V
V
V
= 0.5V (Non-I/O Pins)
IL
IN
I
+ I
= 2.7V (A , B )
n n
IH
OZH
OUT
OUT
OUT
OUT
OUT
OUT
I
+ I
−650
−150
−225
250
500
190
190
190
= 0.5V (A , B )
n n
IL
OZL
I
−60
= 0V (A )
n
OS
−100
= 0V (B )
n
I
Output HIGH Leakage Current
Bus Drainage Test
µA
µA
Max
0.0V
Max
Max
Max
= V (A , B )
CC n n
CEX
I
= 5.25V (A , B )
n n
ZZ
I
Power Supply Current
Power Supply Current
Power Supply Current
130
mA
mA
mA
= HIGH
CCH
O
O
O
I
= LOW
CCL
I
= HIGH Z
CCZ
5
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AC Electrical Characteristics
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
CC
Symbol
Parameter
Units
C
C
L
L
Min
3.0
4.0
2.5
3.5
Typ
5.5
7.0
5.5
7.0
Max
7.5
9.0
7.5
9.5
Min
Max
Min
2.5
3.5
2.0
3.0
Max
t
Propagation Delay
8.5
10.0
8.5
PLH
ns
ns
ns
t
CPA or CPB to A or B
n
PHL
n
t
Output Enable Time
PZH
t
10.5
OEA or OEB to A or B
n
PZL
n
t
Output Disable Time
2.5
2.5
6.5
5.5
9.0
7.5
2.0
2.0
10.0
8.5
PHZ
t
OEA or OEB to A or B
n
PLZ
n
AC Operating Requirements
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
Symbol
Parameter
V
= +5.0V
V
= +5.0V
V = +5.0V
CC
Units
CC
CC
Min
4.0
4.0
2.0
2.0
1.0
4.0
Max
Min
Max
Min
4.5
4.5
2.5
2.5
1.5
4.5
Max
t (H)
Setup Time, HIGH or LOW
or B to CPA or CPB
S
ns
ns
ns
t (L)
A
n
S
n
t
t
(H)
(L)
Hold Time, HIGH or LOW
or B to CPA or CPB
H
H
A
n
n
t (H)
S
Setup Time, HIGH or LOW
t (L)
S
CEA or CEB to CPA or CPB
Hold Time, HIGH or LOW
t
t
(H)
(L)
2.0
2.0
2.5
2.5
H
H
ns
ns
CEA or CEB to CPA or CPB
Pulse Width, HIGH or LOW
CPA or CPB
t
t
(H)
(L)
3.0
3.0
3.5
3.5
W
W
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6
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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