10371QC [FAIRCHILD]
Low Power Triple 4-Input Multiplexer with Enable; 低功耗三4输入多路复用器与启用型号: | 10371QC |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | Low Power Triple 4-Input Multiplexer with Enable |
文件: | 总8页 (文件大小:89K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
October 1989
Revised August 2000
100371
Low Power Triple 4-Input Multiplexer with Enable
General Description
The 100371 contains three 4-input multiplexers which
Features
■ 35% power reduction of the 100171
share a common decoder (inputs S0 and S1). Output buffer
■ 2000V ESD protection
gates provide true and complement outputs. A HIGH on the
Enable input (E) forces all true outputs LOW (see Truth
Table). All inputs have 50 kΩ pull-down resistors.
■ Pin/function compatible with 100171
■ Voltage compensated operating range = −4.2V to −5.7V
■ Available to industrial grade temperature range
Ordering Code:
Order Number Package Number
Package Description
100371SC
100371PC
10371QC
10371QI
M24B
N24E
V28A
V28A
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
28-Pin PLCC
Pin Names
Description
Data Inputs
I0x–I3x
S0, S1
E
Select Inputs
Enable Input (Active LOW)
Data Outputs
Za–Zc
Za–Zc
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation
DS010148
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Truth Table
Inputs
S0
Outputs
Zn
E
S1
L
L
L
L
H
L
H
L
L
L
I0x
I1x
I2x
I3x
L
H
H
X
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature (TSTG
Maximum Junction Temperature (TJ)
EE Pin Potential to Ground Pin
)
−65°C to +150°C
+150°C
Case Temperature (TC)
Commercial
V
−7.0V to +0.5V
VEE to +0.5V
−50 mA
0°C to +85°C
−40°C to +85°C
−5.7V to −4.2V
Input Voltage (DC)
Industrial
Output current (DC Output HIGH)
ESD (Note 2)
Supply Voltage (VEE
)
≥2000V
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics (Note 3)
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C
Symbol
Parameter
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Min
Typ
−955
−1705
Max
−870
Units
mV
Conditions
Loading with
VOH
VOL
−1025
−1830
−1035
V
IN =VIH (Max)
or VIL (Min)
IN = VIH (Min)
−1620
mV
50Ω to −2.0V
Loading with
50Ω to −2.0V
VOHC
VOLC
VIH
mV
V
−1610
−870
mV
or VIL (Max)
−1165
−1830
0.50
mV
Guaranteed HIGH Signal
for All Inputs
VIL
Input LOW Voltage
−1475
mV
µA
µA
mA
Guaranteed LOW Signal
for All Inputs
IIL
Input LOW Current
Input HIGH Current
VIN = VIL (Min)
IIH
I0X–I3X
340
300
−39
VIN = VIH (Max)
S0, S1, E
IEE
Power Supply Current
−75
Inputs Open
Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
DIP AC Electrical Characteristics
V
EE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol Parameter
Propagation Delay
T
C = 0°C
T
C = +25°C
TC = +85°C
Units
ns
Conditions
Min
Max
Min
Max
Min
Max
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tTLH
tTHL
0.45
0.90
0.65
0.35
1.50
2.40
2.30
1.20
0.45
1.50
0.45
1.60
I0x–I3x to Output
Propagation Delay
S0, S1 to Output
Propagation Delay
E to Output
Figures 1, 2
(Note 4)
0.90
0.65
0.35
2.40
2.30
1.20
1.00
0.75
0.35
2.60
2.40
1.20
ns
ns
Transition Time
ns
Figures 1, 2
20% to 80%, 80% to 20%
Note 4: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
3
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Commercial Version (Continued)
SOIC and PLCC AC Electrical Characteristics
V
EE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol Parameter
Propagation Delay
T
C = 0°C
T
C = +25°C
TC = +85°C
Units
ns
Conditions
Min
Max
Min
Max
Min
Max
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tTLH
tTHL
tOSHL
0.45
0.90
0.65
0.35
1.30
2.20
2.10
1.10
0.45
1.30
0.45
1.40
I0x–I3x to Output
Propagation Delay
Figures 1, 2
(Note 5)
0.90
0.65
0.35
2.20
2.10
1.10
1.00
0.75
0.35
2.40
2.20
1.10
ns
S0, S1 to Output
Propagation Delay
ns
E to Output
Transition Time
ns
Figures 1, 2
20% to 80%, 80% to 20%
Maximum Skew Common Edge
Output-to-Output Variation
Data to Output Path
PLCC only
(Note 6)
400
490
490
430
400
490
490
430
400
490
490
430
ps
ps
ps
ps
tOSLH
tOST
tPS
Maximum Skew Common Edge
Output-to-Output Variation
Data to Output Path
PLCC only
(Note 6)
Maximum Skew Opposite Edge
Output-to-Output Variation
Data to Output Path
PLCC only
(Note 6)
Maximum Skew
PLCC only
(Note 6)
Pin (Signal) Transition Variation
Data to Output Path
Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite
directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design.
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4
Industrial Version
PLCC DC Electrical Characteristics (Note 7)
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C
T
C = −40°C
TC = 0°C to +85°C
Symbol
Parameter
Units
Conditions
Min
Max
−870
Min
Max
−870
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
−1085
−1830
−1095
−1025
−1830
−1035
mV
mV
mV
mV
mV
V
IN =VIH (Max)
or VIL(Min)
IN = VIH (Min)
or VIL(Max)
Loading with
50Ω to −2.0V
Loading with
50Ω to −2.0V
−1575
−1620
VOHC
VOLC
VIH
V
−1565
−870
−1610
−870
−1170
−1830
0.50
−1165
−1830
0.50
Guaranteed HIGH Signal
for All Inputs
VIL
Input LOW Voltage
−1480
−1475
mV
µA
µA
mA
Guaranteed LOW Signal
for All Inputs
IIL
Input LOW Current
Input HIGH Current
V
IN = VIL (Min)
IIH
I0X–I3X
340
300
−35
340
300
−39
V
IN = VIH (Max)
S0, S1, E
IEE
Power Supply Current
−75
−75
Inputs Open
Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
PLCC AC Electrical Characteristics
V
EE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol Parameter
Propagation Delay
T
C = −40°C
T
C = +25°C
TC = +85°C
Units
ns
Conditions
Min
Max
Min
Max
Min
Max
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tTLH
tTHL
0.40
1.30
0.45
1.30
0.45
1.40
I0x–I3x to Output
Propagation Delay
S0, S1 to Output
Propagation Delay
E to Output
Figures 1, 2
(Note 8)
0.70
0.65
0.20
2.20
2.10
1.60
0.90
0.65
0.35
2.20
2.10
1.10
1.00
0.75
0.35
2.40
2.20
1.10
ns
ns
Transition Time
ns
Figures 1, 2
20% to 80%, 80% to 20%
Note 8: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
5
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Test Circuitry
Notes:
VCC, VCCA = +2V, VEE = −2.5V
L1 and L2 = equal length 50Ω impedance lines
RT = 50Ω terminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50Ω to GND
C
L = Fixture and stray capacitance ≤ 3 pF
FIGURE 1. AC Test Circuit
Switching Waveforms
FIGURE 2. Propagation Delay and Transition Times
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6
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
Package Number N24E
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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