ES29DS640DT-90TGI_技术文档

E S I

Excel Semiconductor inc.

ES29LV160E

16Mbit(2M x 8/1M x 16)

CMOS 3.0 Volt-only, Boot Sector Flash Memory

• Minimum 100,000 program/erase cycles per sector

• 20 Year data retention at 125^oC

GENERAL FEATURES

• Single power supply operation

- 2.7V -3.6V for read, program and erase operations

SOFTWARE FEATURES

• Sector Structure

- 16Kbyte x 1, 8Kbyte x 2, 32Kbyte x 1 boot sectors

- 64Kbyte x 31 sectors

• Erase Suspend / Erase Resume

• Data# poll and toggle for Program/erase status

• CFI ( Common Flash Interface) supported

• Unlock Bypass program

• Autoselect mode

• Auto-sleep mode after t_ACC+ 30ns

• Top or Bottom boot block

- ES29LV160ET for Top boot block device

- ES29LV160EB for Bottom boot block device

• Package Options

- 48-pin TSOP

- 48-ball FBGA ( 6 x 8 mm )

- Pb-free packages

HARDWARE FEATURES

• Hardware reset input pin ( RESET#)

- Provides a hardware reset to device

- All Pb-free products are RoHS-Compliant

- Any internal device operation is terminated and the

device returns to read mode by the reset

• Low Vcc write inhibit

• Manufactured on 0.18um process technology

• Compatible with JEDEC standards

- Pinout and software compatible with single-power

supply flash standard

• Ready/Busy# output pin ( RY/BY#)

- Provides a program or erase operational status

about whether it is finished for read or still being

progressed

DEVICE PERFORMANCE

• Sector protection / unprotection ( RESET# , A9 )

- Hardware method of locking a sector to prevent

any program or erase operation within that sector

- Two methods are provided :

• Read access time

- 70ns / 90ns

- In-system method by RESET# pin

- A9 high-voltage method for PROM programmers

• Program and erase time

- Program time : 6us/byte, 8us/word ( typical )

- Sector erase time : 0.7sec/sector ( typical )

• Temporary Sector Unprotection ( RESET# )

- Allows temporary unprotection of previously

protected sectors to change data in-system

• Power consumption (typical values)

- 200nA in standby or automatic sleep mode

- 9mA active read current at 5 MHz

- 15mA active write current during program or erase

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Excel Semiconductor inc.

GENERAL PRODUCT DESCRIPTION

The ES29LV160 is completely compatible with the

JEDEC standard command set of single power sup-

ply Flash. Commands are written to the internal

command register using standard write timings of

microprocessor and data can be read out from the

cell array in the device with the same way as used in

other EPROM or flash devices.

The ES29LV160 is a 16 megabit, 3.0 volt-only flash

memory device, organized as 2M x 8 bits (Byte

mode) or 1M x 16 bits (Word mode) which is config-

urable by BYTE#. Four boot sectors and thirty one

main sectors are provided : 16Kbytes x 1, 8Kbytes

x 2, 32Kbytes x 1 and 64Kbytes x 31. The device is

manufactured with ESI’s proprietary, high perfor-

mance and highly reliable 0.18um CMOS flash

technology. The device can be programmed or

erased in-system with standard 3.0 Volt Vcc supply

( 2.7V-3.6V) and can also be programmed in stan-

dard EPROM programmers. The device offers min-

imum endurance of 100,000 program/erase cycles

and more than 10 years of data retention.

The ES29LV160 offers access time as fast as 70ns

or 90ns, allowing operation of high-speed micropro-

cessors without wait states. Three separate control

pins are provided to eliminate bus contention : chip

enable (CE#), write enable (WE#) and output

enable (OE#).

All program and erase operation are automatically

and internally performed and controlled by embed-

ded program/erase algorithms built in the device.

The device automatically generates and times the

necessary high-voltage pulses to be applied to the

cells, performs the verification, and counts the num-

ber of sequences. Some status bits (DQ7, DQ6 and

DQ5) read by data# polling or toggling between

consecutive read cycles provide to the users the

internal status of program/erase operation: whether

it is successfully done or still being progressed.

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PRODUCT SELECTOR GUIDE

Family Part Number

Voltage Range

ES29LV160E

2.7 ~ 3.6V

Speed Option

70

35

90

40

Max Access Time (ns)

CE# Access (ns)

OE# Access (ns)

FUNCTION BLOCK DIAGRAM

RY/BY#

Timer/

Counter

Vcc

Vss

Vcc Detector

DQ0-DQ15(A-1)

Analog Bias

Generator

Input/Output

Buffers

Write

State

Command

Register

WE

#

Machine

RESET#

Data Latch/

Sense Amps

Sector Switches

Y-Decoder

X-Decoder

Y-Decoder

Cell Array

A<0:19>

CE#

OE#

Chip Enable

Output Enable

Logic

BYTE#

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PIN DESCRIPTION

Description

A0-A19

20 Addresses

DQ0-DQ14

15 Data Inputs/Outputs

DQ15 (Data Input/Output, Word Mode)

A-1 (LSB Address Input, Byte Mode)

DQ15/A-1

CE#

OE#

Chip Enable

Output Enable

WE#

Write Enable

RESET#

BYTE#

RY/BY#

Hardware Reset Pin, Active Low

Selects 8-bit or 16-bit mode

Ready/Busy Output (N/A SO 044)

3.0 volt-only single power supply

Vcc

(see Product Selector Guide for speed options and voltage supply tolerances)

Vss

NC

Device Ground

Pin Not Connected Internally

LOGIC SYMBOL

20

16 or 8

A0 ~ A19

DQ0 ~ DQ15

(A-1)

CE#

OE#

WE#

RESET#

BYTE#

RY/BY#

(N/A SO 044)

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CONNECTION DIAGRAM

48

47

1

2

3

4

5

A15

A14

A13

A12

A11

A10

A9

A16

BYTE#

Vss

DQ15/A-1

DQ7

DQ14

DQ6

46

45

44

48-Pin Standard TSOP

6

7

8

43

42

41

DQ13

A8

9

A19

NC

WE#

RESET#

NC

40

39

38

37

36

35

34

DQ5

DQ12

DQ4

Vcc

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

Vss

ES29LV160

NC

RY/BY#

A18

A17

A7

33

32

31

30

A6

A5

A4

A3

A2

A1

29

28

27

26

25

CE#

A0

48-Ball FBGA (6 x 8 mm)

(Top View, Balls Facing Down)

A

B

C

D

E

F

G

H

DQ15/

A-1

6

5

A13

A9

A12

A8

BYTE#

DQ14

A14

A10

A16

Vss

A15

A11

DQ7

DQ6

DQ13

Vcc

WE#

A19

NC

DQ4

DQ3

RESET#

NC

DQ5

DQ2

DQ12

DQ10

4

3

RY/

BY#

NC

DQ11

A18

A6

A7

A3

A5

A1

DQ0

A0

A17

A4

DQ8

CE#

DQ9

OE#

DQ1

Vss

2

1

A2

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DEVICE BUS OPERATIONS

on the device address inputs produce valid data on

the device data outputs. The device stays at the read

mode until another operation is activated by writing

commands into the internal command register. Refer

to the AC read cycle timing diagrams for further

details ( Fig. 16 ).

Several device operational modes are provided in

the ES29LV160 device. Commands are used to ini-

tiate the device operations. They are latched and

stored into internal registers with the address and

data information needed to execute the device

operation.

The available device operational modes are listed

in Table 1 with the required inputs, controls, and the

resulting outputs. Each operational mode is

described in further detail in the following subsec-

tions.

Word/Byte Mode Configuration ( BYTE# )

The device data output can be configured by BYTE#

into one of two modes : word and byte modes. If the

BYTE# pin is set at logic ‘1’, the device is configured

in word mode, DQ0 - DQ15 are active and controlled

by CE# and OE#. If the BYTE# pin is set at logic ‘0’,

the device is configured in byte mode, and only data

I/O pins DQ0 - DQ7 are active and controlled by CE#

and OE#. The data I/O pins DQ8 - DQ14 are tri-

stated, and the DQ15 pin is used as an input for the

LSB (A-1) address.

Read

The internal state of the device is set for the read

mode and the device is ready for reading array data

upon device power-up, or after a hardware reset. To

read the stored data from the cell array of the

device, CE# and OE# pins should be driven to V

IL

Standby Mode

while WE# pin remains at V . CE# is the power

IH

control and selects the device. OE# is the output

control and gates array data to the output pins.

When the device is not selected or activated in a

system, it needs to stay at the standby mode, in

which current consumption is greatly reduced with

outputs in the high impedance state.

Word or byte mode of output data is determined by

the BYTE# pin. No additional command is needed

in this mode to obtain array data. Standard micro-

processor read cycles that assert valid addresses

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The device enters the CMOS standby mode when

CE# and RESET# pins are both held at Vcc 0.3V.

(Note that this is a more restricted voltage range

set-up cycle and the last cycle with the program data

and addresses. In this mode, two unlock cycles are

saved ( or bypassed ).

+

than V ) If CE# and RESET# are held at V , but

IH.

IH

Sector Addresses

not within Vcc+0.3V, the device will be still in the

standby mode, but the standby current will be

greater than the CMOS standby current (0.2uA typi-

cally). When the device is in the standby mode, only

The entire memory space of cell array is divided into

a many of small sectors: 16Kbytes x 1, 8Kbytes x 2,

32Kbytes x 1 and 64Kbytes x 31 main sectors. In

erase operation, a single sector, multiple sectors, or

the entire device (chip erase) can be selected for

erase. The address space that each sector occupies

is shown in detail in the Table 3-4.

standard access time (t ) is required for read

CE

access, before it is ready for read data. And even if

the device is deselected by CE# pin during erase or

programming operation, the device draws active cur-

rent until the operation is completely done. While the

device stays in the standby mode, the output is

placed in the high impedance state, independent of

the OE# input.

Autoselect Mode

Flash memories are intended for use in applications

where the local CPU alters memory contents. In

such applications, manufacturer and device identifi-

cation (ID) codes must be accessible while the

device resides in the target system ( the so called

“in-system program”). On the other hand, signature

codes have been typically accessed by raising A9

pin to a high voltage in PROM programmers. How-

ever, multiplexing high voltage onto address lines is

not the generally desired system design practice.

Therefore, in the ES29LV160 device an autoselect

command is provided to allow the system to access

the signature codes without any high voltage. The

conventional A9 high-voltage method used in the

PROM programers for signature codes are still sup-

ported in this device.

If the system writes the autoselect command

sequence, the device enters the Autoselect mode.

The system can then read some useful codes such

as manufacturer and device ID from the internal reg-

isters on DQ7 - DQ0. Standard read cycle timings

apply in this mode. In the Autoselect mode, the fol-

lowing three informations can be accessed through

either autoselect command method or A9 high-volt-

age autoselect method. Refer to the Table 2.

The device can enter the deep power-down mode

where current consumption is greatly reduced down

to less than 0.2uA typically by the following three

ways:

- CMOS standby ( CE#, RESET# = Vcc + 0.3V )

- During the device reset ( RESET# = Vss + 0.3V )

- In Autosleep Mode ( after t_ACC+ 30ns )

Refer to the CMOS DC characteristics Table11 for

further current specification.

Autosleep Mode

The device automatically enters a deep power-down

mode called the autosleep mode when addresses

remain stable for t

+30ns. In this mode, current

ACC

consumption is greatly reduced ( less than 0.2uA

typical ), regardless of CE#, WE# and OE# control

signals.

Writing Commands

To write a command or command sequences to ini-

tiate some operations such as program or erase, the

-

Manufacturer ID

Device ID

Sector protection verify

system must drive WE# and CE# to V , and OE# to

IL

V . For program operations, the BYTE# pin deter-

IH

mines whether the device accepts program data in

bytes or words. Refer to “BYTE# timings for Write

Operations” in the Fig. 19 for more information.

Hardware Device Reset ( RESET# )

The RESET# pin provides a hardware method of

resetting the device to read array data. When the

Unlock Bypass Mode

RESET# pin is driven low for at least a period of t

,

RP

To reduce more the programming time, an unlock-

bypass mode is provided. Once the device enters

this mode, only two write cycles are required to ini-

tiate the programming operation instead of four

cycles in the normal program command sequences

which are composed of two unlock cycles, program

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Excel Semiconductor inc.

the device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the

RESET# pulse The device also resets the internal

state machine to reading array data. The operation

that was interrupted should be reinitiated once after

the device is ready to accept another command

sequence, to ensure data integrity.

Sector protection can be implemented via two

methods.

-

In-system protection

A9 High-voltage protection

To check whether the sector protection was suc-

cessfully executed or not, another operation called

“protect verification” needs to be performed after

the protection operation on a sector. All protection

and protect verifications provided in the device are

summarized in detail at the Table 1.

CMOS Standby during Device Reset

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at Vss

device draws the greatly reduced CMOS standby

current ( I ). If RESET# is held at V but not

+ 0.3V, the

In-System Protection

CC4

IL

within Vss+0.3V, the standby current will be greater.

“In-system protection”, the primary method,

requires V (11.5V~12.5V) on the RESET# with

ID

RY/BY# and Terminating Operations

A6=0, A1=1, and A0=0. This method can be imple-

mented either in-system or via programming equip-

ment. This method uses standard microprocessor

bus cycle timing. Refer to Fig. 26 for timing diagram

and Fig. 2 for the protection algorithm.

If RESET# is asserted during a program or erase

operation, the RY/BY# pin remains a “0” (busy) until

the internal reset operation is completed, which

requires a time of t

(during Embedded Algo-

READY

rithms). The system can thus monitor RY/BY# to

determine whether the reset operation is completed.

If RESET# is asserted when a program or erase

operation is not executing (RY/BY# pin is “1”), the

A9 High-Voltage Protection

“High-voltage protection”, the alternate method

intended only for programming equipment, must

reset operation is completed within a time of t

force V (11.5~12.5V) on address pin A9 and con-

READY

ID

(not during Embedded Algorithms). The system can

trol pin OE# with A6=0, A1=1 and A0=0. Refer to

Fig. 28 for timing diagram and Fig. 4 for the protec-

tion algorithm.

read data after the RESET# pin returns to V , which

IH

requires a time of t

RH.

SECTOR UNPROTECTION

RESET# tied to the System Reset

The previously protected sectors must be unpro-

tected before modifying any data in the sectors.

The sector unprotection algorithm unprotects all

sectors in parallel. All unprotected sectors must first

be protected prior to the first sector unprotection

write cycle to avoid any over-erase due to the intrin-

sic erase characteristics of the protection cell. After

the unprotection operation, all previously protected

sectors will need to be individually re-protected.

Standard microprocessor bus cycle timings are

used in the unprotection and unprotect verification

operations. Three unprotect methods are provided

in the ES29LV160 device. All unprotection and

unprotect verification cycles are summarized in

detail at the Table 1.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the

Flash memory, enabling the system to read the boot-

up firmware from the Flash memory.Refer to the AC

Characteristics tables for RESET# parameters and

to Fig. 17 for the timing diagram.

SECTOR PROTECTION

The ES29LV160 features hardware sector protec-

tion. In the device, sector protection is performed on

the sector previously defined in the Table 3-4. Once

after a sector is protected, any program or erase

operation is not allowed in the protected sector. The

previously protected sectors must be unprotected by

one of the unprotect methods provided here before

changing data in those sectors.

-

In-system unprotection

A9 High-voltage unprotection

Temporary sector unprotection

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The command register and all internal program/

erase circuits are disabled, and the device resets to

the read mode. Subsequent writes are ignored until

In-System Unprotection

“In-system unprotection”, the primary method,

Vcc is greater than V

. The system must provide

requires V (11.5V~12.5V) on the RESET# with

LKO

ID

proper signals to the control pins to prevent unin-

A6=1, A1=1, and A0=0. This method can be imple-

mented either in-system or via programming equip-

ment. This method uses standard microprocessor

bus cycle timing. Refer to Fig. 26 for timing diagram

and Fig. 3 for the unprotection algorithm.

tentional writes when Vcc is greater than V

.

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 5ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

A9 High-Voltage Unprotection

“High-voltage unprotection”, the alternate method

intended only for programming equipment, must

Logical inhibit

force V (11.5~12.5V) on address pin A9 and con-

Write cycles are inhibited by holding any one of

ID

trol pin OE# with A6=1, A1=1 and A0=0. Refer to

Fig. 29 for timing diagram and Fig. 5 for the unpro-

tection algorithm.

OE#=V , CE#=V or WE#=V . To initiate a write

IL

IH

cycle, CE# and WE# must be a logical zero while

OE# is a logical one.

Temporary Sector Unprotect

Power-up Write Inhibit

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system.

The Sector Unprotect mode is activated by setting

If WE#=CE#=V and OE#=V during power up,

IL

IH

the device does not accept any commands on the

rising edge of WE#. The internal state machine is

automatically reset to the read mode on power-up.

the RESET# pin to V (11.5V-12.5V). During this

ID

mode, formerly protected sectors can be pro-

grammed or erased by selecting the sector

addresses. Once V is removed from the RESET#

ID

START

pin, all the previously protected sectors are pro-

tected again. Fig. 1 shows the algorithm, and Fig. 25

shows the timing diagrams for this feature.

RESET# = V_ID

(Note 1)

HARDWARE DATA PROTECTION

The ES29LV160 device provides some protection

measures against accidental erasure or program-

ming caused by spurious system level signals that

may exist during power transition. During power-up,

all internal registers and latches in the device are

cleared and the device automatically resets to the

read mode. In addition, with its internal state

machine built-in the device, any alteration of the

memory contents or any initiation of new operation-

can only occur after successful completion of spe-

cific command sequences. And several features are

incorporated to prevent inadvertent write cycles

resulting from Vcc power-up and power-down transi-

tion or system noise.

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors are unprotected .

2. All previously protected sectors are protected once again.

Low Vcc Write inhibit

When Vcc is less than V

, the device does not

LKO

accept any write cycles. This protects data during

Vcc power-up and power-down.

Figure 1. Temporary Sector Unprotect

Operation

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Table 1. ES29LV160 Device Bus Operations

DQ0

~

DQ7

DQ8~DQ15

Operation

CE# OE# WE# RESET# Addresses

BYTE#

= V_IH

BYTE#

= V_IL

(Note 1)

Read

Write

L

H

L

A

D

L

H

DQ8~DQ14 = High-Z,

DQ15 = A-1

IN

OUT

A

H

(Note 3)

High-Z

(Note 3)

High-Z

IN

Vcc+

0.3V

Standby

X

Vcc+

0.3V

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z

X

Sector Protect

(Note 2)

SA,A6=L,

A1=H,A0=L

V

L

X

L

H

X

L

X

L

(Note 3)

X

ID

Sector Unprotect

(Note 2)

SA,A6=H,

A1=H,A0=L

In-system

V

ID

Temporary Sector

Unprotect

A

(Note 3)

High-Z

IN

SA,A9=V

A6=L,

,

ID

Sector protect

V

H

ID

A9 High-Volt-

age Method

A1=H,A0=L

(Note 3)

High-Z

SA,A9=V

A6=H,

,

ID

Sector unprotect

V

H

L

A1=H,A0=L

Legend: L=Logic Low=V , H=Logic High=V , V =11.5-12.5V, X=Don’t Care, SA=Sector Address, A =Address In, D =Data In,

IL

IH ID

IN

D

=Data Out

OUT

Notes:

1. Addresses are A19:A0 in word mode (BYTE#=V ) , A19:A-1 in byte mode (BYTE#=V ).

IH

IL

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Pro-

tection and Unprotection” section.

3. D or D

as required by command sequence, data polling, or sector protection algorithm.

IN

OUT

Table 2. Autoselect Codes (A9 High-Voltage Method)

A19 A11

A8

A9 to

A7

A5

to

A2

DQ8~DQ15

Description CE# OE# WE# to

to

A6

A1 A0

DQ7~DQ0

BYTE# BYTE#

A12 A10

= V_IH

= V_IL

L

H

V_ID

X

L

X

L

X

ManufactureID:ESI

L

X

4Ah

Device ID:

ES29LV160

H

22h

X

C4h(T),49h(B)

Sector Protection

Verification

01h(protected)

00h(unprotected)

V_ID

L

H

SA

X

L

X

H

L

Legend: T= Top Boot Block, B = Bottom Boot Block, L=Logic Low=V , H=Logic High=V , SA=Sector Address, X = Don’t care

IL

IH

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Table 3. Top Boot Sector Addresses (ES29LV160ET)

Sector address

A19~A12

Sector Size

(Kbytes/Kwords)

(X8)

Address Range

(X16)

Address Range

Sector

Remark

SA0

SA1

00000XXX

00001XXX

00010XXX

00011XXX

00100XXX

00101XXX

00110XXX

00111XXX

01000XXX

01001XXX

01010XXX

01011XXX

01100XXX

01101XXX

01110XXX

01111XXX

10000XXX

10001XXX

10010XXX

10011XXX

10100XXX

10101XXX

10110XXX

10111XXX

11000XXX

11001XXX

11010XXX

11011XXX

11100XXX

11101XXX

11110XXX

111110XX

11111100

64/32

32/16

8/4

000000h~00FFFFh

010000h~01FFFFh

020000h~02FFFFh

030000h~03FFFFh

040000h~04FFFFh

050000h~05FFFFh

060000h~06FFFFh

070000h~07FFFFh

080000h~08FFFFh

090000h~09FFFFh

0A0000h~0AFFFFh

0B0000h~0BFFFFh

0C0000h~0CFFFFh

0D0000h~0DFFFFh

0E0000h~0EFFFFh

0F0000h~0FFFFFh

100000h~10FFFFh

110000h~11FFFFh

120000h~12FFFFh

130000h~13FFFFh

140000h~14FFFFh

150000h~15FFFFh

160000h~16FFFFh

170000h~17FFFFh

180000h~18FFFFh

190000h~19FFFFh

1A0000h~1AFFFFh

1B0000h~1BFFFFh

1C0000h~1CFFFFh

1D0000h~1DFFFFh

1E0000h~1EFFFFh

1F0000h~1F7FFFh

1F8000h~1F9FFFh

1FA000h~1FBFFFh

1FC000h~1FFFFFh

00000h~07FFFh

08000h~0FFFFh

10000h~17FFFh

18000h~1FFFFh

20000h~27FFFh

28000h~2FFFFh

30000h~37FFFh

38000h~3FFFFh

40000h~47FFFh

48000h~4FFFFh

50000h~57FFFh

58000h~5FFFFh

60000h~67FFFh

68000h~6FFFFh

70000h~77FFFh

78000h~7FFFFh

80000h~87FFFh

88000h~8FFFFh

90000h~97FFFh

98000h~9FFFFh

A0000h~A7FFFh

A8000h~AFFFFh

B0000h~B7FFFh

B8000h~BFFFFh

C0000h~C7FFFh

C8000h~CFFFFh

D0000h~D7FFFh

D8000h~DFFFFh

E0000h~E7FFFh

E8000h~EFFFFh

F0000h~F7FFFh

F8000h~FBFFFh

FC000h~FCFFFh

FD000h~FDFFFh

FE000h~FFFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

Main Sector

Boot Sector

11111101

8/4

1111111X

16/8

Note:

The addresses range is A19:A-1 in byte mode (BYTE#=V ) or A19:A0 in word mode (BYTE#=V ).

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Table 4. Bottom Boot Sector Addresses (ES29LV160EB)

Sector address

A19~A12

Sector Size

(Kbytes/Kwords)

(X8)

Address Range

(X16)

Address Range

Sector

Remark

SA0

SA1

0000000X

00000010

00000011

000001XX

00001XXX

00010XXX

00011XXX

00100XXX

00101XXX

00110XXX

00111XXX

01000XXX

01001XXX

01010XXX

01011XXX

01100XXX

01101XXX

01110XXX

01111XXX

10000XXX

10001XXX

10010XXX

10011XXX

10100XXX

10101XXX

10110XXX

10111XXX

11000XXX

11001XXX

11010XXX

11011XXX

11100XXX

11101XXX

11110XXX

11111XXX

16/8

8/4

000000h~003FFFh

004000h~005FFFh

006000h~007FFFh

008000h~00FFFFh

010000h~01FFFFh

020000h~02FFFFh

030000h~03FFFFh

040000h~04FFFFh

050000h~05FFFFh

060000h~06FFFFh

070000h~07FFFFh

080000h~08FFFFh

090000h~09FFFFh

0A0000h~0AFFFFh

0B0000h~0BFFFFh

0C0000h~0CFFFFh

0D0000h~0DFFFFh

0E0000h~0EFFFFh

0F0000h~0FFFFFh

100000h~10FFFFh

110000h~11FFFFh

120000h~12FFFFh

130000h~13FFFFh

140000h~14FFFFh

150000h~15FFFFh

160000h~16FFFFh

170000h~17FFFFh

180000h~18FFFFh

190000h~19FFFFh

1A0000h~1AFFFFh

1B0000h~1BFFFFh

1C0000h~1CFFFFh

1D0000h~1DFFFFh

1E0000h~1EFFFFh

1F0000h~1FFFFFh

00000h~01FFFh

02000h~02FFFh

03000h~03FFFh

04000h~07FFFh

08000h~0FFFFh

10000h~17FFFh

18000h~1FFFFh

20000h~27FFFh

28000h~2FFFFh

30000h~37FFFh

38000h~3FFFFh

40000h~47FFFh

48000h~4FFFFh

50000h~57FFFh

58000h~5FFFFh

60000h~67FFFh

68000h~6FFFFh

70000h~77FFFh

78000h~7FFFFh

80000h~87FFFh

88000h~8FFFFh

90000h~97FFFh

98000h~9FFFFh

A0000h~A7FFFh

A8000h~AFFFFh

B0000h~B7FFFh

B8000h~BFFFFh

C0000h~C7FFFh

C8000h~CFFFFh

D0000h~D7FFFh

D8000h~DFFFFh

E0000h~E7FFFh

E8000h~EFFFFh

F0000h~F7FFFh

F8000h~FFFFFh

Boot Sector

SA2

8/4

SA3

32/16

64/32

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

Main Sector

Note:

The addresses range is A19:A-1 in byte mode (BYTE#=V ) or A19:A0 in word mode (BYTE#=V ).

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In-System Protection / Unprotection Method

START

Protect all sectors:

The indicated por-

tion of the sector

protect algorithm

must be performed

for all unprotected

sectors prior to

issuing the first

sector unprotect

address

COUNT = 1

RESET# = V

COUNT = 1

RESET# = V

ID

Wait 1us

No

Temporary Sector

Unprotect Mode

First Write

Temporary Sector

Unprotect Mode

Cycle = 60h?

Yes

Set up sector

address

No

All sectors

protected ?

Sector Protect:

Write 60h to sec-

tor address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unpro-

tect:

Write 60h to sec-

tor address with

A6 = 1, A1 = 1,

Wait 150us

Verify Sector

Protect:

Write 40h to sec-

tor address with

A6 = 0, A1 = 1,

A0 = 0

Wait 15ms

Increment

COUNT

Reset

COUNT = 1

Verify Sector

Unprotect:

Write 40h to sec-

tor address with

A6 = 1, A1 = 1,

A0 = 0

Set up next

sector address

Read from sec-

tor address with

A6 = 0, A1 = 1,

A0 = 0

Increment

COUNT

No

Read from sec-

tor address with

A6 = 1, A1 = 1,

A0 = 0

No

COUNT=25?

Data = 01h?

Yes

No

Yes

No

Yes

COUNT

=1000?

Data = 00h?

Yes

Protectanother

sector?

Device failed

Yes

No

Remove V

from RESET#

ID

Last sector

verified?

Device failed

Yes

Write reset

command

Remove V from

ID

RESET#

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 3. In-System Sector

Unprotect Algorithm

Figure 2. In-System Sector

Protect Algorithm

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A9 High-Voltage Method

Start

Note: All sectors must be

previously protected.

Start

COUNT = 1

SET A9=OE#=V

ID

SET A9=OE#=V

ID

,

CE#, A0=V

Set Sector Address

A<19 :12>

IL

RESET#,

A6, A1=V

CE#, A6, A0=V

IL

IH

RESET#, A1=V

IH

SET WE# = V

Wait 15ms

IL

SET WE# = V

Wait 150 us

IL

SET WE# = V

IH

SET WE# = V

IH

Increase COUNT

CE#,OE#, A0=V

IL

RESET#, A6, A1=V

IH

CE#,OE#,A6,A0=V

IL

RESET#, A1 = V

IH

Set Sector AddressA<19 :12>

Read Data

No

COUNT= 25?

Data = 01h?

Yes

No

COUNT=1000?

Data = 00h?

Yes

Increase Sector

Address

Yes

Device failed

Yes

Protect Another

Sector ?

Device failed

No

The Last Sector

Address ?

No

Remove V from

ID

A9 and Write

Yes

Reset Command

Remove V from A9 and

ID

Write Reset Command

Sector Protection

Complete

Sector Unprotection

Complete

Figure 4. Sector Protection Algorithm

(A9 High-Voltage Method)

Figure 5. Sector Un-Protection Algorithm

(A9 High-Voltage Method)

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This device enters the CFI Query mode when the

system writes the CFI query command, 98h, to

address 55h in word mode (or address AAh in byte

mode), any time the device is ready to read array

data. The system can read CFI information at the

addresses given in Tables 5-8. To terminate reading

CFI data, the system must write the reset com-

mand.The CFI query command can be written to the

system when the device is in the autoselect mode

or the erase-suspend-read mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 5-8.

When the reset command is written, the device

returns respectively to the read mode or erase-sus-

pend-read mode.

Common Flash Memory

Interface (CFI)

CFI is supported in the ES29LV160 device. The

Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their exist-

ing interfaces for long-term compatibility.

Table 5. CFI Query Identification String

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set(00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

Table 6. System Interface String

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data

Description

Vcc Min. (write/erase)

D7-D4: volt, D3-D0: 100 millivolt

1Bh

1Ch

36h

38h

0027h

0036h

Vcc Max. (write/erase)

D7-D4: volt, D3-D0: 100 millivolt

1Dh

1Eh

1Fh

3Ah

3Ch

3Eh

0000h

0004h

Vpp Min. voltage (00h = no Vpp pin present)

Vpp Max. voltage (00h = no Vpp pin present)

Typical timeout per single byte/word write 2^Nus

Typical timeout for Min. size buffer write 2^Nus (00h = not supported)

Typical timeout per individual block erase 2^Nms

20h

21h

22h

23h

24h

25h

26h

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

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Table 7. Device Geometry Definition

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data

Description

Device Size = 2^Nbyte

27h

4Eh

0015h

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description

02 = x8, x16 Asynchronous

Max. number of bytes multi-byte write = 2^N

(00h = not supported)

2Ah

2Bh

54h

56h

0000h

2Ch

58h

0004h

Number of Erase Block Regions within device

2Dh

2Eh

5Ah

5Ch

0000h

Erase Block Region 1 Information

Number of identical size erase block = 0000h+1 = 1

2Fh

30h

5Eh

60h

0040h

0000h

Erase Block Region 1 Information

Block size in Region 1 = 0040h * 256 byte = 16 Kbyte

31h

32h

62h

64h

0001h

0000h

Erase Block Region 2 Information

Number of identical size erase block = 0001h+1 =2

33h

34h

66h

68h

0020h

0000h

Erase Block Region 2 Information

Block size in Region 2 = 0020h * 256 byte = 8 Kbyte

35h

36h

6Ah

6Ch

0000h

Erase Block Region 3 Information

Number of identical size erase block = 0000h+1 =1

37h

38h

6Eh

70h

0080h

0000h

Erase Block Region 3 Information

Block size in Region 3 = 0080h * 256 byte = 32 Kbyte

39h

3Ah

72h

74h

001Eh

0000h

Erase Block Region 4 Information

Number of identical size erase block = 001Eh+1 =31

3Bh

3Ch

76h

78h

0000h

0001h

Erase Block Region 4 Information

Block size in Region 4 = 0100h * 256 byte = 64 Kbyte

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Table 8. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0030h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not required

Silicon Revision Number (Bits 7-2)

45h

8Ah

0000h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

8Ch

8Eh

90h

92h

94h

96h

98h

0002h

0001h

0004h

0000h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

04 = In-System Method and A9 High-Voltage Method

Simultaneous Operation

00 = Not Supported

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

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COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates

device operations. Table 9 defines the valid register

command sequences. Note that writing incorrect

address and data values or writing them in the

improper sequence may place the device in an

unknown state. A reset command is required to

return the device to normal operation.

the Device Bus Operations section for more informa-

tion.The Read-Only Operations table provides the

read parameters, and Fig. 16 shows the timing dia-

gram

RESET COMMAND

Writing the reset command resets the device to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched

on the rising edge of WE# or CE#, whichever hap-

pens first. Refer to the AC Characteristics section for

timing diagrams.

The reset command may be written between the

sequence cycles in an erase command sequence

before erasing begins. This resets the device to

which the system was writing to the read mode.

Once erasure begins, however, the device ignores

reset commands until the operation is complete.

READING ARRAY DATA

The device is automatically set to reading array data

after device power-up. No commands are required

to retrieve data. The device is ready to read array

data after completing an Embedded Program or

Embedded Erase algorithm.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device

to which the system was writing to the read mode. If

the program command sequence is written to a sec-

tor that is in the Erase Suspend mode, writing the

reset command returns the device to the erase-sus-

pend-read mode. Once programming begins, how-

ever, the device ignores reset commands until the

operation is complete.

After the device accepts an Erase Suspend com-

mand, the device enters the erase-suspend-read

mode, after which the system can read data from

any non-erase-suspended sector. After completing a

programming operation in the Erase Suspend mode,

the system may once again read array data with the

same exception. See the Erase Suspend/Erase

Resume Commands section for more information.

The reset command may be written between the

sequence cycles in an autoselect command

sequence. Once in the autoselect mode, the reset

command must be written to return to the read

mode. If the device entered the autoselect mode

while in the Erase Suspend mode, writing the reset

command returns the device to the erase-suspend-

read mode.

The system must issue the reset command to return

the device to the read (or erase-suspend-read)

mode if DQ5 goes high during an active program or

erase operation, or if the device is in the autoselect

mode. See the next section, Reset Command, for

more information.

If DQ5 goes high during a program or erase opera-

tion, writing the reset command returns the device to

the read mode (or erase-suspend-read mode if the

device was in Erase-Suspend).

See also Requirements for Reading Array Data in

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Command Definitions

Table 9. ES29LV160 Command Definitions

Bus Cycles (Notes 2~5)

Fourth

Command

Sequence

(Note 1)

First

Addr

RA

Second

Addr

Third

Addr

Fifth

Addr

Sixth

Data

RD

F0

Data

Addr

Data

Addr

Data

Read (Note 6)

Reset (Note 7)

1

XXX

555

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

2AA

555

2AA

555

2AA

555

PA

555

AAA

555

AAA

555

AAA

555

AAA

555

AAA

555

AAA

Manufacturer ID

Device ID (Top)

Device ID (Bottom)

4

3

AA

55

90

A0

20

X00

4A

AAA

555

X01

C4

AAA

555

X02

X01

49

AAA

555

X02

(SA)X02

(SA)X04

Sector Protect Verify

(Note 9)

00/01

PD

AAA

555

Program

PA

AAA

555

Unlock Bypass

AAA

XXX

555

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

Byte

Word

Byte

555

AAA

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

6

AA

55

80

AA

55

10

30

AAA

555

AAA

Sector Erase

SA

AAA

XXX

55

AAA

Erase Suspend (Note 12)

Erase Resume (Note 13)

1

B0

30

Word

Byte

CFI Query (Note 14)

1

98

AA

Legend:

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A19-A12 uniquely select any sector.

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

Notes:

9. The data is 00h for an unprotected sector and 01h for a

protected sector.

10. The Unlock Bypass command is required prior to the Unlock-

Bypass Program command.

11. The Unlock Bypass Reset command is required to return

to the read mode when the device is in the unlock bypass

mode.

12. The system may read and program in non-erasing sectors,

or enter the autoselect mode, when in the Erase Suspend

mode. The Erase Suspend command is valid only during

a sector erase operation.

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

4. Data bits DQ15-DQ8 are don’t care in command sequences,

except for RD and PD

5. Unless otherwise noted, address bits A19-A11 are don’t cares.

6. No unlock or command cycles required when device is in

read mode.

7. The Reset command is required to return to the read mode

(or to the erase-suspend-read mode if previously in Erase

Suspend) when a device is in the autoselect mode, or if DQ5

goes high (while the device is providing status information).

8. The fourth cycle of the autoselect command sequence

is a read cycle. Data bits DQ15-DQ8 are don’t care. See the

Autoselect Command Sequence section for more information.

13. The Erase Resume command is valid only during the Erase

Suspend mode.

14. Command is valid when device is ready to read array data

or when device is in autoselect mode.

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AUTOSELECT COMMAND

BYTE / WORD PROGRAM

The autoselect command sequence allows the host

system to access the manufacturer and device

codes, and determine whether or not a sector is

protected, including information about factory-

locked or customer lockable version.

The system may program the device by word or

byte, depending on the state of the BYTE# pin.

Programming is a four-bus-cycle operation. The

program command sequence is initiated by writing

two unlock write cycles, followed by the program

set-up command. The program address and data

are written next, which in turn initiate the Embedded

Program algorithm. The system is not required to

provide further controls or timings. The device auto-

matically provides internally generated program

pulses and verifies the programmed cell margin.

Table 9 shows the address and data requirements

for the byte program command sequence. Note that

the autoselect and CFI modes are unavailable

while a programming operation is in progress.

Identifier Code

Manufacturer ID

Device ID

Address

00h

Data

4Ah

01h

C4h(T),

49h(B)

Sector Protect Verify

(SA)02h

00 / 01

Table 9 shows the address and data requirements.

This method is an alternative to “A9 high-voltage

method” shown in Table 2, which is intended for

PROM programmers and requires V on address

ID

pin A9. The autoselect command sequence may be

written to an address within sector that is either in

the read mode or erase-suspend-read mode. The

auto-select command may not be written while the

device is actively programming or erasing. The

autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the autoselect command.

The device then enters the autoselect mode. The

system may read at any address any number of

times without initiating another autoselect com-

mand sequence.

START

Write Program Com-

mand Sequence

Embedded

Program

algorithm in

progress

Data Poll

from System

Once after the device enters the auto-select mode,

the manufacture ID code ( 4Ah ) can be accessed

by one of two ways. Just one read cycle ( with A6,

A1 and A0 = 0 ) can be used. Or four consecutive

read cycles ( with A6 = 1 and A1, A0 = 0 ) for con-

tinuation codes (7Fh) and then another last cycle

for the code (4Ah) (with A6, A1 and A0 = 0) can be

used for reading the manufacturer code.

No

Verify Data

?

Yes

No

Last Address?

Yes

Increment Address

- 4Ah (one-cycle read)

- 7Fh 7Fh 7Fh 7Fh 4Ah (Five-cycle read)

Programming

Completed

The system must write the reset command to return

to the read mode (or erase-suspend-read mode if

the device was previously in Erase Suspend).

Note: See Table 9 for program command sequence

Figure 6. Program Operation

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During the unlock-bypass mode, only the unlock-

bypass program and unlock-bypass reset com-

mands are valid. To exit the unlock-bypass mode,

the system must issue the two-cycle unlock-bypass

reset command sequence. The first cycle must con-

tain the data 90h. The second cycle need to only

contain the data 00h. The device then returns to the

read mode.

Program Status Bits : DQ7, DQ6 or RY/BY#

When the Embedded Program algorithm is com-

plete, the device then returns to the read mode and

addresses are no longer latched. The system can

determine the status of the program operation by

using DQ7, DQ6, or RY/BY#. Refer to the Write

Operation Status section Table 10 for information on

these status bits.

- Unlock Bypass Enter Command

- Unlock Bypass Reset Command

- Unlock Bypass Program Command

Any Commands Ignored during Program-

ming Operation

CHIP ERASE COMMAND

Any commands written to the device during the

Embedded Program algorithm are ignored. Note that

a hardware reset can immediately terminates the

program operation. The program command

sequence should be reinitiated once the device has

returned to the read mode, to ensure data integrity.

To erase the entire memory, a chip erase command

is used. This command is a six bus cycle operation.

The chip erase command sequence is initiated by

writing two unlock cycles, followed by a set-up com-

mand. Two additional unlock write cycles are then

followed by the chip erase command, which in turn

invokes the Embedded Erase algorithm. The chip

erase command erases the entire memory includ-

ing all other sectors except the protected sectors,

but the internal erase operation is performed on a

single sector base.

Programming from “0” back to “1”

Programming is allowed in any sequence and

across sector boundaries. But a bit cannot be pro-

grammed from “0” back to a ”1”. Attempting to do so

may cause the device to set DQ5 = 1, or cause the

DQ7 and DQ6 status bits to indicate the operation

was successful. However, a succeeding read will

show that the data is still “0”. Only erase operations

can convert a “0” to a “1”

Embedded Erase Algorithm

The device does not require the system to prepro-

gram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the

entire memory for an all zero data pattern prior to

electrical erase. The system is not required to pro-

vide any controls or timings during these opera-

tions. Table 9 shows the address and data

requirements for the chip erase command

sequence. Note that the autoselect, and CFI modes

are unavailable while an erase operation is in

progress

Unlock Bypass

In the ES29LV160 device, an unlock bypass pro-

gram mode is provided for faster programming oper-

ation. In this mode, two cycles of program command

sequences can be saved. To enter this mode, an

unlock bypass enter command should be first written

to the system. The unlock bypass enter command

sequence is initiated by first writing two unlock

cycles. This is followed by a third write cycle contain-

ing the unlock bypass command, 20h. The device

then enters the unlock-bypass program mode. A

two-cycle unlock bypass program command

sequence is all that is required to program in this

mode. The first cycle in this sequence contains the

unlock bypass program set-up command, A0h; the

second cycle contains the program address and

data. Additional data is programmed in the same

manner. This mode dispenses with the initial two

unlock cycles required in the standard program com-

mand sequence, resulting in faster total program-

ming time. Table 9 shows the requirements for the

command sequence.

Erase Status Bits : DQ7, DQ6, DQ2, or RY/

BY#

When the Embedded Erase algorithm is complete,

the device returns to the read mode and addresses

are no longer latched. The system can determine

the status of the erase operation by using DQ7,

DQ6, DQ2, or RY/BY#. Refer to the Write Opera-

tion Status section Table 10 for information on these

status bits.

Commands Ignored during Erase Operation

Any command written during the chip erase opera-

tion are ignored. However, note that a hardware

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reset immediately terminates the erase operation.If

that occurs, the chip erase command sequence

should be reinitiated once the device has returned to

reading array data. to ensure data integrity. Fig. 7

illustrates the algorithm for the erase operation.

Refer to the Erase and Program Operations tables in

the AC Characteristics section for parameters, and

Fig. 21 section for timing diagrams.

to the read mode. The system must rewrite the

command sequence and any additional addresses

and commands.

Status Bits : DQ7,DQ6,DQ2, or RY/BY#

When the Sector Erase Embedded Erase algorithm

is complete, the device returns to reading array

data and addresses are no longer latched. Note

that while the Embedded Erase operation is in

progress, the system can read data from the non-

erasing sector. The system can determine the sta-

tus of the erase operation by reading

DQ7,DQ6,DQ2, or RY/BY# in the erasing sector.

Refer to the Write Operation Status section Table

10 for information on these status bits.

SECTOR ERASE COMMAND

By using a sector erase command, a single sector or

multiple sectors can be erased. The sector erase

command is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 9 shows the

address and data requirements for the sector erase

command sequence. Note that the autoselect, and

CFI modes are unavailable while an erase operation

is in progress.

Valid Command during Sector Erase

Once the sector erase operation has begun, only

the Erase Suspend command is valid. All other

commands are ignored. However, note that a hard-

ware reset immediately terminates the erase oper-

ation. If that occurs, the sector erase command

Embedded Sector Erase Algorithm

The device does not require the system to prepro-

gram prior to erase. The Embedded Erase algorithm

automatically programs and verifies the entire mem-

ory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings these operations.

START

Write Erase

Command Sequence

(Notes 1,2)

Sector Erase Time-out Window and DQ3

Data Poll to

Erasing Bank

from System

Embedded

Erase

algorithm in

progress

After the command sequence is written, a sector

erase time-out of 50us occurs. During the time-out

period, additional sector addresses and sector erase

commands may be written. Loading the sector erase

buffer may be done in any sequence, and the num-

ber of sectors may be from one sector to all sectors.

The time between these additional cycles must be

less than 50 us, otherwise the last address and com-

mand may not be accepted, and erasure may begin.

It is recommended that processor interrupts be dis-

abled during this time to ensure all commands are

accepted. The interrupts can be re-enabled after the

last Sector Erase command is written. The system

can monitor DQ3 to determine if the sector erase

timer has timed out (See the section on DQ3:Sector

Erase Timer.). The time-out begins from the rising

edge of the final WE# pulse in the command

sequence.

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 9 for erase command sequence

2. See the section on DQ3 for information on the sector erase timer

Figure 7. Erase Operation

Any command other than Sector Erase or Erase Sus-

pend during the time-out period resets the device

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sequence should be reinitiated once the device has

returned to reading array data, to ensure data integ-

rity.

After an erase-suspended program operation is

complete, the device returns to the erase-suspend-

read mode. The system can determine the status for

the program operation using the DQ7 or DQ6 status

bits, just as in the standard Byte Program operation.

Refer to the Write Operation Status section for more

information.

Fig. 7 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations

tables in the AC Characteristics section for parame-

ters, and Fig. 21 section for timing diagrams.

Autoselect during Erase-Suspend- Read

Mode

ERASE SUSPEND/ERASE RESUME

In the erase-suspend-read mode, the system can

also issue the autoselected command sequence.

Refer to the Autoselect Mode and Autoselect Com-

mand Sequence section for details (Table 9).

An erase operation is a long-time operation so that

two useful commands are provided in the

ES29LV160 device Erase Suspend and Erase

Resume Commands. Through the two commands,

erase operation can be suspended for a while and

the suspended operation can be resumed later when

it is required. While the erase is suspended, read or

program operations can be performed by the system.

Erase Resume Command

To resume the sector erase operation, the system

must write the Erase Resume command. Further

writes of the Resume command are ignored.

Another Erase Suspend command can be written

after the chip has resumed erasing.

Erase Suspend Command, (B0h)

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then

read data from, or program data to, any sector not

selected for erasure. This command is valid only dur-

ing the sector erase operation, including the 50us

time-out period during the sector erase command

sequence. The Erase Suspend command is ignored

if written during the chip erase operation or Embed-

ded Program algorithm. When the Erase Suspend

command is written during the sector erase opera-

tion, the device requires a maximum of 20us to sus-

pend the erase operation. However, when the Erase

Suspend command is written during the sector erase

time-out, the device immediately terminates the time-

out period and suspends the erase operation.

Read and Program during Erase-Suspend-

Read Mode

After the erase operation has been suspended, the

device enters the erase-suspend-read mode. The

system can read data from or program data to any

sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.)

Reading at any address within erase-suspended sec-

tors produces status information on DQ7-DQ0. The

system can use DQ7, or DQ6 and DQ2 together, to

determine if a sector is actively erasing or is erase-

suspended. Refer to the Write Operation Status sec-

tion for information on these status bits (Table 10).

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COMMAND DIAGRAM

PA/PD

Program

Done

A0

20

AA

80

Unlock

Bypass

90

55

Auto-

select

10

98

SA/30

Chip

Erase

AA

F0

Done

CFI

Read

50us

Done

Sector

Erase

00

98

Resume

30

B0

Suspend

Erase-

suspend

Read

Figure 8. Command Diagram

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WRITE OPERATION STATUS

Erase algorithm is complete, or if the device enters

the Erase Suspend mode, Data# polling produces a

“1” on DQ7. The system must provide an address

within any of the sectors selected for erasure to read

valid status information on DQ7.

In the ES29LV160 device, several bits are provided

to determine the status of a program or erase oper-

ation: DQ2, DQ3, DQ5, DQ6, DQ7 and RY/BY#.

Table 10 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a

method for determining whether a program or erase

operation is complete or in progress. The device

also provides a hardware-based output signal, RY/

BY#, to determine whether an Embedded Program

or Erase operation is in progress or has been com-

pleted.

Erase on the Protected Sectors

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 1.8us,

then the device returns to the read mode. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and

ignores the selected sectors that are protected. How-

ever, if the system reads DQ7 at an address within a

protected sector, the status may not be valid.

DQ7 (DATA# POLLING)

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Program or Erase

algorithm is in progress or completed, or whether a

device is in Erase Suspend. Data# Polling is valid

after the rising edge of the final WE# pulse in the

command sequence.

Data# Polling Algorithm

Just prior to the completion of an Embedded

Program or Ease operation, DQ7 may change

asynchronously with DQ0-DQ6 while Output

Enable(OE#) is asserted low. That is, this device

may change from providing status information to

valid data on DQ7. Depending on when the system

samples the DQ7 output, it may read the status or

valid data. Even if the device has completed the

program or erase operation and DQ7 has valid data,

the data outputs on DQ0-DQ7 will appear on

successive read cycles.

During Programming

During the Embedded Program algorithm, the

device outputs on DQ7 the complement of the

datum programmed to DQ7. This DQ7 status also

applies to programming during Erase Suspend.

When the Embedded Program algorithm is com-

plete, the device outputs the datum programmed to

DQ7. The system must provide the program

address to read valid status information on DQ7. If

a program address falls within a protected sector,

Data# Polling on DQ7 is active for approximately

250ns, then the device returns to the read mode.

Table 10 shows the outputs for Data# Polling on

DQ7. Fig. 9 shows the Data# Polling algorithm. Fig.

22 in the AC Characteristics section shows the

Data# Polling timing diagram.

During Erase

During the Embedded Erase algorithm, Data# Poll-

ing produces a “0” on DQ7. When the Embedded

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Erase Suspend mode. Toggle Bit I may be read at

any address, and is valid after the rising edge of the

final WE# pulse in the command sequence ( prior to

the program or erase operation), and during the sec-

tor erase time-out. During an Embedded Program or

Erase algorithm operation, successive read cycles to

any address cause DQ6 to toggle. The system may

use either OE# or CE# to control the read cycles.

When the operation is complete, DQ6 stops tog-

gling.

START

Read DQ7-DQ0

Addr = VA

Yes

DQ7 = Data ?

No

DQ5 = 1 ?

The system can use DQ6 and DQ2 together to

determine whether a sector is actively erasing or is

erase-suspended. When the device is actively eras-

ing (that is, the Embedded Erase algorithm is in

progress), DQ6 toggles. When the device enters the

Erase Suspend mode, DQ6 stops toggling. How-

ever, the system must also use DQ2 to determine

which sectors are erasing or erase-suspended.

Alternatively, the system can use DQ7(see the sub-

section on DQ7:Data# Polling). DQ6 also toggles

during the erase-suspend-program mode, and stops

toggling once the Embedded Program algorithm is

complete.

Yes

Read DQ7-DQ0

Addr = VA

Yes

DQ7 = Data ?

No

FAIL

PASS

Notes:

1. VA = Valid address for programming. During a sector erase

operation, a valid address is any sector address within the

sector being erased. During chip erase, a valid address in

any non-protected sector address.

Table 10 shows the outputs for Toggle Bit I on DQ6.

Fig. 10 shows the toggle bit algorithm. Fig. 23 in the

“AC Characteristics” section shows the toggle bit

timing diagrams. Fig. 24 shows the differences

between DQ2 and DQ6 in graphical form. See also

the subsection on DQ2 : (Toggle Bit II).

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5

Figure 9. Data# Polling Algorithm

Toggling on the Protected Sectors

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 1.8us, then returns to reading

array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unpro-

tected sectors, and ignores the selected sectors that

are protected. If a program address falls within a

protected sector, DQ6 toggles for approximately

250ns after the program command sequence is writ-

ten, then returns to reading array data.

RY/BY# ( READY/BUSY# )

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is

in progress or complete. The RY/BY# status is valid

after the rising edge of the final WE# pulse in the

command sequence. Since RY/BY# is an open-

drain output, several RY/BY# pins can be tied

together in parallel with a pull-up resistor to Vcc. If

the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the

standby mode, or in the erase-suspend-read mode.

Table 10 shows the outputs for RY/BY#.

DQ2 ( TOGGLE BIT II )

The “Toggle Bit II” on DQ2, when used with DQ6,

indicates whether a particular sector is actively eras-

ing (that is, the Embedded Erase algorithm is in

progress), or whether that sector is erase-sus-

pended. Toggle Bit II is valid after the rising edge of

the final WE# pulse in the command sequence DQ2

DQ6 ( TOGGLE BIT I )

Toggle Bit I on DQ6 indicates whether an Embed-

ded Program or Erase algorithm is in progress or

complete, or whether the device has entered the

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toggles when the system reads at addresses within

those sectors that have been selected for erasure.

(The system may use either OE# or CE# to control

the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-

suspended. DQ6, by comparison, indicates

whether the device is actively erasing, or is in Erase

Suspend, but cannot distinguish which sectors are

selected for erasure. Thus, both status bits are

required for sector and mode information. Refer to

Table 10 to compare outputs for DQ2 and DQ6. Fig.

10 shows the toggle bit algorithm in flowchart form,

and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the DQ6: Toggle Bit I subsec-

tion. Fig. 23 shows the toggle bit timing diagram.

Fig. 24 shows how differently DQ2 operates com-

pared with DQ6.

START

Read DQ7-DQ0

No

Toggle Bit

= Toggle ?

Yes

DQ5 = 1 ?

Yes

No

Read DQ7-DQ0

Twice

Reading Toggle Bits DQ6/DQ2

No

Toggle Bit

= Toggle ?

Refer to Fig. 10 for the following discussion. When-

ever the system initially begins reading toggle bit

status, it must read DQ7-DQ0 at least twice in a row

to determine whether a toggle bit is toggling. Typi-

cally, the system would note and store the value of

the toggle bit after the first read. After the second

read, the system would compare the new value of

the toggle bit with the first. If the toggle bit is not

toggling, the device has completed the program or

erase operation. The system can read array data

on DQ7-DQ0 on the following read cycle. However,

if after the initial two read cycles, the system deter-

mines that the toggle bit is still toggling, the system

also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no

longer toggling, the device has successfully com-

pleted the program or erase operation. If it is still

toggling, the device did not completed the operation

successfully, and the system must write the reset

command to return to reading array data. The

remaining scenario is that the system initially deter-

mines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

the toggle bit and DQ5 through successive read

cycles, determining the status as described in the

previous paragraph. Alternatively, it may choose to

perform other system tasks. In this case, this sys-

tem must start at the beginning of the algorithm

when it returns to determine the status of the opera-

tion (top of Fig. 10).

Yes

Program/Erase

Operation

Complete

Program/Erase

Operation Not

Complete, Write

Reset Command

Note:

The system should recheck the toggle bit even if DQ5 = “1”

because the toggle bit may stop toggling as DQ5 changes to “1”.

See the subsections on DQ6 and DQ2 for more information.

Figure 10. Toggle Bit Algorithm

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DQ5 ( EXCEEDED TIMING LIMITS )

If additional sectors are selected for erasure, the

entire time-out also applies after each additional

sector erase command. When the time-out period is

complete, DQ3 switches from a “0” to a”1”. If the

time between additional sector erase commands

from the system can be assumed to be less than

50us, the system need not monitor DQ3. See also

the Sector Erase Command Sequence section. After

the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or

DQ6 (Toggle Bit I) to ensure that the device has

accepted the command sequence, and then read

DQ3. If DQ3 is “1”, the Embedded Erase algorithm

has begun; all further commands (except Erase Sus-

pend) are ignored until the erasure operation is com-

plete. If DQ3 is “0”, the device will accept additional

sector erase commands. To ensure the command

has been accepted, the system software should

check the status of DQ3 prior to and following each

subsequent sector erase command. If DQ3 is high

on the second status check, the last command might

not have been accepted. In Table 10, DQ3 status

operation is well defined and summarized with other

status bits, DQ7, DQ6, DQ5, and DQ2.

DQ5 indicates whether the program or erase time

has exceeded a specified internal pulse count limit.

Under these conditions DQ5 produces a “1”, indi-

cating that the program or erase cycle was not suc-

cessfully completed. The device may output a “1”

on DQ5 if the system tries to program a “1” to a

location that was previously programmed to “0”

Only an erase operation can change a “0” back to a

“1”. Under this condition, the device halts the opera-

tion, and when the timing limit has been exceeded,

DQ5 produces a ”1”. Under both these conditions,

the system must write the reset command to return

to the read mode.

DQ3 ( SECTOR ERASE TIMER )

After writing a sector erase command sequence,

the system may read DQ3 to determine whether or

not erasure has begun. (The sector erase time

does not apply to the chip erase command.)

Table 10. Write Operation Status

DQ7

DQ5

(Note 1)

DQ3

DQ2

(Note 2)

RY/

BY#

Status

DQ6

(Note 2)

DQ7#

0

Embedded Program Algorithm

Embedded Erase Algorithm

Toggle

0

N/A

No toggle

0

Standard

Mode

1

Toggle

Erase Suspended

Sector

1

No toggle

0

N/A

1

Erase-Suspend-

Read

Erase Sus-

pend Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes :

1. DQ5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the

section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

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ABSOLUTE MAXIMUM RATINGS

20ns

Storage Temperature

+0.8V

o

Plastic Packages ..............................................-65 C to +150 C

Vss-0.5V

Ambient Temperature

o

with Power Applied ...........................................-65 C to +125 C

Vss-2.0V

Voltage with Respect to Ground

20ns

Vcc (Note 1) ..........................................................-0.5V to +4.0V

A9, OE# and RESET# (Note 2) ........................-0.5V to +12.5V

All other pins (Note 1) ...................................-0.5V to Vcc + 0.5V

Negative Overshoot

Output Short Circuit Current (Note 3) ................. 200 mA

20ns

Notes:

Vcc+2.0V

1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage

transitions, input or I/O pins may overshoot Vss to -2.0V for per-

iods of up to 20ns. Maximum DC voltage on input or I/O pins is

Vcc+0.5V. See Fig. 11. During voltage transition, input or I/O pins

may overshoot to Vcc+2.0V for periods up to 20ns. See Fig. 11.

Vcc+0.5V

2.0V

2. Minimum DC input voltage on pins A9, OE# and RESET# is -0.5V

.

During voltage transitions, A9, OE# and RESET# may overshoot

Vss to -2.0V for periods of up to 20ns. See Fig. 11. Maximum DC

input voltage on pin A9 is +12.5V which may overshoot to +14.0V

for periods up to 20ns.

20ns

Positive Overshoot

3. No more than one output may be shorted to ground at a time. Du-

ration of the short circuit should not be greater than one second.

Figure 11. Maximum Overshoot Waveform

Stresses above those listed under “Absolute Maximum Ratings” may

cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditions ab-

ove those indicated in the operational sections of this datasheet is

not implied. Exposure of the device to absolute maximum rating con-

ditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A).................................-40^oC to +85^oC

Commercial Devices

Ambient Temperature (T_A)....................................0^oC to +70^oC

Vcc Supply Voltages

Vcc for all devices ............................................2.7V to 3.6V

Operating ranges define those limits between which the functio-

nality of the device is guaranteed.

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DC CHARACTERISTICS

Table 11. CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

Min Typ

Max

Unit

I_LI

Input Load Current

V_IN=Vss to Vcc

Vcc=Vcc max

+ 1.0

uA

I_LIT

I_LR

I_LO

A9 Input Load Current

Vcc=Vcc max; A9=12.5V

35

uA

RESET# Input Load Current

Output Leakage Current

Vcc=Vcc max; RESET#=12.5V

35

Vout=Vss to Vcc,

Vcc=Vcc max

+ 1.0

5MHz

9

2

16

4

CE#=V_ILOE#=V_IH, Byte

mode

1MHz

I_CCI

Vcc Active Read Current

(Notes 1,2)

mA

CE#=V_IL, OE#=V_IH, Word

mode

5MHz

1MHz

9

16

4

2

I_CC2

I_CC3

I_CC4

I_CC5

Vcc Active Write Current (Note 2,3)

Vcc Standby Current (Note 2)

Vcc Reset Current (Note 2)

CE#=V_IL, OE#=V_IH, WE#=V_IL

CE#, RESET#= Vcc+0.3V

RESET#=Vss + 0.3V

15

30

mA

uA

0.2

10

Automatic Sleep Mode

(Notes2,4)

V_IH= Vcc + 0.3V

V_IL= Vss + 0.3V

V_IL

V_IH

V_ID

Input Low Voltage

Input High Voltage

-0.5

0.8

V

0.7xVcc

11.5

Vcc+0.3

12.5

Voltage for Autoselect and

Temporary Sector Unprotect

Vcc = 3.0V + 10%

V_OL

Output Low Voltage

I_OL= 4.0 mA, Vcc = Vcc min

I_OH= -2.0mA, Vcc = Vcc min

I_OH= -100 uA, Vcc = Vcc min

0.45

V

V_OH1

V_OH2

V_LKO

0.85 Vcc

Vcc - 0.4

2.3

Output High Voltage

V

Low Vcc Lock-Out Voltage (Note 5)

2.5

Notes:

1. The Icc current listed is typically less than 2 mA/MHz, with OE# at V_IH, Typical condition : 25^oC, Vcc = 3V

2. Maximum I_CCspecifications are tested with Vcc = Vcc max.

3. Icc active while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30ns. Typical sleep mode current is

200 nA.

5. Not 100% tested.

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DC CHARACTERISTICS

Zero-Power Flash

25

Icc1 (Active Read current)

20

Icc5 (Automatic Sleep Mode)

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 12. I_cc1Current vs. Time (Showing Active and Automatic Sleep Currents)

12

3.6V

2.7V

10

8

6

4

2

0

1

3

2

4

5

Note: T = 25^oC

Frequency in MHz

Figure 13. Typical I_cc1vs. Frequency

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3.3V

Table 12. Test Specifications

2.7k

Ω

Test Condition

70

90

1TTL gate

30 pF

Device

Under

Test

Output Load

C

L

Output Load Capacitance, C_L(including jig

capacitance)

30 pF

6.2kΩ

Input Rise and Fall Times

5 ns

0.0 - 3.0 V

1.5 V

Input Pulse Levels

Input timing measurement reference levels

Output timing measurement reference levels

Figure 14. Test Setup

1.5 V

Note: Diodes are IN3064 or equivalent

Key To Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0V

1.5V Output

Input 1.5V

Measurement Level

0.0V

Figure 15. Input Waveforms and Measurement Levels

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AC CHARACTERISTICS

Table 13. Read-Only Operations

Parameter

Speed

Unit

Description

Test Setup

Options

JEDEC Std.

70

90

t_AVAV

t_RC

t_ACC

t_CE

t_OE

t_DF

Read Cycle Time(Note 1)

Min

70

35

90 ns

t_AVQV

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_AXQX

Address to Output Delay

CE#,OE#=V_IL

OE#=V_IL

Max

Min

90 ns

40 ns

ns

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

16

0

t_DF

ns

t_OH

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First

ns

t_OEH

Output Enable Hold

Time (Note 1)

Read

Min

0

ns

Toggle and Data# Polling

10

Note : 1. Not 100% tested

t_RC

Address

Address Stable

t_ACC

CE#

OE#

WE#

t_RH

t_DF

t_RH

t_OE

t_OEH

t_CE

t_OH

High-Z

OUTPUTS

Output Valid

RESET#

RY/BY#

0V

Figure 16. Read Operation Timings

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AC CHARACTERISTICS

Table 14. Hardware Reset ( RESET #)

Parameter

Description

All Speed Options Unit

JEDEC Std.

t_Ready

RESET# Pin Low (During Embedded Algorithms) to Read Mode

(See Note)

Max

20

us

t_Ready

RESET# Pin Low (Not During Embedded Algorithms) to Read

Mode (See Note)

500

ns

t_RP

RESET# Pulse Width

Min

500

50

20

0

ns

us

ns

t_RH

t_RPD

t_RB

RESET High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note : Not 100% tested

RY/BY#

0V

CE#,OE#

RESET#

t_RH

t_RP

t_READY

(A) Not During Embedded Algorithm

t_READY

RY/BY#

t_RB

CE#,OE#

RESET#

t_RP

(B) During Embedded Algorithm

Figure 17. Reset Timings

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AC CHARACTERISTICS

Table 15. Word/Byte Configuration (BYTE#)

Parameter

Description

70

90

Unit

JEDEC

Std.

t_ELFL/t_ELFH

t_FLQZ

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

5

ns

30

90

t_FHQV

70

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ0-DQ14)

Data Output

(DQ0-DQ7)

BYTE# Switching

Switching from

word to byte mode

DQ0-DQ14

DQ15/A-1

DQ15

Output

Address Input

t_FLQZ

t_ELFH

BYTE#

BYTE# Switching

Switching from

byte to word mode

Data Output

(DQ0-DQ7)

Data Output

(DQ0-DQ14)

DQ0-DQ14

DQ15

Output

Address Input

DQ15/A-1

t_FHQV

Figure 18. BYTE# Timing for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

t_HOLD

(t_AH

(t_AS

)

Note : Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 19. BYTE# Timing for Write Operations

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AC CHARACTERISTICS

Table 16. Erase and Program Operations

Parameter

Description

70

90

Unit

JEDEC

t_AVAV

Std.

t_WC

Write Cycle Time (Note 1)

Min

70

90

ns

t_AVWL

t_AS

Address Setup Time

0

t_ASO

t_AH

t_AHT

t_DS

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

45

t_WLAX

45

35

Address Hold Time From CE# or OE# high during toggle bit polling

Data Setup Time

0

t_DVWH

t_WHDX

45

t_DH

Data Hold Time

0

t_OEPH

t_GHWL

t_CS

Output Enable High during toggle bit polling

Read Recovery Time Before Write (OE# High to WE# Low)

CE# Setup Time

20

0

t_GHWL

t_ELWL

0

t_WHEH

t_WLWH

t_WHDL

t_CH

CE# Hold Time

0

t_WP

Write Pulse Width

35

t_WPH

t_SR/W

Write Pulse Width High

30

0

Latency Between Read and Write Operations

Byte

Typ

6

8

t_WHWH1

t_WHWH2

t_WHWH1

Programming Operation (Note 2)

Word

us

t_WHWH2

t_VCS

Sector Erase Operation (Note 2)

Vcc Setup Time (Note 1)

0.7

sec

us

Min

Max

50

0

t_RB

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ns

t_BUSY

90

ns

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

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AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data(last two cycles)

t_WC

t_AS

Address

555h

PA

t_AH

CE#

t_CH

OE#

WE#

t_CS

t_WP

t_WHWH1

t_WPH

t_DS

t_DH

Status

Dout

A0h

PD

t_BUSY

DATA

t_RB

RY/BY#

Vcc

t_VCS

NOTES :

1. PA = program address, PD = program data, Dout is the true data at the program address.

2. Illustration shows device in word mode.

Figure 20. Program Operation Timings

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AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

t_AH

t_WC

t_AS

SA

Address

2AAh

VA

555h for chip erase

CE#

t_CH

OE#

WE#

t_CS

t_WP

t_WHWH2

t_WPH

t_DS

t_DH

10h for chip erase

30h

In

Complete

55h

Progress

DATA

t_RB

t_BUSY

RY/BY#

Vcc

t_VCS

NOTES :

1. SA = sector address(for Sector Erase), VA = valid address for reading status data(see “Write Operation Status”).

2. These waveforms are for the word mode.

Figure 21. Chip/Sector Erase Operation Timings

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AC CHARACTERISTICS

t_RC

Address

VA

t_ACC

VA

t_CE

CE#

OE#

t_CH

t_OE

t_OEH

t_DF

WE#

t_OH

HIGH-Z

DQ7

Complement

Status Data

True

Valid Data

HIGH-Z

DQ0-DQ6

Status Data

True

Valid Data

t_BUSY

RY/BY#

NOTE : VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle

Figure 22. Data# Polling Timings (During Embedded Algorithms)

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AC CHARACTERISTICS

t_AHT

t_AS

Address

t_ASO

t_AHT

CE#

t_OEH

t_CEPH

WE#

OE#

t_OEPH

t_DH

t_OE

DQ6/DQ2

RY/BY#

Valid Data

Valid Status

(first read)

Valid Status

(second read)

Valid Status

(stops toggling)

NOTE : VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

Figure 23. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Enter Erase

Suspend

Program

Enter

Suspend

Erase

Resume

WE#

Erase

Suspend

Program

Erase

Suspend

Read

Erase

Complete

Erase

Suspend

Read

Erase

DQ6

DQ2

NOTE : DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 24. DQ2 vs. DQ6

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AC CHARACTERISTICS

Table 17. Temporary Sector Unprotect

Parameter

Description

All Speed Options

Unit

JEDEC Std.

t_VIDR

t_RSP

t_RRB

V_IDRise and Fall Time (See Note)

Min

500

4

ns

us

RESET# Setup Time for Temporary Sector Unprotect

RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect

4

Note: Not 100% tested.

V_ID

RESET#

Vss,V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 25. Temporary Sector Unprotect Timing Diagram

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AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA,A6,

A1,A0

Valid*

Sector Protect or Unprotect

Valid*

Verify

Status

DQ

60h

40h

Sector Protect : 150us,

Sector Unprotect: 15ms

1us

CE#

WE#

OE#

* For sector protect, A6=0,A1=1,A0=0 For sector unprotect, A6=1,A1=1,A0=0

Figure 26. Sector Protect & Unprotect Timing Diagram

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AC CHARACTERISTICS

Table 18. Alternate CE# Controlled Erase and Program Operations

Parameter

Description

70

90

Unit

JEDEC

t_AVAV

Std.

t_WC

t_AS

Write Cycle Time( Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

70

90

ns

t_AVWL

t_ELAX

t_DVEH

t_EHDX

t_GHEL

t_WLEL

t_EHWH

t_ELEH

t_ELEL

0

t_AH

45

35

45

t_DS

t_DH

Data Hold Time

0

t_GHEL

t_WS

t_WH

t_CP

Read Recovery Time Before Write (OE# High to WE# Low)

0

WE# Setup Time

WE# Hold Time

CE# Pulse Width

CE# Pulse Width High

Byte

35

t_CPH

30

Typ

6

8

t_WHWH1

t_WHWH2

t_WHWH1

t_WHWH2

Programming Operation (Note 2)

us

Word

Sector Erase Operation (Note 2)

0.7

sec

Notes :

1. Not 100% tested

2. See the “Erase And Programming Performance” section for more information.

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AC CHARACTERISTICS

PD for program

SA for sector erase

555 for chip erase

555 for program

2AA for erase

Data Polling

Address

PA

t_AH

t_AS

t_WC

t_WH

WE#

t_GHEL

OE#

CE#

t_{WHWH1 or 2}

t_CP

t_CPH

t_WS

t_DS

t_BUSY

t_DH

D_OUT

DQ7#

DATA

t_RH

PD for program

30 for sector erase

10 for chip erase

A0 for program

55 for erase

RESET#

RY/BY#

NOTES :

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data

3. DQ7# is the complement of the data written to the device. Dout is the data written to the device.

4. Waveforms are for the word mode.

Figure 27. Alternate CE# Controlled

Write(Erase/Program) Operation Timings

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Table 19. AC CHARACTERISTICS

Parameter

Description

Value

35/40

500

150

15

Unit

ns

t_OE

t_VIDR

t_WPP1

t_WPP2

t_OESP

t_CSP

Output Enable to Output Delay

Voltage Transition Time

Max

Min

ns

Write Pulse Width for Protection Operation

Write Pulse Width for Unprotection Operation

OE# Setup Time to WE# Active

CE# Setup Time to WE# Active

Voltage Setup Time

us

ms

us

4

us

t_ST

4

us

A<19:12>

SAy

SAx

A<0>

A

<1>

<6>

A

t_VIDR

V_ID

t_VIDR

A<9>

t_ST

V_ID

OE#

WE#

t_OESP

t_WPP1

t_ST

t_OE

t_CSP

CE#

DQ

0x01

RESET#

Vcc

Figure 28. Sector Protection timings (A9 High-Voltage Method)

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AC CHARACTERISTICS

A<19:12>

SA1

SA0

A<0>

A

<1>

<6>

A

t_VIDR

V_ID

t_VIDR

A<9>

t_ST

V_ID

OE#

WE#

t_OESP

t_WPP2

t_ST

t_OE

t_CSP

CE#

DQ

0x00

RESET#

Vcc

NOTE : It is recommended to verify for all sectors.

Figure 29. Sector Unprotection timings (A9 High-Voltage Method)

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Table 20. ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2) Unit

Comments

Sector Erase Time

0.7

25

6

15

sec

us

Excludes 00h programming prior to

erasure (Note 4)

Chip Erase Time

Byte Program Time

Word Program Time

150

210

8

us

Exclude system level overhead (Note 5)

Byte Mode

Word Mode

12.6

8.4

37.8

25.2

Chip Program Time (Note 3)

sec

Notes:

1. Typical program and erase times assume the following conditions: 25^oC, 3.0V Vcc, 10,000 cycles. Additionally, programming

typicals assume checkerboard pattern.

2. Under worst case conditions of 90^oC, Vcc = 2.7V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two-or-four-bus-cycle sequence for the program command. See

Table 9 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles

.

Table 21. LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to Vss on all pins except I/O pins (including A9, OE#, and RESET#)

Input voltage with respect to Vss on all I/O pins

- 1.0V

12.5 V

Vcc + 1.0 V

+100 mA

Vcc Current

- 100 mA

Note: Includes all pins except Vcc. Test conditions: Vcc = 3.0 V, one pin at a time

Table 22. TSOP, SO, AND BGA PACKAGE CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

7.5

5.0

12

Unit

TSOP

6

pF

C_IN

Input Capacitance

V_IN= 0

V_OUT= 0

V_IN= 0

FBGA

TSOP

FBGA

TSOP

FBGA

4.2

8.5

5.4

7.5

3.9

C_OUT

Output Capacitance

6.5

9

C_IN2

Control Pin Capacitance

4.7

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25^oC, f=1.0MHz.

Table 23. DATA RETENTION

Parameter Description

Test conditions

Min

Unit

150^oC

125^oC

10

Years

Minimum Pattern Data Retention Time

20

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PHYSICAL DIMENSIONS

48-Pin Standard TSOP (measured in millimeters)

0.10

C

2

A2

N

1

SEE DETAIL B

-B-

-A-

5

E

e

9

N

2

N

2

---- + 1

----

5

4

D1

A1

-C-

D

SEATING

PLANE

B

0.08MM (0.0031”)

b

M

C A-B S

6

7

A

WITH

PLATING

B

SEE DETAIL A

(c)

c1

7

BASE

METAL

b1

R

c

SECTION B-B

GAUGE

PLANE

0.25MM

(0.0098”) BSC

e/2

θ°

PARALLEL TO

SEATING PLANE

L

-X-

X = A OR B

DETAIL A

DETAIL B

NOTES:

Package

TS 48

JEDEC

MO-142 (B) DD

1. Controlling dimensions are in millimeters(mm). (Dimensioning

and tolerancing conforms to ANSI Y14.5M-1982)

Symbol

MIN

-

NOM

MAX

2. Pin 1 identifier for standard pin out (Die up).

A

A1

A2

b1

b

-

1.20

0.15

1.05

0.23

3. Pin 1 identifier for reverse pin out (Die down): Ink or Laser mark

4. To be determined at the seating plane. The seating plane is def-

ined as the plane of contact that is made when the package lea-

ds are allowed to rest freely on a flat horizontal surface.

5. Dimension D1 and E do not include mold protrusion. Allowable

mold protrusion is 0.15mm (0.0059”) per side.

0.05

0.95

0.17

0.10

19.80

18.30

11.90

-

1.00

0.20

0.22

0.27

6. Dimension b does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.0031”) total in excess

of b dimension at max. material condition. Minimum space

between protrusion and an adjacent lead to be 0.07mm

(0.0028”).

c1

c

-

0.16

0.21

-

20.00

18.40

12.00

0.50 BASIC

0.60

D

20.20

18.50

12.10

7. These dimensions apply to the flat section of the lead between

0.10mm (0.0039”) and 0.25mm (0.0098”) from the lead tip.

8. Lead coplanarity shall be within 0.10mm (0.004”) as measured

from the seating plane.

D1

E

e

9. Dimension “e” is measured at the centerline of the leads.

L

0.50

0°

0.70

5°

θ

3°

R

N

0.08

-

0.20

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PHYSICAL DIMENSIONS

48-Ball FBGA (6 x 8 mm)

0.20

(4x)

D1

A

D

H

G F

E

D

C

B

A

6

5

4

7

SE

e

E

E1

3

2

1

6

b

7

SD

B

A1 CORNER INDEX MARK 11

PIN 1 ID.

0.15 M Z A B

0.08 M Z

10

//

0.25

Z

A2

A

0.08

Z

A1

NOTES:

PACKAGE

JEDEC

xFBD 048

N/A

1. Dimensioning and tolerancing per ASME Y14.5M-1994

2. All dimensions are in millimeters.

6.00 mm x8.00 mm PACKAGE

3. Ball position designation per JESD 95-1, SPP-010.

4. e represents the solder ball grid pitch.

5. Symbol “MD” is the ball row matrix size in the “D” direction.

Symbol “ME” is the ball column matrix size in the “E” direct-

ion. N is the maximum number of solder balls for matrix si-

ze MD X ME.

SYMBOL

A

MIN

NOM

MAX

1.10

NOTE

OVERALL THICK

NESS

A1

A2

D

0.21

0.7

0.25

0.76

0.29

0.82

BALL HEIGHT

BODY THICKNESS

BODY SIZE

8.00 BSC

6. Dimension “b” is measured at the maximum ball diameter

in a plane parallel to datum Z.

E

6.00 BSC

5.60 BSC

4.00 BSC

8

BODY SIZE

D1

E1

MD

BALL FOOTPRINT

7. SD and SE are measured with respect to datums A and B

and define the position of the center solder ball in the out-

er row. When there is an odd number of solder balls in the

outer row parallel to the D or E dimension, respectively, SD

or SE = 0.000 when there is an even number of solder balls

in the outer row, SD or SE = e/2

8. “X” in the package variations denotes part is outer qualifi-

cation.

9. “+” in the package drawing indicate the theoretical center

of depopulated balls.

ROW MATRIX SIZED

DIRECTION

ME

6

ROW MATRIX SIZED

DIRECTION

N

48

TOTAL BALL COUNT

BALL DIAMETER

BALL PITCH

b

0.30

0.35

0.40

0.80 BSC

0.40 BSC

e

SD / SE

SOLDER BALL

PLACEMENT

10. For package thickness A is the controlling dimension.

11. A1 corner to be indentified by chamfer, ink mark, metalli-

zed markings indention or other means.

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ORDERNG INFORMATION

Standard Products

ESI standard products are available in several package and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the following:

ES 29 LV 160 X X - XX

X

X X X

TEMPERATURE RANGE

Blank : Commercial (0^oC to + 70^oC)

I

:

Industrial (- 40^oC to + 85^oC)

Pb-free

C

:

Pb product

G

:

Pb-free product

PACKAGE TYPE

T : Standard TSOP (48-pin), W : FBGA(48-ball)

VOLTAGE RANGE

Blank : 2.7 ~ 3.6V

SPEED OPTION

70 : 70ns

90 : 90ns

SECTOR ARCHITECTURE

Blank : Uniform sector

T

B

:

Top sector

Bottom sector

TECHNOLOGY

D : 0.18um

E : 0.18um(2nd Gen.) F : 0.13um

DENSITY & ORGANIZATION

400 : 4M ( x8 / x16)

160 : 16M ( x8 / x16)

640 : 64M ( x8 / x16)

800 : 8M ( x8 / x16)

320 : 32M ( x8 / x16)

POWER SUPPLY AND INTERFACE

F

: 5.0V

LV : 3.0V

DL

: 3.0V, Dual Bank

DS : 1.8V, Dual Bank

BDS : 1.8V, Burst mode, Dual Bank

COMPONENT GROUP

29 : Flash Memory

EXCEL SEMICONDUCTOR

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Product Selection Guide

Industrial Device

Part No.

Speed Vcc

Boot Sector

Top

Ball Pitch/Size

Package

Pb

Body Size

ES29LV160ET-70TGI

ES29LV160ET-70TCI

ES29LV160EB-70TGI

ES29LV160EB-70TCI

ES29LV160ET-90TGI

ES29LV160ET-90TCI

ES29LV160EB-90TGI

ES29LV160EB-90TCI

70ns

90ns

2.7 - 3.6V

48-pin TSOP

Pb-free

2.7 - 3.6V

Top

-

Bottom

Top

Pb-free

-

Pb-free

Top

-

Bottom

Pb-free

-

ES29LV160ET-70WGI

ES29LV160ET-70WCI

ES29LV160EB-70WGI

ES29LV160EB-70WCI

ES29LV160ET-90WGI

ES29LV160ET-90WCI

ES29LV160EB-90WGI

ES29LV160EB-90WCI

70ns

90ns

2.7 - 3.6V

Top

0.8mm/0.3mm

48-Ball FBGA

Pb-free

6mm x 8mm

Top

-

Bottom

Top

Pb-free

-

Pb-free

Top

-

Bottom

Pb-free

-

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Product Selection Guide

Commercial Device

Part No.

Speed Vcc

Boot Sector

Top

Ball Pitch/Size

Package

Pb

Body Size

ES29LV160ET-70TG

ES29LV160ET-70TC

ES29LV160EB-70TG

ES29LV160EB-70TC

ES29LV160ET-90TG

ES29LV160ET-90TC

ES29LV160EB-90TG

ES29LV160EB-90TC

70ns

90ns

2.7 - 3.6V

48-pin TSOP

Pb-free

2.7 - 3.6V

Top

-

Bottom

Top

Pb-free

-

Pb-free

Top

-

Bottom

Pb-free

-

ES29LV160ET-70WG

ES29LV160ET-70WC

ES29LV160EB-70WG

ES29LV160EB-70WC

ES29LV160ET-90WG

ES29LV160ET-90WC

ES29LV160EB-90WG

ES29LV160EB-90WC

70ns

90ns

2.7 - 3.6V

Top

0.8mm/0.3mm

48-Ball FBGA

Pb-free

6mm x 8mm

Top

-

Bottom

Top

Pb-free

-

Pb-free

Top

-

Bottom

Pb-free

-

52

Rev. 0B January 5 , 2006

ES29LV160E

E S I

Excel Semiconductor inc.

Document Title

16M Flash Memory

Revision History

Revision Number

Rev. 0A

Data

Items

Sep. 1, 2005

Jan. 5, 2006

Initial Release Version.

Add RoHS-Compliant Package Option.

Rev. 0B

Excel Semiconductor Inc.

1010 Keumkang Hightech Valley, Sangdaewon1-Dong 133-1, Jungwon-Gu, Seongnam-Si, Kyongki-Do, Rep.

of Korea. Zip Code : 462-807 Tel : +82-31-777-5060 Fax : +82-31-740-3798 Homepage : www.excelsemi.com

/

The attached datasheets are provided by Excel Semiconductor.inc (ESI). ESI reserves the right to change the spec-

ifications and products. ESI will answer to your questions about device. If you have any questions, please contact the

ESI office.

53

Rev. 0B January 5 , 2006

ES29LV160E


型号：	ES29DS640DT-90TGI
厂家：	EXCEL SEMICONDUCTOR INC.
描述：	16Mbit(2M x 8/1M x 16) CMOS 3.0 Volt-only, Boot Sector Flash Memory 16兆（ 2M ×8 / 1M ×16 ）的CMOS 3.0伏只，引导扇区闪存闪存
文件：	总53页 (文件大小：700K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ES29DS640DT-90TGI [EXCELSEMI]

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