XRT86VX38IB329-F [EXAR]
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION; 八路T1 / E1 / J1成帧器/ LIU康贝 - 硬件描述
| 型号： | XRT86VX38IB329-F |
| 厂家： | 
EXAR CORPORATION |
| 描述： | OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
| 文件： | 总61页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
JANUARY 2010
REV. 1.0.2
payload content of Receive LAPD Message frames
from the incoming T1/E1/J1 data stream and write the
contents into the Receive HDLC buffers. Each framer
also contains a Transmit and Overhead Data Input
port, which permits Data Link Terminal Equipment
direct access to the outbound T1/E1/J1 frames.
Likewise, a Receive Overhead output data port
permits Data Link Terminal Equipment direct access
to the Data Link bits of the inbound T1/E1/J1 frames.
GENERAL DESCRIPTION
The XRT86VX38 is an eight-channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Short-
hual LIU integrated solution featuring R3 technology
(Relayless, Reconfigurable, Redundancy) and BITS
Timing element. The physical interface is optimized
with internal impedance, and with the patented pad
structure, the XRT86VX38 provides protection from
power failures and hot swapping.
The XRT86VX38 fully meets all of the latest T1/E1/J1
specifications:
ANSI T1/E1.107-1988, ANSI T1/
The XRT86VX38 contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/E1/J1 signal formats.
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
Each Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function. There are 3
Transmit HDLC controllers per channel which
encapsulate contents of the Transmit HDLC buffers
into LAPD Message frames. There are 3 Receive
HDLC controllers per channel which extract the
Applications and Features (next page)
FIGURE 1. XRT86VX38 8-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO
External Data
Link Controller
Local PCM
Highway
Tx Overhead In
Rx Overhead Out
XRT86VX38
1 of 8-channels
1:2 Turns Ratio
1:1 Turns Ratio
TTIP
2-Frame
Slip Buffer
Elastic Store
Tx Serial
Data In
Tx LIU
Interface
Tx Framer
Rx Framer
TRING
Tx Serial
Clock
LLB
LB
RTIP
2-Frame
Slip Buffer
Elastic Store
Rx Serial
Data Out
Rx LIU
Interface
RRING
Rx Serial
Clock
LIU &
Loopback
Control
PRBS
Generator &
Analyser
HDLC/LAPD
Controllers
Performance
Monitor
RxLOS
Line Side
8kHz sync
OSC
DMA
Interface
Microprocessor
Interface
Signaling&
Alarms
JTAG
Back Plane
1.544-16.384 Mbit/s
WR
ALE_AS
4
3
INT
D[7:0]
RD
A[14:0]
µP
Select
System (Terminal) Side
RDY_DTACK
TxON
Intel/Motorola µP
Memory
Configuration, Control &
Status Monitor
Exar Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems
SONET/SDH terminal or Add/Drop multiplexers (ADMs)
T1/E1/J1 add/drop multiplexers (MUX)
Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1
BITS Timing
Digital Access Cross-connect System (DACs)
Digital Cross-connect Systems (DCS)
Frame Relay Switches and Access Devices (FRADS)
ISDN Primary Rate Interfaces (PRA)
PBXs and PCM channel bank
T3 channelized access concentrators and M13 MUX
Wireless base stations
ATM equipment with integrated DS1 interfaces
Multichannel DS1 Test Equipment
T1/E1/J1 Performance Monitoring
Voice over packet gateways
Routers
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Supports Section 13 - Synchronization Interface in ITU G.703 for both Transmit and Receive Paths
Supports SSM Synchronous Messaging Generation (BOC for T1, National Bits for E1) on the Transmit Path
Supports SSM Synchronous Messaging Extraction (BOC for T1, National Bits for E1) on the Receive Path
Supports BITS timing generation on the Transmit Outputs
Supports BITS timing extraction from NRZ data on the Analog Receive Path
DS-0 Monitoring on both Transmit and Receive Time Slots
Supports SSM Synchronization Messaging per ANSI T1.101-1999 and ITU G.704
Supports a Customized Section 13 - Synchronization Interface in G.703 at 1.544MHz
Independent, full duplex DS1 Tx and Rx Framer/LIUs
Each channel has full featured Long-haul/Short-haul LIU
Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz
asynchronous back plane connections with jitter and wander attenuation
•
Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 2-channel
multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus
•
•
•
•
Programmable output clocks for Fractional T1/E1/J1
Supports Channel Associated Signaling (CAS)
Supports Common Channel Signalling (CCS)
Supports ISDN Primary Rate Interface (ISDN PRI) signaling
2
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
•
•
Extracts and inserts robbed bit signaling (RBS)
3 Integrated HDLC controllers for transmit and receive, each controller having two 96-byte buffers (buffer 0 /
buffer 1)
•
•
•
•
HDLC Controllers Support SS7
Timeslot assignable HDLC
V5.1 or V5.2 Interface
Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface
every 1 second or for a single transmission
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports SPRM and NPRM
Alarm Indication Signal with Customer Installation signature (AIS-CI)
Remote Alarm Indication with Customer Installation (RAI-CI)
Gapped Clock interface mode for Transmit and Receive.
Intel/Motorola and Power PC interfaces for configuration, control and status monitoring
Parallel search algorithm for fast frame synchronization
Wide choice of T1 framing structures: SF/D4, ESF, SLC®96, T1DM and N-Frame (non-signaling)
Direct access to D and E channels for fast transmission of data link information
Full BERT Controller for generation and detection on system and line side of the chip
PRBS, QRSS, and Network Loop Code generation and detection
Seven Independent, simultaneous Loop Code Detectors per Channel
Programmable Interrupt output pin
Supports programmed I/O and DMA modes of Read-Write access
The framer block encodes and decodes the T1/E1/J1 Frame serial data
Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms
Detects OOF, LOF, LOS errors and COFA conditions
Loopbacks: Local (LLB) and Line remote (LB)
Facilitates Inverse Multiplexing for ATM
Performance monitor with one second polling
Boundary scan (IEEE 1149.1) JTAG test port
Accepts external 8kHz Sync reference
1.8V Inner Core
3.3V CMOS operation with 5V tolerant inputs
256-pin fpBGA and 329-pin fpBGA package with -40°C to +85°C operation
ORDERING INFORMATION
P
ART
NUMBER
P
ACKAGE
OPERATING TEMPERATURE RANGE
XRT86VX38IB329
XRT86VX38IB256
329 Fine Pitch Ball Grid Array
256 Fine Pitch Ball Grid Array
-40
-40
°
C to +85
C to +85
°
C
C
°
°
3
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
329 BALL - FINE PITCH BALL GRID ARRAY (BOTTOM VIEW - SEE PIN LIST FOR DESCRIPTION)
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
O O O O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
G
H
J
O O O O O O O
O O O O O O O
O O O O O O O
O O O O O O O
O O O O O O O
O O O O O O O
O O O O O O O
K
L
M
N
P
R
T
O O O O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O O O O
U
V
W
4
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
256 BALL - FINE PITCH BALL GRID ARRAY (BOTTOM VIEW - SEE PIN LIST FOR DESCRIPTION)
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
O O O O O O O O O O O O O O O O
G
H
J
K
L
M
N
P
R
T
5
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
LIST OF PARAGRAPHS
1.0 PIN LISTS .................................................................................................................................................6
2.0 PIN DESCRIPTIONS ..............................................................................................................................12
I
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
LIST OF FIGURES
Figure 1.: XRT86VX38 8-channel DS1 (T1/E1/J1) Framer/LIU Combo ............................................................................ 1
Figure 2.: Framer System Transmit Timing Diagram (Base Rate/Non-Mux) ................................................................... 40
Figure 3.: Framer System Receive Timing Diagram (RxSERCLK as an Output) ............................................................ 41
Figure 4.: Framer System Receive Timing Diagram (RxSERCLK as an Input) ............................................................... 41
Figure 5.: Framer System Transmit Timing Diagram (HMVIP and H100 Mode) ............................................................. 42
Figure 6.: Framer System Receive Timing Diagram (HMVIP/H100 Mode) ..................................................................... 43
Figure 7.: ITU G.703 Pulse Template .............................................................................................................................. 47
Figure 8.: ITU G.703 Section 13 Synchronous Interface Pulse Template ....................................................................... 48
Figure 9.: DSX-1 Pulse Template (normalized amplitude) .............................................................................................. 49
Figure 10.: Intel µP Interface Timing During Programmed I/O Read and Write Operations When ALE Is Not Tied ’HIGH’ 51
Figure 11.: Intel µP Interface Timing During Programmed I/O Read and Write Operations When ALE Is Tied ’HIGH’ .. 52
Figure 12.: Motorola Asychronous Mode Interface Signals During Programmed I/O Read and Write Operations ......... 53
Figure 13.: Power PC 403 Interface Signals During Programmed I/O Read and Write Operations ............................... 54
II
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
LIST OF TABLES
Table 1:: 329 Ball List by Ball Number ...............................................................................................................................6
Table 2:: 256 Ball List by Ball Number ...............................................................................................................................9
Table 3:: Pin Description Structure ..................................................................................................................................12
Table 4:: E1 Receiver Electrical Characteristics ..............................................................................................................44
Table 5:: T1 Receiver Electrical Characteristics ..............................................................................................................45
Table 6:: E1 Transmitter Electrical Characteristics ..........................................................................................................45
Table 7:: E1 Transmit Return Loss Requirement .............................................................................................................46
Table 8:: T1 Transmitter Electrical Characteristics ..........................................................................................................46
Table 9:: Transmit Pulse Mask Specification ...................................................................................................................47
Table 10:: E1 Synchronous Interface Transmit Pulse Mask Specification .......................................................................48
Table 11:: DSX1 Interface Isolated pulse mask and corner points ..................................................................................49
Table 12:: AC Electrical Characteristics ...........................................................................................................................50
Table 13:: Intel Microprocessor Interface Timing Specifications ......................................................................................51
Table 14:: Intel Microprocessor Interface Timing Specifications ......................................................................................52
Table 15:: Motorola Asychronous Mode Microprocessor Interface Timing Specifications ...............................................53
Table 16:: Power PC 403 Microprocessor Interface Timing Specifications .....................................................................54
III
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
1.0 PIN LISTS
TABLE 1: 329 BALL
L
IST
TABLE 1: 329 BALL
LIST
TABLE 1: 329 BALL
LIST
BY ALL UMBER
B
N
BY ALL UMBER
B
N
BY ALL UMBER
B
N
T
ABLE 1: 329 BALL
LIST
P
IN
P
IN
N
AME
P
IN
P
IN
N
AME
P
IN
PIN NAME
BY ALL UMBER
B
N
B13
B14
B15
B16
B17
B18
B19
C1
RXLOS1
D7
D8
TDO
RXSER0
F1
F2
RRING1
VSS
P
IN
PIN NAME
TXMSYNC1
TXSIG1
A1
A2
VDD
D9
RXSERCLK0
RXCRCSYNC0
TXSER0
RXCRCSYNC1
VDD18
F3
TTIP1
TRING1
VDD
VDDPLL18
VSS
RXSERCLK2
RXSER2
TXSIG2
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
E1
F4
A3
F5
A4
DGND
F15
F16
F17
F18
F19
G1
VDD18
A5
TDI
RXSER3
RTIP0
RXSERCLK3
RxSCLK3
TXSERCLK3
TXSER3
RVDD2
RGND1
TGND1
TVDD1
VDD18
VDD18
VSS
A6
VSS
TXSERCLK1
RXLOS2
TXSYNC2
TXSER2
RXSIG3
A7
RXSIG0
RXSYNC0
TXSYNC0
TXSIG0
C2
RVDD0
A8
C3
GNDPLL
VDDPLL18
VSS
A9
C4
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
B1
C5
G2
RXSERCLK1
VDD
C6
AGND
RXCASYNC3
RTIP1
G3
C7
aTEST
G4
TXSYNC1
TXSER1
VSS
C8
MCLKIN
TRST
E2
RVDD1
G5
C9
E3
TRING0
G7
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
D1
TCK
E4
TGND0
G8
RXCASYNC2
RXCRCSYNC2
RxSCLK2
VDD
RxSCLK0
RXSER1
RXSYNC1
RXCASYNC1
RXSYNC2
RXSIG2
E5
ANALOG
VDD18
G9
VDD18
VSS
E6
G10
G11
G12
G13
G15
G16
G17
G18
G19
H1
E7
VSS
VDD18
VSS
E8
VDD18
GNDPLL
VDDPLL18
VDDPLL18
DVDD18
RXTSEL
VDD
E9
VDD18
VDD18
DATA7
B2
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
RXCASYNC0
VDD18
B3
TXSERCLK2
TXMSYNC2
RXCRCSYNC3
RRING0
RGND0
TXMSYNC3
WR / R/W
TXSIG3
CS
B4
VDD18
B5
VDD18
B6
RxSCLK1
VDD18
B7
TMS
D2
RTIP2
B8
RXLOS0
VDD
D3
TTIP0
VDD
H2
RGND2
TRING2
TTIP2
B9
D4
TVDD0
RXSYNC3
RXLOS3
TXSYNC3
H3
B10
B11
B12
TXMSYNC0
TXSERCLK0
RXSIG1
D5
GNDPLL
AVDD18
H4
D6
H5
VSS
6
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
TABLE 1: 329 BALL
L
IST
TABLE 1: 329 BALL
L
IST
TABLE 1: 329 BALL
LIST
TABLE 1: 329 BALL
LIST
BY ALL UMBER
B
N
BY ALL UMBER
B
N
BY ALL UMBER
B
N
BY ALL UMBER
B
N
P
IN
P
IN
NAME
P
IN
P
IN
N
AME
P
IN
P
IN
NAME
P
IN
PIN NAME
H7
H8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K4
K5
TTIP3
M2
M3
RGND4
TGND4
TVDD4
VDD18
VSS
N19
P1
ADDR0
RTIP5
VSS
TVDD3
VSS
H9
K7
M4
P2
H10
H11
H12
H13
H15
H16
H17
H18
H19
J1
K8
VSS
M5
P3
TGND5
RVDD6
TGND6
VDD18
VDD
K9
VSS
M7
P4
K10
K11
K12
K13
K15
K16
K17
K18
K19
L1
VSS
M8
VSS
P5
VSS
M9
VSS
P15
P16
P17
P18
P19
R1
ADDR12
DATA6
ADDR14
DATA5
ADDR13
RRING2
RVDD3
TGND2
TVDD2
VDD18
VDD18
VSS
VSS
M10
M11
M12
M13
M15
M16
M17
M18
M19
N1
VSS
VSS
VSS
PTYPE0
PCLK
ADDR8
DATA2
VSS
VSS
DATA1
RRING5
RGND5
TVDD6
TRING6
TTIP6
ALE / AS
ADDR10
PTYPE2
RRING3
RVDD4
TTIP4
ADDR3
RDY / DTACK
ADDR1
ADDR2
ADDR5
RRING4
RVDD5
TTIP5
R2
J2
R3
J3
R4
J4
L2
R5
J5
L3
R6
VSS
J7
L4
TRING4
TGND3
VDD18
VSS
N2
R7
RXCRCSYNC7
TXMSYNC6
VDD18
VDD18
VDD
J8
L5
N3
R8
J9
VSS
L7
N4
TRING5
TVDD5
VDD18
VSS
R9
J10
J11
J12
J13
J15
J16
J17
J18
J19
K1
VSS
L8
N5
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
T1
VSS
L9
VSS
N7
VSS
L10
L11
L12
L13
L15
L16
L17
L18
L19
M1
VSS
N8
VDD18
VDD
VDD18
ADDR11
ADDR9
VDD
VSS
N9
VDD18
VSS
VSS
N10
N11
N12
N13
N15
N16
N17
N18
VDD18
VDD
VDD18
VDD18
ADDR4
ADDR6
DATA3
ADDR7
RTIP4
VDD18
VSS
REQ1
INT
VDD18
VSS
RXSERCLK4
VDD
DATA4
RTIP3
RGND3
TRING3
DATA0
RD / DS / WE
PTYPE1
ACK1
K2
RTIP6
K3
T2
RGND6
7
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TABLE 1: 329 BALL
L
IST
TABLE 1: 329 BALL
L
IST
TABLE 1: 329 BALL
LIST
BY ALL UMBER
B
N
BY ALL UMBER
B
N
BY ALL UMBER
B
N
P
IN
P
IN
NAME
P
IN
P
IN
N
AME
P
IN
PIN NAME
T3
T4
TTIP7
TVDD7
U16
U17
U18
U19
V1
TXMSYNC4
RXCASYNC4
RXSIG4
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
RXCASYNC6
VDD
T5
8KEXTOSC
VDD18
RXSER6
TXSIG5
RXSIG5
VDD
T6
RXLOS4
T7
VDD
VDD
T8
RXSYNC7
RXCASYNC7
RXSYNC6
TXSERCLK5
RXSERCLK6
TXMSYNC5
RxSCLK5
RXSERCLK5
TXSYNC4
RXSYNC4
ACK0
V2
TGND7
T9
V3
RGND7
RXCRCSYNC5
TXSER4
RxSCLK4
VSS
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
U1
V4
RESET
V5
E1OSCCLK
TXMSYNC7
RXLOS7
V6
V7
V8
RXSER7
TXSYNC6
RXCRCSYNC6
RXLOS6
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
W1
W2
W3
W4
W5
W6
W7
W8
W9
RXSIG6
REQ0
TXSER5
RRING6
RXSER5
RXCASYNC5
TXSIG4
U2
RVDD7
U3
TRING7
U4
VDD
TXSERCLK4
RXSER4
RXCRCSYNC4
VSS
U5
TXSERCLK7
TXSIG7
U6
U7
RXSERCLK7
RxSCLK7
RXSIG7
U8
RTIP7
U9
RRING7
U10
U11
U12
U13
U14
U15
TXSIG6
TXON
RxSCLK6
VSS
T1OSCCLK
TXSER7
TXSYNC5
RXSYNC5
RXLOS5
TXSYNC7
TXSERCLK6
TXSER6
8
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
TABLE 2: 256 BALL
L
IST
TABLE 2: 256 BALL
LIST
TABLE 2: 256 BALL
LIST
BY ALL UMBER
B
N
BY ALL UMBER
B
N
BY ALL UMBER
B
N
TABLE 2: 256 BALL
LIST
BY ALL UMBER
B
N
P
IN
P
IN
N
AME
P
IN
P
IN
NAME
P
IN
PIN NAME
P
IN
P
IN
N
AME
B16
C1
RXSER3
RRING0
RGND0
TTIP0
D16
E1
RXLOS3
RRING1
RGND1
TTIP1
F16
G1
ADDR13
RRING2
RGND2
TTIP2
TRING2
TGND2
VDD18
VSS
A1
A2
GNDPLL
GNDPLL
C2
E2
G2
A3
VDDPLL18
VDDPLL18
RxTSEL
TMS
C3
E3
G3
A4
C4
GNDPLL
AVDD18
DVDD18
aTEST
TDI
E4
TRING1
TGND0
MCLKIN
VSS
G4
A5
C5
E5
G5
A6
C6
E6
G6
A7
RXLOS0
C7
E7
G7
A8
RXCRCSYNC0
RXCASYNC0
RXSERCLK1
RXSYNC1
TXMSYNC1
RXSYNC2
TXSYNC2
RxSCLK2
VDD
C8
E8
VDD
G8
VSS
A9
C9
TXSYNC0
E9
VSS
G9
VSS
A10
A11
A12
A13
A14
A15
A16
B1
C10
C11
C12
C13
C14
C15
C16
D1
RXCRCSYNC1
RXLOS1
E10
E11
E12
E13
E14
E15
E16
F1
TXSER0
VDD
G10
G11
G12
G13
G14
G15
G16
H1
VSS
ADDR14
DATA6
DATA7
DATA5
VDD
TXSER1
RXCRCSYNC3
RXCASYNC3
TXMSYNC3
TXSYNC3
TXSERCLK3
RTIP2
RXSERCLK2
RXCRCSYNC2
TXMSYNC2
RXSYNC3
RTIP1
ADDR12
RTIP3
RVDD3
TTIP3
TRING3
TVDD3
VDD18
VSS
RTIP0
B2
RVDD0
D2
RVDD1
F2
RVDD2
H2
B3
VDDPLL18
ANALOG
AGND
D3
TRING0
F3
TGND1
H3
B4
D4
TVDD0
F4
TVDD1
H4
B5
D5
VDDPLL18
DGND
F5
TVDD2
H5
B6
TDO
D6
F6
VSS
H6
B7
RXSER0
D7
TRST
F7
VSS
H7
B8
RXSERCLK0
RXSYNC0
RxSCLK0
RXSER1
D8
TCK
F8
VDD18
H8
VSS
B9
D9
TXMSYNC0
TXSERCLK0
RXCASYNC1
RxSCLK1
RXCASYNC2
TXSER2
F9
VDD18
H9
VSS
B10
B11
B12
B13
B14
B15
D10
D11
D12
D13
D14
D15
F10
F11
F12
F13
F14
F15
VDD18
H10
H11
H12
H13
H14
H15
VSS
RXLOS2
RxSCLK3
WR / R/W
CS
VDD18
PTYPE2
DATA4
ADDR10
INT
TXSYNC1
TXSERCLK1
RXSER2
TXSERCLK2
RXSERCLK3
TXSER3
9
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TABLE 2: 256 BALL
L
IST
TABLE 2: 256 BALL
L
IST
TABLE 2: 256 BALL
LIST
TABLE 2: 256 BALL
LIST
BY ALL UMBER
B
N
BY ALL UMBER
B
N
BY ALL UMBER
B
N
BY ALL UMBER
B
N
P
IN
P
IN
NAME
P
IN
P
IN
N
AME
P
IN
P
IN
NAME
P
IN
PIN NAME
H16
J1
ADDR11
RRING3
RGND3
TTIP4
K16
L1
ADDR5
M16
N1
PCLK
P16
R1
RXLOS4
RRING6
RGND6
RGND7
RESET
RRING4
RGND4
TTIP5
RRING5
RGND5
TGND6
TVDD7
TGND7
J2
L2
N2
R2
J3
L3
N3
R3
J4
TRING4
TGND3
VDD18
VSS
L4
TRING5
TGND5
N4
R4
J5
L5
N5
R5
E1OSCCLK
RXSERCLK7
RXSYNC7
TXMSYNC6
RXCRCSYNC6
RXLOS6
J6
L6
8KEXTOSC
VDD18
N6
TXMSYNC7
RXCRCSYNC7
TXSYNC6
RXCASYNC6
TXSERCLK5
RXSYNC5
TXSER4
R6
J7
L7
N7
R7
J8
VSS
L8
VDD18
N8
R8
J9
VSS
L9
VDD18
N9
R9
J10
J11
J12
J13
J14
J15
J16
K1
VSS
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
VDD18
N10
N11
N12
N13
N14
N15
N16
P1
R10
R11
R12
R13
R14
R15
R16
T1
VDD18
DATA3
ADDR9
ADDR8
ADDR7
ALE / AS
RTIP4
RVDD4
TGND4
TVDD4
TVDD5
VDD18
VSS
ADDR3
TXMSYNC5
RXCASYNC5
RXCRCSYNC5
RXCASYNC4
RXCRCSYNC4
REQ1
DATA1
ADDR0
RXSYNC4
VDD
ADDR1
RD / DS / WE
RDY / DTACK
RTIP5
ACK0
REQ0
RTIP6
RVDD7
K2
RVDD5
P2
RVDD6
T2
RTIP7
K3
TTIP6
P3
TTIP7
T3
RRING7
K4
TRING6
TVDD6
P4
TRING7
T4
TXON
K5
P5
TXSER7
T5
T1OSCCLK
TXSYNC7
TXSERCLK6
TXSER6
K6
VDD
P6
TXSERCLK7
RXLOS7
RXSER7
RxSCLK6
TXSER5
T6
K7
RxSCLK7
RXCASYNC7
VDD
P7
T7
K8
VSS
P8
T8
K9
VSS
P9
T9
RXSYNC6
RXSER6
K10
K11
K12
K13
K14
K15
VSS
RXSERCLK6
TXSYNC5
PTYPE1
PTYPE0
DATA0
P10
P11
P12
P13
P14
P15
T10
T11
T12
T13
T14
T15
VDD18
DATA2
ADDR4
ADDR6
ADDR2
RXSER5
RXLOS5
TXMSYNC4
RXSERCLK4
RXSER4
RxSCLK5
RXSERCLK5
TXSYNC4
TXSERCLK4
RxSCLK4
ACK1
10
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
TABLE 2: 256 BALL
LIST
BY ALL UMBER
B
N
P
IN
PIN NAME
T16
VDD
11
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
2.0 PIN DESCRIPTIONS
There are six types of pins defined throughout this pin description and the corresponding symbol is presented
in table below. The per-channel pin is indicated by the channel number or the letter ’n’ which is appended at the
end of the signal name, for example, TxSERn, where "n" indicates channels 0 to 7. All output pins are "tri-
stated" upon hardware RESET.
S
YMBOL
I
PIN TYPE
Input
O
Output
Bidirectional
Ground
I/O
GND
PWR
NC
Power
No Connect
The structure of the pin description is divided into eleven groups, as presented in the table below
TABLE 3: PIN
D
ESCRIPTION
STRUCTURE
S
ECTION
P
AGE UMBER
N
Transmit System Side Inter-
face
page 13
Receive System Side Inter-
face
page 18
Receive Line Interface
Transmit Line Interface
Timing Interface
page 23
page 24
page 25
page 26
page 26
page 35
page 36
page 37
page 38
JTAG Interface
Microprocessor Interface
Power Pins (3.3V)
Power Pins (1.8V)
Ground Pins
No Connect Pins
12
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
TRANSMIT SYSTEM SIDE INTERFACE
329 PKG 256 PKG
OUTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
BALL
#
BALL
#
DRIVE(MA)
TxSER0/
TxPOS0
TxSER1/
TxPOS1
TxSER2/
TxPOS2
TxSER3/
TxPOS3
TxSER4/
TxPOS4
TxSER5/
TxPOS5
TxSER6/
TxPOS6
TxSER7/
TxPOS7
D11
A14
E10
C12
D14
F15
N12
P10
T8
I
-
Transmit Serial Data Input (TxSERn)/Transmit Positive
Digital Input (TxPOSn):
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Mode - TxSERn
D17
F19
W17
V13
W9
These pins function as the transmit serial data input on the
system side interface, which are latched on the rising edge of
the TxSERCLKn pin. Any payload data applied to this pin will
be inserted into an outbound DS1/E1 frame and output to the
line. In DS1 mode, the framing alignment bits, facility data link
bits, CRC-6 bits, and signaling information can also be
inserted from this input pin if configured appropriately. In E1
mode, all data intended to be transported via Time Slots 1
through 15 and Time slots 17 through 31 must be applied to
this input pin. Data intended for Time Slots 0 and 16 can also
be applied to this input pin If configured accordingly.
W6
P5
DS1 or E1 High-Speed Multiplexed Mode* - TxSERn
In this mode, these pins are used as the high-speed multi-
plexed data input pin on the system side. High-speed multi-
plexed data of channels 0-3 must be applied to TxSER0 and
high-speed multiplexed data of channels 4-7 must be applied
to TxSER4 in a byte or bit-interleaved way. The framer latches
in the multiplexed data on TxSER0 and TxSER4 using TxM-
SYNC/TxINCLK and demultiplexes this data into 4 serial
streams. The LIU block will then output the data to the line
interface using TxSERCLKn.
DS1 or E1 Framer Bypass Mode - TxPOSn
In this mode, TxSERn is used for the positive digital input pin
(TxPOSn) to the LIU.
NOTE:
1. *High-speed multiplexed modes include (For T1/E1)
16.384MHz HMVIP, H.100, Bit-multiplexed modes,
and (For T1 only) 12.352MHz Bit-multiplexed mode.
2. In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
3. These 8 pins are internally pulled “High” for each
channel.
13
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT SYSTEM SIDE INTERFACE
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
BALL
#
BALL
#
DRIVE(MA)
TxSERCLK0/
TxLINECLK0
TxSERCLK1/
TxLINECLK1
TxSERCLK2/
TxLINECLK2
TxSERCLK3/
TxLINECLK3
TxSERCLK4/
TxLINECLK4
TxSERCLK5/
TxLINECLK5
TxSERCLK6/
TxLINECLK6
TxSERCLK7/
TxLINECLK7
B11
D10
B13
B15
E16
T14
N10
T7
I/O
12
Transmit Serial Clock (TxSERCLKn)/Transmit Line Clock
(TxSERCLKn):
The exact function of these pins depends on the mode of
operation selected, as described below.
D14
C17
F18
V17
T11
W8
In Base-Rate Mode (1.544MHz/2.048MHz) - TxSERCLKn:
This clock signal is used by the transmit serial interface to
latch the contents on the TxSERn pins into the T1/E1 framer
on the rising edge of the TxSERCLKn. These pins can be con-
figured as input or output as described below.
When TxSERCLKn is configured as Input:
These pins will be inputs if the TxSERCLK is chosen as the
timing source for the transmit framer. Users must provide a
1.544MHz clock rate to this input pin for T1 mode of operation,
and 2.048MHz clock rate in E1 mode.
When TxSERCLKn is configured as Output:
These pins will be outputs if either the recovered line clock or
the MCLK PLL is chosen as the timing source for the T1/E1
transmit framer. The transmit framer will output a 1.544MHz
clock rate in T1 mode of operation, and a 2.048MHz clock rate
in E1 mode.
U5
P6
DS1/E1 High-Speed Backplane Modes* - TxSERCLKn as
INPUT ONLY
In this mode, TxSERCLK is an optional clock signal input
which is used as the timing source for the transmit line inter-
face, and is only required if TxSERCLK is chosen as the tim-
ing source for the transmit framer. If TxSERCLK is chosen as
the timing source, system equipment should provide
1.544MHz (For T1 mode) or 2.048MHz (For E1 mode) to the
TxSERCLKn pins on each channel. TxSERCLK is not
required if either the recovered clock or MCLK PLL is chosen
as the timing source of the device.
High speed or multiplexed data is latched into the device using
the TxMSYNC/TxINCLK high-speed clock signal.
DS1 or E1 Framer Bypass Mode - TxLINECLKn
In this mode, TxSERCLKn is used as the transmit line clock
(TxLINECLK) to the LIU.
NOTE
:
*High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
N
OTE: In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
NOTE
:
These 8 pins are internally pulled “High” for each
channel.
14
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT SYSTEM SIDE INTERFACE
REV. 1.0.2
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
BALL
#
BALL
#
DRIVE(MA)
TxSYNC0/
TxNEG0
A9
C9
I/O
12
Transmit Single Frame Sync Pulse (TxSYNCn) / Transmit
Negative Digital Input (TxNEGn):
The exact function of these pins depends on the mode of
operation selected, as described below.
TxSYNC1/
TxNEG1
A13
B12
A14
E15
T13
M11
N8
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - TxSYNCn:
TxSYNC2/
TxNEG2
D16
E19
T16
U13
V9
These TxSYNCn pins are used to indicate the single frame
boundary within an outbound T1/E1 frame. In both DS1 or E1
mode, the single frame boundary repeats every 125 microsec-
onds (8kHz).
TxSYNC3/
TxNEG3
TxSYNC4/
TxNEG4
In DS1/E1 base rate, TxSYNCn can be configured as either
input or output as described below.
TxSYNC5/
TxNEG5
When TxSYNCn is configured as an Input:
Users must provide a signal which must pulse "High" for one
period of TxSERCLK during the first bit of an outbound DS1/
E1 frame. It is imperative that the TxSYNC input signal be syn-
chronized with the TxSERCLK input signal.
TxSYNC6/
TxNEG6
TxSYNC7/
TxNEG7
W7
T6
When TxSYNCn is configured as an Output:
The transmit T1/E1 framer will output a signal which pulses
"High" for one period of TxSERCLK during the first bit of an
outbound DS1/E1 frame.
DS1/E1 High-Speed Backplane Modes* - TxSYNCn as
INPUT ONLY:
In this mode, TxSYNCn must be an input regardless of the
clock source that is chosen to be the timing source for the
transmit framer. In 2.048MVIP/4.096/8.192MHz high-speed
modes, TxSYNCn pins must be pulsed ’High’ for one period of
TxSERCLK during the first bit of the outbound T1/E1 frame. In
HMVIP mode, TxSYNC0 and TxSYNC4 must be pulsed ’High’
for 4 clock cycles of the TxMSYNC/TxINCLK signal in the
position of the first two and the last two bits of a multiplexed
frame. In H.100 mode, TxSYNC0 and TxSYNC4 must be
pulsed ’High’ for 2 clock cycles of the TxMSYNC/TxINCLK sig-
nal in the position of the first and the last bit of a multiplexed
frame.
DS1 or E1 Framer Bypass Mode - TxNEGn
In this mode, TxSYNCn is used as the negative digital input
pin (TxNEG) to the LIU.
NOTE
:
*High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
N
OTE: In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
NOTE
:
These 8 pins are internally pulled “Low” for each
channel.
15
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT SYSTEM SIDE INTERFACE
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
BALL
#
BALL
#
DRIVE(MA)
TxMSYNC0/
TxINCLK0
B10
B14
C18
G16
U16
T13
R8
D9
I/O
12
Multiframe Sync Pulse (TxMSYNCn) / Transmit Input
Clock (TxINCLKn)
The exact function of these pins depends on the mode of
operation selected, as described below.
TxMSYNC1/
TxINCLK1
A12
C15
E14
P13
R11
R8
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - TxM-
SYNCn
TxMSYNC2/
TxINCLK2
In this mode, these pins are used to indicate the multi-frame
boundary within an outbound DS1/E1 frame.
TxMSYNC3/
TxINCLK3
In DS1 ESF mode, TxMSYNCn repeats every 3ms.
In DS1 SF mode, TxMSYNCn repeats every 1.5ms.
In E1 mode, TxMSYNCn repeats every 2ms.
TxMSYNC4/
TxINCLK4
TxMSYNC5/
TxINCLK5
If TxMSYNCn is configured as an input, TxMSYNCn must
pulse "High" for one period of TxSERCLK during the first bit of
an outbound DS1/E1 multi-frame. It is imperative that the
TxMSYNC input signal be synchronized with the TxSERCLK
input signal.
TxMSYNC6/
TxINCLK6
TxMSYNC7/
TxINCLK7
V6
N6
If TxMSYNCn is configured as an output, the transmit section
of the T1/E1 framer will output and pulse TxMSYNC "High" for
one period of TxSERCLK during the first bit of an outbound
DS1/E1 frame.
DS1/E1 High-Speed Backplane Modes* - (TxINCLKn as
INPUT ONLY)
In this mode, this pin must be used as the high-speed input
clock pin (TxINCLKn) for the backplane interface to latch in
high-speed or multiplexed data on the TxSERn pin. The fre-
quency of TxINCLK is presented in the table below.
F
REQUENCY OF
OPERATION MODE
T
X
INCLK(MH
Z)
2.048MVIP non-multiplexed
4.096MHz non-multiplexed
8.192MHz non-multiplexed
2.048
4.096
8.192
12.352MHz Bit-multiplexed
(DS1 ONLY)
12.352
16.384MHz Bit-multiplexed
16.384 HMVIP Byte-multiplexed
16.384 H.100 Byte-multiplexed
16.384
16.384
16.384
NOTES:
1. *High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
2. In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
3. These 8 pins are internally pulled “Low” for each
channel.
16
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT SYSTEM SIDE INTERFACE
REV. 1.0.2
329 PKG 256 PKG
OUTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
BALL
#
BALL
#
DRIVE(MA)
TxSIG0
TxSIG1
TxSIG2
TxSIG3
TxSIG4
TxSIG5
TxSIG6
TxSIG7
A10
B15
B18
I/O
8
Transmit Time Slot Octet Identifier Output 0 (TxCHNn_0) /
Transmit Serial Signaling Input (TxSIGn):
The exact function of these pins depends on whether or not
the transmit framer enables the transmit fractional/signaling
interface, as described below:
G18
V16
W13
U10
U6
If transmit fractional/signaling interface is disabled -
- No function
If transmit fractional/signaling interface is enabled -
TxSIGn:
These pins can be used to input robbed-bit signaling data to
be inserted within an outbound DS1 frame or to input Channel
Associated Signaling (CAS) data within an outbound E1
frame, as described below.
T1 Mode: Signaling data (A,B,C,D) of each channel must be
provided on bit 4,5,6,7 of each time slot on the TxSIG pin if 16-
code signaling is used. If 4-code signaling is selected, signal-
ing data (A,B) of each channel must be provided on bit 4, 5 of
each time slot on the TxSIG pin. If 2-code signaling is
selected, signaling data (A) of each channel must be provided
on bit 4 of each time slot on the TxSIG pin.
E1 Mode: Signaling data in E1 mode can be provided on the
TxSIGn pins on a time-slot-basis as in T1 mode, or it can be
provided on time slot 16 only via the TxSIGn input pins. In the
latter case, signaling data (A,B,C,D) of channel 1 and channel
17 must be inserted on the TxSIGn pin during time slot 16 of
frame 1, signaling data (A,B,C,D) of channel 2 and channel 18
must be inserted on the TxSIGn pin during time slot 16 of
frame 2...etc. The CAS multiframe Alignments bits (0000 bits)
and the extra bits/alarm bit (xyxx) must be inserted on the
TxSIGn pin during time slot 16 of frame 0.
NOTE
:
Transmit fractional interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
NOTE
:
These 8 pins are internally pulled “Low” for each
channel.
17
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RECEIVE SYSTEM SIDE INTERFACE
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
BALL
#
BALL #
RxSYNC0/
RxNEG0
A8
B9
I/O
12
Receive Single Frame Sync Pulse (RxSYNCn):
The exact function of these pins depends on the mode of
operation selected, as described below.
RxSYNC1/
RxNEG1
C13
C15
E17
T17
U14
T10
T8
A11
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) -
RxSYNCn:
RxSYNC2/
RxNEG2
A13
C16
N13
N11
T9
These RxSYNCn pins are used to indicate the single
frame boundary within an inbound T1/E1 frame. In both
DS1 or E1 mode, the single frame boundary repeats
every 125 microseconds (8kHz).
RxSYNC3/
RxNEG3
RxSYNC4/
RxNEG4
In DS1/E1 base rate, RxSYNCn can be configured as
either input or output depending on the slip buffer configu-
ration as described below.
RxSYNC5/
RxNEG5
When RxSYNCn is configured as an Input:
Users must provide a signal which must pulse "High" for
one period of RxSERCLK and repeats every 125µS. The
receive serial Interface will output the first bit of an
inbound DS1/E1 frame during the provided RxSYNC
pulse.
RxSYNC6/
RxNEG6
RxSYNC7/
RxNEG7
R7
NOTE: It is imperative that the RxSYNC input signal be
synchronized with the RxSERCLK input signal.
When RxSYNCn is configured as an Output:
The receive T1/E1 framer will output a signal which
pulses "High" for one period of RxSERCLK during the first
bit of an inbound DS1/E1 frame.
DS1/E1 High-Speed Backplane Modes* - RxSYNCn as
INPUT ONLY:
In this mode, RxSYNCn must be an input regardless of
the slip buffer configuration. In 2.048MVIP/4.096/
8.192MHz high-speed modes, RxSYNCn pins must be
pulsed ’High’ for one period of RxSERCLK during the first
bit of the inbound T1/E1 frame. In HMVIP mode,
RxSYNCn must be pulsed ’High’ for 4 clock cycles of the
RxSERCLK signal in the position of the first two and the
last two bits of a multiplexed frame. In H.100 mode,
RxSYNCn must be pulsed ’High’ for 2 clock cycles of the
RxSERCLK signal in the position of the first and the last
bit of a multiplexed frame.
DS1 or E1 Framer Bypass Mode - RxNEGn
In this mode, RxSYNCn is used as the Receive negative
digital output pin (RxNEG) from the LIU.
N
OTE
:
:
*High-speed backplane modes include (For T1/
E1) 2.048MVIP, 4.096MHz, 8.192MHz,
16.384MHz HMVIP, H.100, Bit-multiplexed
modes, and (For T1 only) 12.352MHz Bit-
multiplexed mode.
N
N
OTE
In DS1 high-speed modes, the DS-0 data is
mapped into an E1 frame by ignoring every fourth
time slot (don’t care).
OTE: These 8 pins are internally pulled “Low” for each
channel.
18
XRT86VX38
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RECEIVE SYSTEM SIDE INTERFACE
REV. 1.0.2
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
BALL
#
BALL #
RxCRCSYNC0
RxCRCSYNC1
RxCRCSYNC2
RxCRCSYNC3
RxCRCSYNC4
RxCRCSYNC5
RxCRCSYNC6
RxCRCSYNC7
D10
D12
A17
C19
V19
W16
V10
R7
A8
O
12
Receive Multiframe Sync Pulse (RxCRCSYNCn):
C10
C14
E12
R15
R13
R9
The RxCRCSYNCn pins are used to indicate the receive
multi-frame boundary. These pins pulse "High" for one
period of RxSERCLK when the first bit of an inbound
DS1/E1 Multi-frame is being output on the RxCRCSYNCn
pin.
•
•
•
In DS1 ESF mode, RxCRCSYNCn repeats every 3ms
In DS1 SF mode, RxCRCSYNCn repeats every 1.5ms
In E1 mode, RxCRCSYNCn repeats every 2ms.
N7
RxCASYNC0
RxCASYNC1
RxCASYNC2
RxCASYNC3
RxCASYNC4
RxCASYNC5
RxCASYNC6
RxCASYNC7
E10
C14
A16
D19
U17
V15
W10
T9
A9
D11
D13
E13
R14
R12
N9
O
12
Receive CAS Multiframe Sync Pulse (RxCASYNCn):
- E1 Mode Only
The RxCASYNCn pins are used to indicate the E1 CAS
Multif-frame boundary. These pins pulse "High" for one
period of RxSERCLK when the first bit of an E1 CAS
Multi-frame is being output on the RxCASYNCn pin.
M8
19
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REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE SYSTEM SIDE INTERFACE
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
BALL
#
BALL #
RxSERCLK0/
RxLINECLK0
RxSERCLK1/
RxLINECLK1
RxSERCLK2/
RxLINECLK2
RxSERCLK3/
RxLINECLK3
RxSERCLK4/
RxLINECLK4
RxSERCLK5/
RxLINECLK5
RxSERCLK6/
RxLINECLK6
RxSERCLK7/
RxLINECLK7
D9
B8
I/O
12
Receive Serial Clock Signal (RxSERCLKn) / Receive
Line Clock (RxLINECLKn):
The exact function of these pins depends on the mode of
operation selected, as described below.
A11
A10
C13
D15
P14
T12
M10
R6
In Base-Rate Mode (1.544MHz/2.048MHz) - RxSER-
CLKn:
B16
F16
R17
T15
T12
U7
These pins are used as the receive serial clock on the
system side interface which can be configured as either
input or output. The receive serial interface outputs data
on RxSERn on the rising edge of RxSERCLKn.
When RxSERCLKn is configured as Input:
These pins will be inputs if the slip buffer on the Receive
path is enabled. System side equipment must provide a
1.544MHz clock rate to this input pin for T1 mode of oper-
ation, and 2.048MHz clock rate in E1 mode.
When RxSERCLKn is configured as Output:
These pins will be outputs if slip buffer is bypassed. The
receive framer will output a 1.544MHz clock rate in T1
mode of operation, and a 2.048MHz clock rate in E1
mode.
DS1/E1 High-Speed Backplane Modes* - (RxSERCLK
as INPUT ONLY)
In this mode, this pin must be used as the high-speed
input clock for the backplane interface to output high-
speed or multiplexed data on the RxSERn pin. The fre-
quency of RxSERCLK is presented in the table below.
F
REQUENCY OF
OPERATION MODE
R
X
SERCLK(MH
Z)
2.048MVIP non-multiplexed
4.096MHz non-multiplexed
8.192MHz non-multiplexed
2.048
4.096
8.192
12.352MHz Bit-multiplexed
(DS1 ONLY)
12.352
16.384MHz Bit-multiplexed
16.384 HMVIP Byte-multiplexed
16.384 H.100 Byte-multiplexed
16.384
16.384
16.384
NOTES:
1. *High-speed backplane modes include (For T1/
E1) 2.048MVIP, 4.096MHz, 8.192MHz,
16.384MHz HMVIP, H.100, Bit-multiplexed
modes, and (For T1 only) 12.352MHz Bit-
multiplexed mode.
2. For DS1 high-speed modes, the DS-0 data is
mapped into an E1 frame by ignoring every
fourth time slot (don’t care).
20
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OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE SYSTEM SIDE INTERFACE
REV. 1.0.2
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
BALL
#
BALL #
RxSERCLK0/
RxLINECLK0
RxSERCLK1/
RxLINECLK1
RxSERCLK2/
RxLINECLK2
RxSERCLK3/
RxLINECLK3
RxSERCLK4/
RxLINECLK4
RxSERCLK5/
RxLINECLK5
RxSERCLK6/
RxLINECLK6
RxSERCLK7/
RxLINECLK7
D9
B8
I/O
12
(Continued)
DS1 or E1 Framer Bypass Mode - RxLINECLKn
A11
A10
C13
D15
P14
T12
M10
R6
In this mode, RxSERCLKn is used as the Receive Line
Clock output pin (RxLineClk) from the LIU.
B16
F16
R17
T15
T12
U7
NOTE: These 8 pins are internally pulled “High” for each
channel.
RxSER0/
RxPOS0
RxSER1/
RxPOS1
RxSER2/
RxPOS2
RxSER3/
RxPOS3
RxSER4/
RxPOS4
RxSER5/
RxPOS5
RxSER6/
RxPOS6
RxSER7/
RxPOS7
D8
C12
B17
B19
V18
V14
W12
V8
B7
O
12
Receive Serial Data Output (RxSERn):
The exact function of these pins depends on the mode of
operation selected, as described below.
B11
B14
B16
P15
P11
T10
P8
DS1/E1 Mode - RxSERn
These pins function as the receive serial data output on
the system side interface, which are updated on the rising
edge of the RxSERCLKn pin. All the framing alignment
bits, facility data link bits, CRC bits, and signaling informa-
tion will also be extracted to this output pin.
DS1 or E1 High-Speed Multiplexed Mode* - RxSERn
In this mode, these pins are used as the high-speed multi-
plexed data output pin on the system side. High-speed
multiplexed data of channels 0-3 will output on RxSER0
and high-speed multiplexed data of channels 4-7 will out-
put on RxSER4 in a byte or bit-interleaved way. The
framer outputs the multiplexed data on RxSER0 and
RxSER4 using the high-speed input clock (RxSERCLKn).
DS1 or E1 Framer Bypass Mode
In this mode, RxSERn is used as the positive digital out-
put pin (RxPOSn) from the LIU.
N
OTE: *High-speed multiplexed modes include (For T1/
E1) 16.384MHz HMVIP, H.100, Bit-multiplexed
modes, and (For T1 only) 12.352MHz Bit-
multiplexed mode.
NOTE
:
In DS1 high-speed modes, the DS-0 data is
mapped into an E1 frame by ignoring every fourth
time slot (don’t care).
21
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RECEIVE SYSTEM SIDE INTERFACE
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
BALL
#
BALL #
RxSig0
RxSig1
RxSig2
RxSig3
RxSig4
RxSig5
RxSig6
RxSig7
A7
O
8
Receive Serial Signaling Output (RxSIGn):
B12
C16
D18
U18
W14
V12
U9
The exact function of these pins depends on whether or
not the receive framer enables the receive fractional/sig-
naling interface, as described below:
If receive fractional/signaling interface is disabled :
-No function
If receive fractional/signaling interface is enabled -
RxSIGn:
These pins can be used to output robbed-bit signaling
data within an inbound DS1 frame or to output Channel
Associated Signaling (CAS) data within an inbound E1
frame, as described below.
T1 Mode: Signaling data (A,B,C,D) of each channel will
be output on bit 4,5,6,7 of each time slot on the RxSIG pin
if 16-code signaling is used. If 4-code signaling is
selected, signaling data (A,B) of each channel will be out-
put on bit 4, 5 of each time slot on the RxSIG pin. If 2-
code signaling is selected, signaling data (A) of each
channel will be output on bit 4 of each time slot on the
RxSIG pin.
E1 Mode: Signaling data in E1 mode will be output on the
RxSIGn pins on a time-slot-basis as in T1 mode, or it can
be output on time slot 16 only via the RxSIGn output pins.
In the latter case, signaling data (A,B,C,D) of channel 1
and channel 17 will be output on the RxSIGn pin during
time slot 16 of frame 1, signaling data (A,B,C,D) of chan-
nel 2 and channel 18 will be output on the RxSIGn pin
during time slot 16 of frame 2...etc. The CAS multiframe
Alignments bits (0000 bits) and the extra bits/alarm bit
(xyxx) will be output on the RxSIGn pin during time slot 16
of frame 0.
NOTE
:
Receive Fractional/signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from register 0xn122 to ‘1’.
RxSCLK0
RxSCLK1
RxSCLK2
RxSCLK3
RxSCLK4
RxSCLK5
RxSCLK6
RxSCLK7
C11
E14
A18
F17
W18
T14
U11
U8
B10
D12
A15
F12
T15
T11
P9
O
8
Receive Recovered Line Clock Output (RxSCLKn):
The exact function of these pins depends on whether or
not the receive framer enables the receive fractional/sig-
naling interface, as described below:
If receive fractional/signaling interface is disabled -
-No function
If receive fractional/signaling interface is enabled -
Receive Recovered Line Clock Output (RxSCLKn):
M7
These pins output the recovered T1/E1 line clock
(1.544MHz in T1 mode and 2.048MHz in E1 mode) for
each channel.
NOTE
:
Receive Fractional/Signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from register 0xn122 to ‘1’.
22
XRT86VX38
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REV. 1.0.2
RECEIVE LINE INTERFACE
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
BALL
#
BALL #
RTIP0
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
RTIP6
RTIP7
C1
E1
H1
K1
M1
P1
T1
B1
D1
F1
H1
K1
M1
P1
T2
I
-
Receive Positive Analog Input (RTIPn):
RTIP is the positive differential input from the line inter-
face. This input pin, along with the RRING input pin, func-
tions as the “Receive DS1/E1 Line Signal” input for the
XRT86VX38 device.
The user is expected to connect this signal and the
RRING input signal to a 1:1 transformer for proper opera-
tion. The center tap of the receive transformer should have
a bypass capacitor of 0.1µF to ground (Chip Side) to
improve long haul application receive capabilities.
W2
RRING0
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
D1
F1
J1
C1
E1
G1
J1
I
-
Receive Negative Analog Input (RRINGn):
RRING is the negative differential input from the line inter-
face. This input pin, along with the RTIP input pin, func-
tions as the “Receive DS1/E1 Line Signal” input for the
XRT86VX38 device.
L1
N1
R1
U1
W3
L1
The user is expected to connect this signal and the RTIP
input signal to a 1:1 transformer for proper operation. The
center tap of the receive transformer should have a
bypass capacitor of 0.1µF to ground (Chip Side) to
improve long haul application receive capabilities.
N1
R1
T3
RxLOS0
RxLOS1
RxLOS2
RxLOS3
RxLOS4
RxLOS5
RxLOS6
RxLOS7
B8
A7
O
4
Receive Loss of Signal Output Indicator (RLOSn):
B13
D15
E18
U19
U15
V11
V7
C11
F11
D16
P16
P12
R10
P7
The XRT86VX38 device will assert this output pin (i.e.,
toggle it “high”) anytime (and for the duration that) the
Receive DS1/E1 Framer or LIU block declares the LOS
defect condition.
Conversely, the XRT86VX38 will "TRI-State" this pin any-
time (and for the duration that) the Receive DS1/E1
Framer or LIU block is NOT declaring the LOS defect con-
dition.
NOTE
:
Since the XRT86VX38 tri-states this output pin
(anytime the channel is not declaring the LOS
defect condition), the user MUST connect a "pull-
down" resistor (ranging from 1K to 10K) to each
RxLOS output pin, to pull this output pin to the
logic "LOW" condition, whenever the Channel is
NOT declaring the LOS defect condition.
This output pin will toggle “High” (declare LOS) if the
Receive Framer or the Receive LIU block associated with
Channel N determines that an RLOS condition occurs. In
other words, this pin is OR-ed with the LIU RLOS and the
Framer RLOS bit. If either the LIU RLOS or the Framer
RLOS bit associated with channel N pulses high, the cor-
responding RLOS pin of that particular channel will be set
to “High”.
23
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REV. 1.0.2
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RECEIVE LINE INTERFACE
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
BALL
#
BALL #
RxTSEL
B5
A5
I
-
Receive Termination Control (RxTSEL):
Upon power up, the receivers are in "High" impedance.
Switching to internal termination can be selected through
the microprocessor interface by programming the appro-
priate channel register. However, to switch control to the
hardware pin, RxTCNTL must be programmed to "1" in the
appropriate global register (0x0FE2). Once control has
been granted to the hardware pin, it must be pulled "High"
to switch to internal termination.
NOTE: Internally pulled "Low" with a 50kΩ resistor.
RxTSEL (pin)
Rx Termination
External
0
1
Internal
Note: RxTCNTL (bit) must be set to "1"
TRANSMIT LINE INTERFACE
329 PKG 256 PKG
S
IGNAL
NAME
TYPE
DESCRIPTION
BALL
#
BALL #
TTIP0
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
TTIP6
TTIP7
D3
F3
H4
K4
L3
N3
R5
T3
C3
E3
G3
H3
J3
O
Transmit Positive Analog Output (TTIPn):
TTIP is the positive differential output to the line interface. This out-
put pin, along with the corresponding TRING output pin, function as
the Transmit DS1/E1 output signal drivers for the XRT86VX38
device.
The user is expected to connect this signal and the corresponding
TRING output signal to a 1:2 step up transformer for proper opera-
tion.
L3
M3
P3
This output pin will be tri-stated whenever the user sets the “TxON”
input pin or register bit (0xnF02, bit 3) to “0”.
NOTE: This pin should have a series line capacitor of 0.68µF for DC
blocking purposes.
TRING0
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
E3
F4
H3
K3
L4
D3
E4
G4
H4
J4
O
Transmit Negative Analog Output (TRINGn):
TRING is the negative differential output to the line interface. This
output pin, along with the corresponding TTIP output pin, function as
the Transmit DS1/E1 output signal drivers for the XRT86VX38
device.
The user is expected to connect this signal and the corresponding
TRING output signal to a 1:2 step up transformer for proper opera-
tion.
N4
R4
U3
L4
M4
P4
NOTE: This output pin will be tri-stated whenever the user sets the
“TxON” input pin or register bit (0xnF02, bit 3) to “0”.
24
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT LINE INTERFACE
REV. 1.0.2
329 PKG 256 PKG
S
IGNAL
NAME
TYPE
DESCRIPTION
BALL
#
BALL #
TxON
W4
T4
I
Transmitter On
This input pin permits the user to either enable or disable the Trans-
mit Output Driver within the Transmit DS1/E1 LIU Block. If the TxON
pin is pulled “Low”, all 8 Channels are tri-stated. When this pin is
pulled ‘High’, turning on or off the transmitters will be determined by
the appropriate channel registers (address 0x0Fn2, bit 3)
LOW = Disables the Transmit Output Driver within the Transmit DS1/
E1 LIU Block. In this setting, the TTIP and TRING output pins of all 8
channels will be tri-stated.
HIGH = Enables the Transmit Output Driver within the Transmit DS1/
E1 LIU Block. In this setting, the corresponding TTIP and TRING out-
put pins will be enabled or disabled by programming the appropriate
channel register. (address 0x0Fn2, bit 3)
NOTE
:
Whenever the transmitters are turned off, the TTIP and
TRING output pins will be tri-stated.
TIMING INTERFACE
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
BALL
#
BALL #
MCLKIN
C8
E6
I
-
Master Clock Input:
This pin is used to provide the timing reference for the inter-
nal master clock of the device. The frequency of this clock
is programmable from 8kHz to 16.384MHz in register
0x0FE9.
E1OSCCLK
T1OSCCLK
8KEXTOSC
V5
R5
T5
L6
O
O
I
8
8
-
Framer E1 Output Clock Reference
This output pin is defaulted to 2.048MHz, but can be pro-
grammed to 65.536MHz in register 0x011E.
W5
T5
Framer T1 Output Clock Reference
This output pin is defaulted to 1.544MHz, but can be pro-
grammed to output 49.408MHz in register 0x011E.
External Oscillator Select
For normal operation, this pin should not be used, or pulled
“Low”.
This pin is internally pulled “Low” with a 50kΩ resistor.
ANALOG
E5
B4
O
Factory Test Mode Pin
NOTE: For Internal Use Only
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REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
JTAG INTERFACE
The XRT86VX38 device’s JTAG features comply with the IEEE 1149.1 standard. Please refer to the industry
specification for additional information on boundary scan operations.
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
BALL
#
BALL #
TCK
C10
D8
I
I
-
Test clock: Boundary Scan Test clock input:
The TCLK signal is the clock for the TAP controller, and it
generates the boundary scan data register clocking. The
data on TMS and TDI is loaded on the positive edge of
TCK. Data is observed at TDO on the falling edge of TCK.
TMS
B7
A6
C8
-
-
Test Mode Select: Boundary Scan Test Mode Select
input.
The TMS signal controls the transitions of the TAP con-
troller in conjunction with the rising edge of the test clock
(TCK).
NOTE: This pin is internally pulled ’high’
TDI
A5
I
Test Data In: Boundary Scan Test data input
The TDI signal is the serial test data input.
NOTE: This pin is internally pulled ’high’.
TDO
D7
C9
B6
D7
O
I
8
-
Test Data Out: Boundary Scan Test data output
The TDO signal is the serial test data output.
TRST
Test Reset Input:
The TRST signal (Active Low) asynchronously resets the
TAP controller to the Test-Logic-Reset state.
NOTE
:
This pin is internally pulled ’high’
aTEST
C7
C7
I
-
Factory Test Mode Pin
NOTE
:
This pin is internally pulled ’low’, and should be
pulled ’low’ for normal operation.
MICROPROCESSOR INTERFACE
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
BALL
#
BALL #
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
N16
P19
K16
L18
J19
M14
L12
K12
J12
I/O
8
Bidirectional Microprocessor Data Bus
These pins are used to drive and receive data over the bi-
directional data bus, whenever the Microprocessor per-
forms READ or WRITE operations with the Microprocessor
Interface of the XRT86VX38 device.
H13
G14
G12
G13
When DMA interface is enabled, these 8-bit bidirectional
data bus is also used by the T1/E1 Framer or the external
DMA Controller for storing and retrieving information.
H18
H16
G15
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MICROPROCESSOR INTERFACE
REV. 1.0.2
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
BALL
#
BALL #
REQ0
T19
N16
O
8
DMA Cycle Request Output—DMA Controller 0 (Write):
These output pins are used to indicate that DMA transfers
(Write) are requested by the T1/E1 Framer.
On the transmit side (i.e., To transmit data from external
DMA controller to HDLC buffers within the XRT86VX38),
DMA transfers are only requested when the transmit buffer
status bits indicate that there is space for a complete mes-
sage or cell.
The DMA Write cycle starts by T1/E1 Framer asserting the
DMA Request (REQ0) ‘low’, then the external DMA control-
ler should drive the DMA Acknowledge (ACK0) ‘low’ to indi-
cate that it is ready to start the transfer. The external DMA
controller should place new data on the Microprocessor
data bus each time the Write Signal is Strobed low if the
WR is configured as a Write Strobe. If WR is configured as
a direction signal, then the external DMA controller would
place new data on the Microprocessor data bus each time
the Read Signal (RD) is Strobed low.
The Framer asserts this output pin (toggles it "Low") when
at least one of the Transmit HDLC buffers are empty and
can receive one more HDLC message.
The Framer negates this output pin (toggles it “High”) when
the HDLC buffer can no longer receive another HDLC mes-
sage.
REQ1
R16
R16
O
8
DMA Cycle Request Output—DMA Controller 1 (Read):
These output pins are used to indicate that DMA transfers
(Read) are requested by the T1/E1 Framer.
On the receive side (i.e., To transmit data from HDLC buff-
ers within the XRT86VX38 to external DMA Controller),
DMA transfers are only requested when the receive buffer
contains a complete message or cell.
The DMA Read cycle starts by T1/E1 Framer asserting the
DMA Request (REQ1) ‘low’, then the external DMA control-
ler should drive the DMA Acknowledge (ACK1) ‘low’ to indi-
cate that it is ready to receive the data. The T1/E1 Framer
should place new data on the Microprocessor data bus
each time the Read Signal is Strobed low if the RD is con-
figured as a Read Strobe. If RD is configured as a direction
signal, then the T1/E1 Framer would place new data on the
Microprocessor data bus each time the Write Signal (WR)
is Strobed low.
The Framer asserts this output pin (toggles it "Low") when
one of the Receive HDLC buffer contains a complete
HDLC message that needs to be read by the µC/µP.
The Framer negates this output pin (toggles it “High”) when
the Receive HDLC buffers are depleted.
27
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329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
BALL
#
BALL #
INT
J18
H15
O
8
Interrupt Request Output:
This active-low output signal will be asserted when the
XRT86VX38 device is requesting interrupt service from the
Microprocessor. This output pin should typically be con-
nected to the “Interrupt Request” input of the Microproces-
sor.
The Framer will assert this active "Low" output (toggles it
"Low"), to the local µP, anytime it requires interrupt service.
PCLK
P18
M16
I
-
Microprocessor Clock Input:
This clock input signal is only used if the Microprocessor
Interface has been configured to operate in the Synchro-
nous Modes (e.g., Power PC 403 Mode). If the Micropro-
cessor Interface is configured to operate in this mode, then
it will use this clock signal to do the following.
1. To sample the CS, WR/R/W, A[14:0], D[7:0], RD/DS
and DBEN input pins, and
2. To update the state of the D[7:0] and the RDY/
DTACK output signals.
NOTES:
1. This pin is inactive if the user has configured the
Microprocessor Interface to operate in either the
Intel-Asynchronous
or
the
Motorola-
Asynchronous Modes. In this case, the user
should tie this pin to GND.
When DMA interface is enabled, the PCLK input pin is also
used by the T1/E1 Framer to latch in or latch out receive or
output data respectively.
PTYPE0
PTYPE1
PTYPE2
P17
M13
M12
H12
I
-
Microprocessor Type Input:
N18
K19
These input pins permit the user to specify which type of
Microprocessor/Microcontroller to be interfaced to the
XRT86VX38 device. The following table presents the three
different microprocessor types that the XRT86VX38 sup-
ports.
MICROPROCESSOR
TYPE
0
0
1
0
0
0
0
1
1
68HC11, 8051, 80C188
MOTOROLA 68K
IBM POWER PC 403
NOTE
:
These pins are internally pulled “Low” with a 50k
resistor.
Ω
28
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
REV. 1.0.2
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
B
ALL
#
B
ALL #
RDY/DTACK
M16
L16
O
12
Ready/Data Transfer Acknowledge Output:
The exact behavior of this pin depends upon the type of
Microprocessor/Microcontroller the XRT86VX38 has been
configured to operate in, as defined by the PTYPE[2:0]
pins.
Intel Asynchronous Mode - RDY - Ready Output
Tis output pin will function as the “active-low” READY out-
put.
During a READ or WRITE cycle, the Microprocessor Inter-
face block will toggle this output pin to the logic low level,
ONLY when the Microprocessor Interface is ready to com-
plete or terminate the current READ or WRITE cycle. Once
the Microprocessor has determined that this input pin has
toggled to the logic “low” level, then it is now safe for it to
move on and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor
Interface block is holding this output pin at a logic “high”
level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it detects this output pin being
toggled to the logic low level.
Motorola Asynchronous Mode - DTACK - Data Transfer
Acknowledge Output
Tis output pin will function as the “active-low” DTACK out-
put.
During a READ or WRITE cycle, the Microprocessor Inter-
face block will toggle this output pin to the logic low level,
ONLY when the Microprocessor Interface is ready to com-
plete or terminate the current READ or WRITE cycle. Once
the Microprocessor has determined that this input pin has
toggled to the logic “low” level, then it is now safe for it to
move on and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor
Interface block is holding this output pin at a logic “high”
level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it detects this output pin being
toggled to the logic low level.
29
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MICROPROCESSOR INTERFACE
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
B
ALL
#
B
ALL #
RDY/DTACK
M16
L16
O
12
(Con’t)
Power PC 403 Mode - RDY Ready Output:
This output pin will function as the “active-high” READY
output.
During a READ or WRITE cycle, the Microprocessor Inter-
face block will toggle this output pin to the logic high level,
ONLY when the Microprocessor Interface is ready to com-
plete or terminate the current READ or WRITE cycle. Once
the Microprocessor has sampled this signal being at the
logic “high” level upon the rising edge of PCLK, then it is
now safe for it to move on and execute the next READ or
WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor
Interface block is holding this output pin at a logic “low”
level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it samples this output pin
being at the logic low level.
NOTE
:
The Microprocessor Interface will update the state
of this output pin upon the rising edge of PCLK.
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
N19
M17
M18
M15
L16
M19
L17
L19
K15
J16
L13
L14
I
-
Microprocessor Interface Address Bus Input
These pins permit the Microprocessor to identify on-chip
registers and Buffer/Memory locations within the
XRT86VX38 device whenever it performs READ and
WRITE operations with the XRT86VX38 device.
K15
L11
K13
K16
K14
J15
J14
J13
H14
H16
G16
F16
G11
NOTE
:
These pins are internally pulled “Low” with a 50k
resistor, except ADDR[8:14].
Ω
K18
J15
H15
H19
H17
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MICROPROCESSOR INTERFACE
REV. 1.0.2
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
B
ALL
#
B
ALL #
ALE / AS
K17
J16
I
-
Address Latch Enable Input Address Strobe
The exact behavior of this pin depends upon the type of
Microprocessor/Microcontroller the XRT86VX38 has been
configured to operate in, as defined by the PTYPE[2:0]
pins.
Intel-Asynchronous Mode - ALE
This active-high input pin is used to latch the address
(present at the Microprocessor Interface Address Bus pins
(A[14:0]) into the XRT86VX38 Microprocessor Interface
block and to indicate the start of a READ or WRITE cycle.
Pulling this input pin “high” enables the input bus drivers for
the Address Bus input pins (A[14:0]). The contents of the
Address Bus will be latched into the XRT86VX38 Micropro-
cessor Interface circuitry, upon the falling edge of this input
signal.
Motorola-Asynchronous (68K) Mode - AS
This active-low input pin is used to latch the data residing
on the Address Bus, A[14:0] into the Microprocessor Inter-
face circuitry of the XRT86VX38 device.
Pulling this input pin “low” enables the input bus drivers for
the Address Bus input pins. The contents of the Address
Bus will be latched into the Microprocessor Interface cir-
cuitry, upon the falling edge of this signal.
Power PC 403 Mode - No Function -Tie to GND:
This input pin has no role nor function and should be tied to
GND.
CS
G19
F14
I
-
Microprocessor Interface—Chip Select Input:
The user must assert this active low signal in order to
select the Microprocessor Interface for READ and WRITE
operations between the Microprocessor and the
XRT86VX38 on-chip registers and buffer/memory loca-
tions.
31
XRT86VX38
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MICROPROCESSOR INTERFACE
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
B
ALL
#
B
ALL #
RD/DS/WE
N17
L15
I
-
Microprocessor Interface—Read Strobe Input:
The exact behavior of this pin depends upon the type of
Microprocessor/Microcontroller the Framer has been con-
figured to operate in, as defined by the PTYPE[2:0] pins.
Intel-Asynchronous Mode - RD - READ Strobe Input:
This input pin will function as the RD (Active Low Read
Strobe) input signal from the Microprocessor. Once this
active-low signal is asserted, then the XRT86VX38 device
will place the contents of the addressed register (or buffer
location) on the
Microprocessor Interface Bi-directional data bus (D[7:0]).
When this signal is negated, then the Data Bus will be tri-
stated.
Motorola-Asynchronous (68K) Mode - DS - Data
Strobe:
This input pin will function as the DS (Data Strobe) input
signal.
Power PC 403 Mode - WE - Write Enable Input:
This input pin will function as the WE (Write Enable) input
pin.
Anytime the Microprocessor Interface samples this active-
low input signal (along with CS and WR/R/W) also being
asserted (at a logic low level) upon the rising edge of
PCLK, then the Microprocessor Interface will (upon the
very same rising edge of PCLK) latch the
contents on the Bi-Directional Data Bus (D[7:0]) into the
“target” on-chip register or buffer location within the
XRT86VX38 device.
WR / R/W
G17
F13
I
-
Microprocessor Interface—Write Strobe Input
The exact behavior of this pin depends upon the type of
Microprocessor/Microcontroller the XRT86VX38 has been
configured to operate in, as defined by the PTYPE[2:0]
pins.
Intel-Asynchronous Mode - WR - Write Strobe Input:
This input pin functions as the WR (Active Low WRITE
Strobe) input signal from the Microprocessor. Once this
active-low signal is asserted, then the input buffers (associ-
ated with the Bi-Directional Data Bus pin, D[7:0]) will be
enabled.
The Microprocessor Interface will latch the contents on the
Bi-Directional Data Bus (into the “target” register or
address location, within the XRT86VX38) upon the rising
edge of this input pin.
Motorola-Asynchronous Mode - R/W - Read/Write
Operation Identification Input Pin:
This pin is functionally equivalent to the “R/W” input pin. In
the Motorola Mode, a “READ” operation occurs if this pin is
held at a logic “1”, coincident to a falling edge of the RD/DS
(Data Strobe) input pin. Similarly a WRITE operation
occurs if this pin is at a logic “0”, coincident to a falling edge
of the RD/DS (Data Strobe) input pin.
32
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MICROPROCESSOR INTERFACE
REV. 1.0.2
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
B
ALL
#
B
ALL #
WR / R/W
G17
F13
I
-
(Con’t)
Power PC 403 Mode - R/W - Read/Write Operation Iden-
tification Input:
This input pin will function as the “Read/Write Operation
Identification Input” pin.
Anytime the Microprocessor Interface samples this input
signal at a logic "High" (while also sampling the CS input
pin “Low”) upon the rising edge of PCLK, then the Micro-
processor Interface will (upon the very same rising edge of
PCLK) latch the contents of the Address Bus (A[14:0]) into
the Microprocessor Interface circuitry, in preparation for this
forthcoming READ operation. At some point (later in this
READ operation) the Microprocessor will also assert the
DBEN/OE input pin, and the Microprocessor Interface will
then place the contents of the “target” register (or address
location within the XRT86VX38 device) upon the Bi-Direc-
tional Data Bus pins (D[7:0]), where it can be read by the
Microprocessor.
Anytime the Microprocessor Interface samples this input
signal at a logic "Low" (while also sampling the CS input
pin a logic “Low”) upon the rising edge of PCLK, then the
Microprocessor Interface will (upon the very same rising
edge of PCLK) latch the contents of the Address Bus
(A[14:0]) into the Microprocessor Interface circuitry, in
preparation for the forthcoming WRITE operation. At some
point (later in this WRITE operation) the Microprocessor
will also assert the RD/DS/WE input pin, and the Micropro-
cessor Interface will then latch the contents of the Bi-Direc-
tional Data Bus (D[7:0]) into the contents of the “target”
register or buffer location (within the XRT86VX38).
33
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MICROPROCESSOR INTERFACE
329 PKG 256 PKG
O
UTPUT
S
IGNAL
NAME
TYPE
DESCRIPTION
D
RIVE (MA)
B
ALL
#
BALL #
ACK0
T18
N15
I
-
DMA Cycle Acknowledge Input—DMA Controller 0
(Write):
The external DMA Controller will assert this input pin “Low”
when the following two conditions are met:
1. After the DMA Controller, within the Framer has
asserted (toggled “Low”), the Req_0 output signal.
2. When the external DMA Controller is ready to
transfer data from external memory to the selected
Transmit HDLC buffer.
At this point, the DMA transfer between the external mem-
ory and the selected Transmit HDLC buffer may begin.
After completion of the DMA cycle, the external DMA Con-
troller will negate this input pin after the DMA Controller
within the Framer has negated the Req_0 output pin. The
external DMA Controller must do this in order to acknowl-
edge the end of the DMA cycle.
ACK1
R19
M15
DMA Cycle Acknowledge Input—DMA Controller 1
(Read):
The external DMA Controller asserts this input pin “Low”
when the following two conditions are met:
1. After the DMA Controller, within the Framer has
asserted (toggled "Low"), the Req_1 output signal.
2. When the external DMA Controller is ready to
transfer data from the selected Receive HDLC buffer
to external memory.
At this point, the DMA transfer between the selected
Receive HDLC buffer and the external memory may begin.
After completion of the DMA cycle, the external DMA Con-
troller will negate this input pin after the DMA Controller
within the Framer has negated the Req_1 output pin. The
external DMA Controller will do this in order to acknowl-
edge the end of the DMA cycle.
NOTE
:
This pin is internally pulled “High” with a 50k
resistor.
Ω
RESET
V4
R4
I
-
Hardware Reset Input
Reset is an active low input. If this pin is pulled “Low” for
more than 10µS, the device will be reset. When this occurs,
all output will be ‘tri-stated’, and all internal registers will be
reset to their default values.
34
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REV. 1.0.2
POWER SUPPLY PINS (3.3V)
329 PKG 256 PKG
S
IGNAL
N
AME
TYPE
DESCRIPTION
B
ALL#
BALL #
VDD
A1
A16
E8
PWR
Framer Block Power Supply (I/O)
A12
A19
B6
E11
G15
M6
B9
E16
F5
M9
N14
T16
J17
P16
R11
R13
R15
R18
T7
U4
V1
W11
W15
RVDD
C2
E2
G1
J2
B2
D2
F2
H2
K2
M2
P2
T1
PWR
Receiver Analog Power Supply for LIU Section
L2
N2
P4
U2
TVDD
D4
G4
J4
D4
F4
F5
H5
K4
K5
M5
N4
PWR
Transmitter Analog Power Supply for LIU Section
K5
M4
N5
R3
T4
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REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
POWER SUPPLY PINS (1.8V)
329 PKG 256 PKG
S
IGNAL
N
AME
TYPE
DESCRIPTION
B
ALL
#
B
ALL #
VDD18
D13
E6
F8
F9
PWR Framer Block Power Supply
E8
F10
G6
H6
E9
E11
E12
E13
E15
F15
G5
H11
J6
J11
K6
K11
L7
G7
G9
L8
G11
G13
J5
L9
L10
J7
J13
L7
L13
L15
M5
N7
N9
N11
N13
P15
R9
R10
R12
R14
T6
DVDD18
AVDD18
B4
D6
C6
C5
PWR Digital Power Supply for LIU Section
PWR Analog Power Supply for LIU Section
PWR Analog Power Supply for PLL
VDDPLL18
A2
B2
B3
C4
A3
A4
B3
D5
36
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OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
GROUND PINS
329 PKG 256 PKG
S
IGNAL
N
AME
TYPE
DESCRIPTION
B
ALL
#
B
ALL #
VSS
A3, A6
A15, C5
E7, F2
E7
E9
F6
F7
G7
G8
G9
GND
Framer Block Ground
G8, G10
G12, H5
H7, H8
H9, H10
H11, H12
H13, J8
J9, J10
G10
H7
H8
H9
H10
J7
J11, J12
K7, K8
K9, K10
K11, K12
K13, L8
L9, L10
L11, L12
M7, M8
M9, M10
M11, M12
M13, N8
N10, N12
N15, P2
R6, U12
W1, W19
J8
J9
J10
K7
K8
K9
K10
DGND
AGND
RGND
A4
C6
D6
B5
GND
GND
GND
Digital Ground for LIU Section
Analog Ground for LIU Section
Receiver Analog Ground for LIU Section
D2
G2
H2
K2
M2
R2
T2
V3
C2
E2
G2
J2
L2
N2
R2
R3
TGND
E4
G3
J3
E5
F3
G5
J5
GND
Transmitter Analog Ground for LIU Section
L5
M3
P3
P5
V2
K3
L5
N3
N5
37
XRT86VX38
REV. 1.0.2
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GROUND PINS
329 PKG 256 PKG
S
IGNAL
N
AME
TYPE
DESCRIPTION
B
ALL#
B
ALL #
GNDPLL
B1
C3
D5
A1
A2
C4
GND
Analog Ground for PLL
NO CONNECT PINS
329 PKG 256 PKG
S
IGNAL
N
AME
TYPE
DESCRIPTION
B
ALL
#
BALL #
NC
F6
F7
F8
F9
NC
No Connection
F10
F11
F12
F13
F14
G6
G14
H6
H14
J6
J14
K6
K14
L6
L14
M6
M14
N6
N14
P6
P7
P8
P9
P10
P11
P12
P13
P14
38
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
ELECTRICAL CHARACTERISTICS
Absolute Maximums
PowerSupply.....................................................................
VDD .. ................................................ -0.5V to +3.465V
Power Rating fpBGA Package.................. 2.4
IO
VDD
-0.5V to +1.890V
CORE...............................................
Storage Temperature ...............................-65°C to 150°C
Operating Temperature Range.................-40°C t o 85°C
Supply Voltage ...................... GND-0.5V to +VDD + 0.5V
Input Logic Signal Voltage (Any Pin) .........-0.5V to + 5.5V
ESD Protection (HBM)......................... ..................>2000V
Input Current (Any Pin) ...................................... + 100mA
DC ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VDD = 3.3V + 5% , VDD
= 1.8V + 5% unless otherwise specified
CORE
IO
ARAMETER
S
YMBOL
P
M
IN
.
TYP
.
MAX
.
U
NITS
C
ONDITIONS
I
Data Bus Tri-State Bus Leakage Current
Input Low voltage
-10
+10
0.8
µA
V
LL
V
IL
IH
V
Input High Voltage
2.0
0.0
2.4
VDD
0.4
V
V
Output Low Voltage
V
I
= -1.6mA
OL
OL
VOH
Output High Voltage
VDD
V
I
= 40µA
OH
I
Open Drain Output Leakage Current
Input High Voltage Current
Input Low Voltage Current
µA
µA
µA
OC
I
-10
-10
10
10
V
V
= VDD
= GND
IH
IH
I
IL
IL
XRT86VX38 POWER CONSUMPTION
Test Conditions: TA = 25°C, VDD = 3.3V + 5% , VDD
= 1.8V + 5%, Internal termination, unless otherwise
CORE
IO
specified
MODE
I
MPEDANCE
MIN
.
TYP
.
MAX
.
U
NITS
CONDITIONS
T1
2.02
1.54
W
All ones Pattern
PRBS Pattern
100Ω
E1
E1
1.95
1.57
W
W
All ones Pattern
PRBS Pattern
75
Ω
1.77
1.44
All ones Pattern
PRBS Pattern
120
Ω
NOTE
:
There are NO power sequence requirements on this device. The VDD or VDD
are independent and do not
CORE
IO
have any special timing restrictions.
39
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
AC ELECTRICAL CHARACTERISTICS TRANSMIT FRAMER (BASE RATE/NON-MUX)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
S
YMBOL
P
ARAMETER
M
IN
.
TYP
.
MAX
.
U
NITS
CONDITIONS
t1
TxSERCLK to TxMSYNC delay
TxSERCLK to TxSYNC delay
TxSERCLK to TxSER data delay
234
230
230
13
nS
nS
nS
nS
t2
t3
t4
Rising Edge of TxSERCLK to Rising Edge of TxCH-
CLK
t5
TxSERCLK to TxSIG delay
230
nS
FIGURE 2. FRAMER
SYSTEM
TRANSMIT
TIMING
D
IAGRAM (BASE RATE/NON-MUX)
1
TxMSYNC
TxSYNC
t
2
TxSERCLK
t
3
TxSER
t
4
TxCHCLK
(Output)
t
5
TxCHN_0
(TxSIG)
B
A
C
D
AC ELECTRICAL CHARACTERISTICS RECEIVE FRAMER (BASE RATE/NON-MUX)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
S
YMBOL
P
ARAMETER
M
IN
.
TYP
.
MAX
.
U
NITS
CONDITIONS
RxSERCLK as an Output
t8
Rising Edge of RxSERCLK to Rising Edge of
RxCASYNC
4
4
4
6
nS
nS
nS
nS
t9
Rising Edge of RxSERCLK to Rising Edge of
RxCRCSYNC
t10
Rising Edge of RxSERCLK to Rising Edge of
RxSYNC (RxSYNC as Output)
t11
Rising Edge of RxSERCLK to Rising Edge of
RxSER
RxSERCLK as an Input
40
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
AC ELECTRICAL CHARACTERISTICS RECEIVE FRAMER (BASE RATE/NON-MUX)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
REV. 1.0.2
S
YMBOL
P
ARAMETER
M
IN
.
TYP
.
MAX
.
U
NITS
CONDITIONS
t13
Rising Edge of RxSERCLK to Rising Edge of
RxCASYNC
8
nS
nS
nS
nS
nS
t14
t15
t15
t16
Rising Edge of RxSERCLK to Rising Edge of
RxCRCSYNC
8
Rising Edge of RxSERCLK to Rising Edge of
RxSYNC (RxSYNC as Output)
10
Rising Edge of RxSERCLK to Rising Edge of
RxSYNC (RxSYNC as Input)
230
10
Rising Edge of RxSERCLK to Rising Edge of
RxSER
FIGURE 3. FRAMER
SYSTEM
R
ECEIVE
TIMING
DIAGRAM (R
X
SERCLK AS AN
O
UTPUT)
RxCRCSYNC
RxCASYNC
RxSYNC
t
9
t
10
RxSERCLK
(Output)
t
11
RxSER
FIGURE 4. FRAMER
SYSTEM
R
ECEIVE TIMING DIAGRAM (RXSERCLK AS AN INPUT)
RxCRCSYNC
RxCASYNC
RxSYNC
t
14
t
15
RxSERCLK
(Input)
t
16
RxSER
41
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
AC ELECTRICAL CHARACTERISTICS TRANSMIT FRAMER (HMVIP/H100 MODE)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
S
YMBOL
P
ARAMETER
M
IN
.
TYP
.
MAX
.
U
NITS
C
ONDITIONS
t1
TxSYNC Setup Time - HMVIP Mode
TxSYNC Hold Time - HMVIP Mode
7
nS
nS
nS
nS
nS
nS
nS
nS
t2
t3
t4
t5
t6
t7
t8
4
7
4
6
3
6
3
TxSYNC Setup Time - H100 Mode
TxSYNC Hold Time - H100 Mode
TxSER Setup Time - HMVIP and H100 Mode
TxSER Hold Time - HMVIP and H100 Mode
TxSIG Setup Time - HMVIP and H100 Mode
TxSIG Hold Time - HMVIP and H100 Mode
F
IGURE 5. FRAMER
S
YSTEM
TRANSMIT
TIMING
D
IAGRAM (HMVIP AND H100 MODE)
TxInClk
(16MHz)
TxSYNC
(HMVIP Mode)
t2
t1
t4
TxSYNC
(H100 Mode)
t3
TxSERCLK
TxSER
t5
t6
t8
TxCHN_0
(TxSIG)
t7
B
A
C
D
NOTE: Setup and Hold time is not valid from TxInClk to TxSERCLK as TxInClk is used as the timing source for the back
plane interface and TxSERCLK is used as the timing source on the line side.
42
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
AC ELECTRICAL CHARACTERISTICS RECEIVE FRAMER (HMVIP/H100 MODE)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
S
YMBOL
P
ARAMETER
M
IN
.
TYP
.
MAX
.
U
NITS
CONDITIONS
t1
RxSYNC Setup Time - HMVIP Mode
RxSYNC Hold Time - HMVIP Mode
RxSYNC Setup Time - H100 Mode
RxSYNC Hold Time - H100 Mode
4
nS
nS
nS
nS
nS
t2
t3
t4
t5
3
5
3
Rising Edge of RxSERCLK to Rising Edge of
RxSER delay
11
NOTE
:
Both RxSERCLK and RxSYNC are inputs
F
IGURE 6. FRAMER
S
YSTEM
R
ECEIVE
TIMING
D
IAGRAM (HMVIP/H100 MODE)
RxSERCLK
(16MHz)
RxSYNC
(HMVIP Mode)
t2
t1
t4
RxSYNC
(H100 Mode)
t3
t5
RxSER
43
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
T
ABLE 4: E1 RECEIVER
= 1.8V + 5%, TA= -40°to 85°C, unless otherwise specified
CORE
ELECTRICAL CHARACTERISTICS
VDD = 3.3V + 5% , VDD
IO
P
ARAMETER
M
IN
.
TYP
.
MAX
.
U
NIT
TEST CONDITIONS
Receiver loss of signal:
Cable attenuation @1024kHz
Number of consecutive zeros before
RLOS is set
32
20
Input signal level at RLOS
RLOS De-asserted
15
dB
ITU-G.775, ETSI 300 233
12.5
11
% ones
dB
Receiver Sensitivity
With nominal pulse amplitude of 3.0V
for 120
tion.
Ω and 2.37V for 75Ω applica-
(Short Haul with cable loss)
Receiver Sensitivity
0
43
dB
With nominal pulse amplitude of 3.0V
for 120
tion.
Ω and 2.37V for 75Ω applica-
(Long Haul with cable loss)
Input Impedance
15
20
k
Ω
Input Jitter Tolerance:
1 Hz
37
UIpp
UIpp
ITU G.823
ITU G.736
ITU G.736
ITU-G.703
10kHz-100kHz
0.3
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude
-
-
kHz
dB
0.5
-
Jitter Attenuator Corner Fre-
quency (-3dB curve) (JABW=0)
10
Hz
Hz
(JABW=1)
1.5
Return Loss:
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
12
8
-
-
dB
dB
dB
8
44
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
T
ABLE 5: T1 RECEIVER
= 1.8V + 5%, TA=-40°to 85°C, unless otherwise specified
CORE
ELECTRICAL CHARACTERISTICS
VDD = 3.3V + 5% , VDD
IO
P
ARAMETER
M
IN.
TYP
.
MAX
.
U
NIT
TEST CONDITIONS
Receiver loss of signal:
Number of consecutive zeros before
RLOS is set
175
20
Input signal level at RLOS
RLOS Clear
15
-
-
dB
Cable attenuation @772kHz
12.5
12
-
-
% ones ITU-G.775, ETSI 300 233
Receiver Sensitivity
dB
With nominal pulse amplitude of 3.0V
for 100 termination
Ω
(Short Haul with cable loss)
Receiver Sensitivity
(Long Haul with cable loss)
Normal
-
With nominal pulse amplitude of 3.0V
for 100 termination
Ω
0
0
36
dB
dB
Extended
45
Input Impedance
15
-
kΩ
Jitter Tolerance:
1Hz
138
0.4
-
-
-
-
UIpp
AT&T Pub 62411
10kHz - 100kHz
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude
-
-
10
6
-
KHz
dB
TR-TSY-000499
AT&T Pub 62411
0.1
Jitter Attenuator Corner Frequency
(-3dB curve)
-
Hz
Return Loss:
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
-
-
-
14
20
16
-
-
-
dB
dB
dB
T
ABLE 6: E1 TRANSMITTER
= 1.8V + 5%, TA=-40°to 85°C, unless otherwise specified
CORE
ELECTRICAL CHARACTERISTICS
VDD = 3.3V + 5% , VDD
IO
P
ARAMETER
M
IN.
TYP
.
MAX
.
U
NIT
TEST CONDITIONS
AMI Output Pulse Amplitude:
75 Application
120 Application
1:2 transformer
2.13
2.70
2.37
3.00
2.60
3.30
V
V
Ω
Ω
Output Pulse Width
224
0.95
0.95
244
264
1.05
1.05
ns
-
Output Pulse Width Ratio
Output Pulse Amplitude Ratio
-
-
ITU-G.703
ITU-G.703
-
45
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
T
ABLE 6: E1 TRANSMITTER
= 1.8V + 5%, TA=-40°to 85°C, unless otherwise specified
CORE
ELECTRICAL CHARACTERISTICS
VDD = 3.3V + 5% , VDD
IO
P
ARAMETER
M
IN.
TYP
.
MAX
.
U
NIT
TEST CONDITIONS
Jitter Added by the Transmitter Output
-
0.025
0.05
UIpp Broad Band with jitter free TCLK
applied to the input.
Output Return Loss:
51kHz -102kHz
15
9
-
-
-
-
-
-
dB
dB
dB
ETSI 300 166
102kHz-2048kHz
2048kHz-3072kHz
8
TABLE 7: E1 TRANSMIT
R
ETURN
L
OSS
REQUIREMENT
R
ETURN
L
OSS
F
REQUENCY
ETS 300166
51-102kHz
6dB
102-2048kHz
2048-3072kHz
8dB
8dB
T
ABLE 8: T1 TRANSMITTER
= 1.8V + 5%, TA=-40°to 85°C, unless otherwise specified
CORE
ELECTRICAL CHARACTERISTICS
VDD = 3.3V + 5% , VDD
IO
P
ARAMETER
M
IN.
TYP
.
MAX
.
U
NIT
TEST CONDITIONS
AMI Output Pulse Amplitude:
Output Pulse Width
2.4
3.0
350
-
3.60
362
20
V
ns
-
1:2 transformer measured at DSX-1.
ANSI T1.102
338
Output Pulse Width Imbalance
Output Pulse Amplitude Imbalance
Jitter Added by the Transmitter Output
-
-
-
ANSI T1.102
-
+200
0.05
mV
ANSI T1.102
0.025
UIpp Broad Band with jitter free TCLK
applied to the input.
Output Return Loss:
51kHz -102kHz
-
-
-
17
12
10
-
-
-
dB
dB
dB
102kHz-2048kHz
2048kHz-3072kHz
46
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
FIGURE 7. ITU G.703 PULSE TEMPLATE
269 ns
(244 + 25)
V = 100%
194 ns
(244 – 50)
Nominal pulse
50%
244 ns
219 ns
(244 – 25)
0%
488 ns
(244 + 244)
Note
– V corresponds to the nominal peak value.
TABLE 9: TRANSMIT PULSE MASK SPECIFICATION
Test Load Impedance
75
Ω
Resistive (Coax)
2.37V
120
Ω
Resistive (twisted Pair)
3.0V
Nominal Peak Voltage of a Mark
Peak voltage of a Space (no Mark)
Nominal Pulse width
0 + 0.237V
244ns
0 + 0.3V
244ns
Ratio of Positive and Negative Pulses Imbalance
0.95 to 1.05
0.95 to 1.05
47
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
FIGURE 8. ITU G.703 SECTION 13 SYNCHRONOUS
INTERFACE
PULSE TEMPLATE
T
T
T
T
T
T
30 30
30 30
30 30
+V
+V1
0
–V1
–V
T
4
T
4
T
4
T
4
T
T1818900-92
Shaded area in which
signal should be
monotonic
T Average period of
synchronizing signal
TABLE 10: E1 SYNCHRONOUS
I
NTERFACE TRANSMIT PULSE MASK SPECIFICATION
Test Load Impedance
75
Ω
Resistive (Coax)
1.5V
120
Ω
Resistive (twisted Pair)
Maximum Peak Voltage of a Mark
Minimum Peak Voltage of a Mark
Nominal Pulse width
1.9V
1.0V
0.75V
244ns
244ns
48
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
FIGURE 9. DSX-1 PULSE
TEMPLATE
(
NORMALIZED AMPLITUDE
)
TABLE 11: DSX1 INTERFACE
ISOLATED PULSE MASK AND CORNER POINTS
MINIMUM CURVE
MAXIMUM CURVE
T
IME (UI)
-0.77
-0.23
-0.23
-0.15
0.0
N
ORMALIZED AMPLITUDE
T
IME (UI)
-0.77
-0.39
-0.27
-0.27
-0.12
0.0
N
ORMALIZED AMPLITUDE
-.05V
-.05V
0.5V
.05V
.05V
.8V
0.95V
0.95V
0.9V
1.15V
1.15V
1.05V
1.05V
-0.07V
0.05V
0.05V
0.15
0.23
0.23
0.46
0.66
0.93
1.16
0.5V
0.27
-0.45V
-0.45V
-0.2V
-0.05V
-0.05V
0.35
0.93
1.16
49
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
T
ABLE 12: AC ELECTRICAL
C
HARACTERISTICS
=25°C, UNLESS OTHERWISE SPECIFIED
YP AX
VDD = 3.3V + 5% , VDD
= 1.8V + 5%, TA
IO
CORE
P
ARAMETER
S
YMBOL
MIN
.
T
.
M
.
U
NITS
MCLKIN Clock Duty Cycle
MCLKIN Clock Tolerance
40
-
-
60
%
±50
-
ppm
50
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
MICROPROCESSOR INTERFACE I/O TIMING
I
NTEL INTERFACE TIMING - ASYNCHRONOUS
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum
external glue logic and is compatible with the timings of the 8051 or 80188 family of microprocessors. The ALE
signal can be tied ’HIGH’ if this signal is not available, and the corresponding timing interface is shown in
Figure 11 and Table 14.
FIGURE 10. INTEL µP INTERFACE
TIMING
D
URING
PROGRAMMED I/O READ AND WRITE OPERATIONS WHEN ALE IS
N
OT IED ’HIGH’
T
t 5
t 5
READ OPERATION
WRITE OPERATION
ALE
ADDR[14:0]
CS
t 0
t0
Valid Address
Valid Address
Valid Data for Readback
DATA[7:0]
RD
Data Available to Write Into the LIU
t1
t3
WR
t2
t4
RDY
TABLE 13: INTEL
MICROPROCESSOR
I
NTERFACE
TIMING
SPECIFICATIONS
S
YMBOL
P
ARAMETER
MIN
M
AX
U
NITS
t
Valid Address to CS Falling Edge and ALE Rising
Edge
0
-
ns
0
t
t
ALE Falling Edge to RD Assert
RD Assert to RDY Assert
5
-
-
ns
ns
ns
ns
ns
ns
ns
1
2
320
NA
RD Pulse Width (t )
320
5
-
2
t
t
ALE Falling Edge to WR Assert
WR Assert to RDY Assert
-
320
-
3
4
-
NA
WR Pulse Width (t )
320
10
4
t
ALE Pulse Width(t )
5
5
51
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
F
T
IGURE 11. INTEL µP INTERFACE
IED ’HIGH’
TIMING DURING PROGRAMMED I/O READ AND WRITE OPERATIONS WHEN ALE IS
READ OPERATION
WRITE OPERATION
ALE
t
0
t
0
ADDR[14:0]
CS
Valid Address
Valid Address
Valid Data for Readback
DATA[7:0]
RD
Data Available to Write Into the LIU
t1
t3
WR
t2
t4
RDY
TABLE 14: INTEL
MICROPROCESSOR
I
NTERFACE
TIMING SPECIFICATIONS
S
YMBOL
P
ARAMETER
MIN
M
AX
U
NITS
t
t
t
Valid Address to CS Falling Edge
CS Falling Edge to RD Assert
RD Assert to RDY Assert
0
-
ns
0
1
2
0
-
-
ns
ns
ns
ns
ns
ns
320
NA
RD Pulse Width (t )
320
0
-
2
t
t
CS Falling Edge to WR Assert
WR Assert to RDY Assert
-
320
-
3
4
-
NA
WR Pulse Width (t )
320
4
52
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
M
OTOROLA ASYCHRONOUS INTERFACE TIMING
The signals used in the Motorola microprocessor interface mode are: Address Strobe (AS), Data Strobe (DS),
Read/Write Enable (R/W), Chip Select (CS), Address and Data bits. The interface is compatible with the timing
of a Motorola 68000 microprocessor family. The interface timing is shown in Figure 12. The I/O specifications
are shown in Table 15.
FIGURE 12. MOTOROLA
A
SYCHRONOUS
M
ODE
I
NTERFACE
S
IGNALS
DURING
PROGRAMMED I/O READ AND WRITE
OPERATIONS
READ OPERATION
W RITE OPERATION
ALE_AS
t0
t0
Valid Address
Valid Address
ADDR[6:0]
CS
t3
t3
Valid Data for Readback
DATA[7:0]
RD_DS
Data Available to Write Into the LIU
t1
t1
WR_R/W
t2
RDY_DTACK
t2
TABLE 15: MOTOROLA
A
SYCHRONOUS
M
ODE
M
ICROPROCESSOR
I
NTERFACE
TIMING SPECIFICATIONS
S
YMBOL
P
ARAMETER
MIN
M
AX
U
NITS
t
t
t
Valid Address to CS Falling Edge
0
-
ns
0
1
2
CS Falling Edge to DS (Pin RD_DS) Assert
DS Assert to DTACK Assert
0
-
-
ns
ns
ns
ns
320
NA
DS Pulse Width (t )
320
0
-
-
2
t
CS Falling Edge to AS (Pin ALE_AS) Falling Edge
3
53
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
POWER PC 403 SYCHRONOUS INTERFACE TIMING
The signals used in the Power PC 403 Synchronus microprocessor interface mode are: Address Strobe (AS),
Microprocessor Clock (uPCLK), Data Strobe (DS), Read/Write Enable (R/W), Chip Select (CS), Address and
Data bits. The interface timing is shown in Figure 13. The I/O specifications are shown in Table 16.
FIGURE 13. POWER PC 403 INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
READ OPERATION
WRITE OPERATION
TS
tdc
uPCLK
tcp
t0
t0
Valid Address
Valid Address
ADDR[14:0]
CS
t3
t3
Valid Data for Readback
DATA[7:0]
WE
Data Available to Write Into the LIU
t1
R/W
TA
t2
T
ABLE 16: POWER PC 403 MICROPROCESSOR
I
NTERFACE
IN
TIMING
S
PECIFICATIONS
S
YMBOL
P
ARAMETER
M
M
AX
UNITS
t
t
t
Valid Address to CS Falling Edge
CS Falling Edge to WE Assert
WE Assert to TA Assert
0
-
ns
ns
ns
ns
0
1
2
0
-
-
320
NA
WE Pulse Width (t )
320
0
-
-
2
t
CS Falling Edge to TS Falling Edge
3
t
µ
PCLK Duty Cycle
40
20
60
-
%
dc
cp
t
µPCLK Clock Period
ns
54
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
86VX38
ORDERING INFORMATION
P
RODUCT
N
UMBER
P
ACKAGE
O
PERATING
TEMPERATURE
R
ANGE
XRT86VX38IB329
XRT86VX38IB256
329 Fine Pitch Ball Grid Array
256 Fine Pitch Ball Grid Array
-40
°
°
C to +85
C to +85
°
C
C
-40
°
PACKAGE DIMENSIONS FOR 329 FINE PITCH BALL GRID ARRAY
329 Fine Pitch Ball Grid Array
(17.0 mm x 17.0 mm, fpBGA)
Rev. 1.00
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A1 corner
A
B
C
D
E
F
G
H
J
K
L
D
D1
M
N
P
R
T
U
V
W
D1
D
(A1 corner feature is mfger option)
Seating
Plane
b
A2
e
A
A1
Note: The control dimension is in millimeter.
INCHES MILLIMETERS
SYMBOL
MIN
MAX
0.067
0.014
0.053
0.675
MIN
1.43
0.26
1.17
16.85
MAX
1.71
0.36
1.35
17.15
A
A1
A2
D
0.056
0.010
0.046
0.663
D1
b
0.567 BSC
14.40 BSC
0.014
0.018
0.36
0.46
e
0.031 BSC
0.80 BSC
55
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
4
PACKAGE DIMENSIONS FOR 256 FINE PITCH BALL GRID ARRAY
256 Fine Pitch Ball Grid Array
(17.0 mm x 17.0 mm, fpBGA)
Rev. 1.00
10
9
8
7
6
5
4
3
2
1
16 15 14 13 12 11
A1 corner
A
B
C
D
E
F
G
H
J
D
D1
K
L
M
N
P
R
T
D1
D
(A1 corner feature is mfger option)
Seating
Plane
b
A2
e
A
A1
Note: The control dimension is in millimeter.
INCHES
MIN
0.058
0.013
0.045
0.661
MILLIMETERS
SYMBOL
MAX
0.070
0.017
0.053
0.677
MIN
1.48
0.33
1.15
16.80
MAX
A
A1
A2
D
1.78
0.43
1.35
17.20
D1
b
0.591 BSC
15.00 BSC
0.020
0.024
0.50
0.60
e
0.039 BSC
1.00 BSC
56
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.2
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2010 EXAR Corporation
Datasheet January 2010.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
57
XRT86VX38
REV. 1.0.2
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
P4.
REVISION HISTORY
R
EVISION
1.0.0
#
D
ATE
DESCRIPTION
May. 01, 2009
June 15, 2009
Initial release of Hardware Description
1.0.1
Update packaging name to fpBGA, add BITS functionality to general description,
updated features and applications and updates to eletrical tables
1.0.2
January 29, 2010 Added timing diagrams, microprocessor timing, and general edits.
58
相关型号：
XRT91L30IQ-F
Transceiver, 1-Func, PQFP64, 10 X 10 MM, 2 MM HEIGHT, ROHS COMPLIANT, PLASTIC, QFP-64
EXAR
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