XR18910 [EXAR]
8:1 Sensor Interface Analog Front End;
| 型号： | XR18910 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | 8:1 Sensor Interface Analog Front End |
| 文件： | 总19页 (文件大小：948K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XR18910
8:1 Sensor Interface Analog Front End
Description
FEATURES
The XR18910 is a unique sensor interface integrated circuit with an
onboard 8:1 multiplexer, offset correction Digital-to-Analog Converter
(DAC), instrumentation amplifier and voltage reference. The XR18910
is designed to integrate multiple bridge sensors with a Microcontroller
(MCU) or Field-Programmable Gate Array (FPGA).
ꢀ■
Integrated features for interfacing multiple
bridge sensors with an MCU or FPGA
8:1 differential MUX with I2C interface
Instrumentation amplifier
LDO
Offset correction DAC with I2C interface
( 560mV offset correction range)
Eight selectable voltage gains from 2V/V to
760V/V with only 0.5ꢀ gain error
3mV maximum input offset voltage
100pA maximum input bias current
559μA maximum supply current
2.7V to 5V analog supply voltage range
1.8V to 5V digital supply voltage range
-40°C to 85°C temperature range
3.5mm x 3.5mm QFN-24 package
The integrated offset correction DAC provides digital calibration of the
variable and in many cases substantial offset voltage generated by the
bridge sensors. The DAC is controlled by an I2C compatible 2-wire serial
interface. The serial interface also provides the user with easy controls
to the XR18910’s many functions such as input and gain selection.
■■
■■
■■
■■
■■
■■
■■
■■
A linear regulator (LDO) provides a regulated voltage to power the input
bridge sensors and is selectable, between 3V and 2.65V. The LDO
current can be sensed and a proportional voltage present at the output
of the IC for monitoring the LDO current.
The XR18910 offers 8 fixed gain settings (from 2V/V to 760V/V), each
with an error of only 0.5ꢀ, that are selectable via the I2C interface.
It also offers less than 3mV maximum input offset voltage, 100pA
maximum input bias current, and 100pA maximum input offset current.
APPLICATIONS
Bridge sensor interface
Pressure and temperature sensors
■■
■■
■■
The XR18910 is designed to operate from 2.7V to 5V supplies, specified
over the industrial temperature range of -40°C to 85°C and is offered in
a space saving 3.5mm x 3.5mm QFN package. It consumes less than
559μA supply current and offers a sleep mode for added power savings.
Strain gauge amplifier
Industrial process controls
Weigh scales
■■
■■
The XR18910 is well suited for industrial and consumer applications
using bridge sensors.
Typical Application
m
m
DD
CC
5.8μF
+
5.8μF
+
2.5
2
6.1μF
mDD
6.1μF
BRDG
mCC
6.1μF
16k
1.5
1
BRIDGE 8
LDO
IN8+
IN8-
0.5
0
OUT
INA /
PGA
ADC
µC
-0.5
-1
16nF
8:1
MUX
±±560m
OFFSET TRIM
m
m
DD
DD
-1.5
-2
BRIDGE 1
16-BIT
DAC
PGA
4.7k
4.7k
IN1+
IN1-
SDA
SCL
2
-2.5
I C
CONTROL
0
2
4
6
8
10
Time (seconds)
XR18910
AGND
DGND
Figure 1. Typical Application
Figure 2. 0.1Hz to 10Hz RTI Voltage Noise
REV1A
1/19
XR18910
Absolute Maximum Ratings
Operating Conditions
Analog supply voltage range .................................... 2.7V to 5.25V
Digital supply voltage range.......................................1.7V to 5.25V
Operating temperature range ...................................-40°C to 85°C
Junction temperature............................................................150°C
Storage temperature range.....................................-65°C to 150°C
Lead temperature (soldering, 10s)........................................260°C
Package thermal resistance θJA ......................................50°C/W(1)
Stresses beyond the limits listed below may cause
permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect
device reliability and lifetime.
Analog supply voltage (VCC).......................................... 0V to 5.5V
Digital supply voltage (VDD)........................................... 0V to 5.5V
Digital input/output (VDDIO)............................................ 0V to 5.5V
VIN .....................................................................................0 to VCC
Differential input voltage (current limit of 10mA) ...................... VCC
ESD rating (HBM - human body model)...................................4kV
NOTE:
1. JEDEC standard, multi-layer test boards, still air.
REV1A
2/19
XR18910
Electrical Characteristics
T = 25°C, V = 3.3V, V = 1.8V, R = 10kΩ to 1.5V, G = 760, unless otherwise noted.
A
CC
DD
L
Symbol Parameter
DC Performance
Conditions
Min
-3
Typ
Max
Units
V
IO
Input offset voltage
Input referred
0.02
3
3
mV
μV/°C
pA
d
Input offset voltage average drift
Input bias current
Input offset current
Power supply rejection ratio
Gain = 2
VIO
I
I
-100
-100
60
15
100
100
B
1
pA
OS
PSRR
V
CC
= 2.7V to 5V
91
dB
2.0
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
ꢀ
Gain = 20
20.0
40.0
80.0
150.0
299.9
599.6
759.4
Gain = 40
Gain = 80
G
Nominal, refer to Gain Register Table (pg. 7)
Gain = 150
Gain = 300
Gain = 600
Gain = 760
G
Gain error
-0.5
0.5
E
Gain error vs temperature
10
435
48
ppm/°C
μA
I
I
I
I
V
CC
supply current
No load to output, no load to LDO
530
62
SVCC
Disable V supply current
No load to output, no load to LDO
μA
SVCCD
SVDD
CC
V
supply current
No load to output, no load to LDO, I2C running
22
29
μA
DD
Total supply current
No load to output, no load to LDO
457
45
559
μA
STOTAL
No load to output, no load to LDO, LDO DIS
No load to output, no load to LDO, LDO EN
μA
I
Total disable supply current
SDTOTAL
70
91
μA
Input Characteristics
Input impedance
1013 || 11.2
Ω || pF
V
0.23 to
3.06
CMIR
Common mode input range
0.5
75
2.5
CMRR
Common mode rejection ratio
Input referred, V
= 0.5 to 2.0V
88
dB
CM
Output Characteristics
0.04 to
3.29
1.5
V
Output voltage swing
Output offset
R = 10kΩ to 1.5V
0.1
1.4
3.1
1.6
V
V
OUT
L
V
OO
Offset DAC 0 00 0000 0000, G = 2
Offset DAC
LDO
Offset DAC range
Offset monotonicity
RTI (referred to input)
560
8
mV
10
Bits
1.5k load, LDO bit LOW
1.5k load, LDO bit HIGH
-6ꢀ
-6ꢀ
3
+6ꢀ
+6ꢀ
150
V
Output voltage
2.65
V
Dropout voltage
Output current
V
CC
= 2.8V, LDO = 2.65V, I
= 10mA
mV
mA
dB
dB
LOAD
10
45
45
25
63
63
Output referred, V = 3V to 5V, LDO = 2.65V
CC
Power supply rejection ratio
Output referred, V = 3.3V to 5V, LDO = 3V
CC
Output current sense transimpedance slope Output voltage relative to 1.5V / LDO current, G = 2
Output current sense range clip G = 2
0.08
0.1
0.12
V/mA
mA
18.8
REV1A
3/19
XR18910
Electrical Characteristics (Continued)
T = 25°C, V = 3.3V, V = 1.8V, R = 10kΩ to 1.5V, G = 760, unless otherwise noted.
A
CC
DD
L
Symbol Parameter
Dynamic Performance
Conditions
Min
Typ
Max
Units
G = 760
G = 2
66
1300
1
kHz
kHz
BW
SR
-3dB bandwidth
Slew rate
V
= 1V , G = 2
V/μs
OUT
P-P
f = 10Hz
75
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
e
Input voltage noise, RTI
f = 100Hz
46
NI
f = 1kHz
35
i
Input current noise
Peak-to-peak noise
Crosstalk
f = 10Hz
0.6
2
N
e
f = 0.1 to 10Hz
μV
P-P
NP-P
XTALK
Channel-to-channel, f = 1kHz
Analog ready after serial register finished write
Wake from ACK of SLEEP_OUT command
90
dB
T
T
Set-up time, 1ꢀ settling
Wake up time, 1ꢀ settling
3.5
9.6
μs
μs
S
WAKE
Digital Characteristics (CMOS)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
V
Logic input HIGH
Logic input LOW
Input leakage HIGH
Input leakage LOW
Clock rate
0.7 x V
V
DD
V
V
IH
IL
DD
0
0.3 x V
DD
I
I
V = V
S
10
μA
μA
MHz
IH
IL
I
V = 0
I
-10
CLK
0.4
F
I2C Bus Timing
T = -40 to 85°C, V = 1.8 to 5V, unless otherwise noted.
A
DD
Standard Mode
I2C-BUS
Fast Mode
I2C-BUS
Symbol
Parameter
Units
Min
0
Max
100
Min
Max
f
Operating frequency
0
400
kHz
μs
SCL
Bus free time between STOP and
START
T
4.7
1.3
BUF
T
T
T
T
T
T
T
T
T
T
T
START condition hold time
START condition setup time
Data hold time
4.0
4.7
0
0.6
0.6
0
μs
μs
μs
μs
ns
ns
μs
μs
ns
ns
μs
HD;STA
SU;STA
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
Data valid acknowledge
SCL LOW to data out valid
Data setup time
0.6
0.6
0.6
0.6
250
4.7
4.0
150
1.3
Clock LOW period
Clock HIGH period
0.6
HIGH
F
Clock/data fall time
300
300
300
Clock/data rise time
1000
R
Pulse width of spikes tolerance
0.5
0.5
SP
REV1A
4/19
XR18910
Electrical Characteristics (Continued)
START
condition
(S)
Bit 7
MSB
(A7)
Bit 0
LSB
(R/W)
STOP
condition
(P)
Bit 6
(A6)
Acknowledge
(A)
Protocol
TSU;STA
TLOW THIGH
1/FSCL
SCL
TF
TR
TSP
TBUF
SDA
THD;STA
TSU;DAT
THD;DAT
TVD;DAT
TVD;ACK
TSU;STO
Figure 3. I2C Bus Timing Diagram
REV1A
5/19
XR18910
Electrical Characteristics (Continued)
Table 1. Register List
R/
W/
C
Reg No.
Byte of
Parameter
Default Power-up
Name
NOP
Function
Parameter
Remark
Code
Condition
Hex Dec
Does not execute a function. NOP is used to
test successful I2C communication
0x00
Reset
0x01
0
No operation
C
0
0
N/A
1
SW_RESET
Software reset
Read Device ID
C
N/A
Resets all registers to default values
Read ID
[15:0]: report “8910” in
BCD
Instructs the XR18910 to report its device ID
8910 in binary form (1000 1001 0001 0000)
0x02
2
DEVICE_ID
R
R
2
2
0x8910
N/A
[15:12]: reserved
[11:8]: Hardware version #
[7:0]: Software version #
Initial H/W version number is ‘0’;
Initial S/W version number is ‘01’.
Read HW & SW
version numbers
0x03
3
VERSION_ID
Sleep in/out
SLEEP_OUT_
REG
Normal operating
mode, system active
0x04
4
C
C
0
0
N/A
N/A
Active
Active
Puts the XR18910 into active mode. (wake up)
Puts the analog portion of the XR18910 into
sleep mode.
SLEEP_IN_
REG
0x05
5
Sleep Mode
During sleep mode, the only I2C command
that can be received/processed is the
SLEEP_OUT command (0x04). All other
register addresses will be ignored.
Basic Config
Eight gain settings are selectable (from 2V/V
Gain = 2 to 760V/V), refer to the Gain Register Table
for more information.
0x06
6
Gain
LDO
Gain select
R/W
R/W
1
1
[2:0]: Gain select
0x00
0x00
Bit 0 controls the LDO voltage (0:3V;1:2.65V).
[0]:LDO 3V, 2.65V
[1]:LDO disable
Bit 1 (Sleep Mode only). Bit 1 controls whether
the LDO shuts down or stays on during Sleep
Mode. (0: Enable; 1: Disable). When the
XR18910 is active, the LDO is always on.
0x07
0x08
7
LDO Settings
LDO = 3V
When on, the LDO current is sensed and a
proportional voltage is present at the output of
the XR18910.
LDO Current
Sense Select
8
LDO Current Sense
C
0
N/A
Off
Current Sense Mode remains active until an input
select command is received by the XR18910.
Channel Switch (Input MUX Select)
0x10 16
0x12 18
0x14 20
0x15 21
0x18 24
0x1A 26
0x1C 28
0x1E 30
Select_Input_1 Select Channel 1
C
C
C
C
C
C
C
C
0
0
0
0
0
0
0
0
Select +IN1, -IN1; Channel 1
Select +IN2, -IN2; Channel 2
Select +IN3, -IN3; Channel 3
Select_Input_2 Select Channel 2
Select_Input_3 Select Channel 3
Select_Input_4 Select Channel 4
Select_Input_5 Select Channel 5
Select_Input_6 Select Channel 6
Select_Input_7 Select Channel 7
Select_Input_8 Select Channel 8
Select +IN4, -IN4; Channel 4
Select +IN5, -IN5; Channel 5
Select +IN6, -IN6; Channel 6
Select +IN7, -IN7; Channel 7
Select +IN8, -IN8; Channel 8
Channel 1
is selected
N/A
Offset DAC Config
Configures DAC offset
applied to Channel 1
0x20 32
0x22 34
0x24 36
0x25 37
0x28 40
0x2A 42
0x2C 44
0x2E 46
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
DAC8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
2
2
2
2
2
2
2
Configures DAC offset
applied to Channel 2
Configures DAC offset
applied to Channel 3
Bit 10 controls the sign of the DAC offset
voltage. Bits 9 thru 0 control the value of
the DAC offset voltage.
Configures DAC offset
applied to Channel 4
[10]: DAC Sign
0mV
0x00
Configures DAC offset
applied to Channel 5
[9:0]: DAC Range
offset
Configures DAC offset
applied to Channel 6
[10]: DAC Sign 0 = positive; 1 = negative
Configures DAC offset
applied to Channel 7
Configures DAC offset
applied to Channel 8
NOTE:
Register numbers not listed above have no function.
REV1A
6/19
XR18910
Electrical Characteristics (Continued)
Table 2. DAC Registers
Hex
D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Offset ꢀ of FS Input
Voltage RTI
0x3FF
0x000
0x7FF
0x400
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
50
0
560mV
0
-560mV
0
-50
0
DAC
Sign
10-Bit DAC Range
Table 3. Gain Registers
Hex
D2
D1
D0
Gain
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
20
40
80
150
300
600
760
REV1A
7/19
XR18910
Pin Configuration
VDD
IN1+
IN1-
1
2
3
4
5
6
18
17
16
15
14
13
BRDG
IN8-
IN8+
IN7-
IN2+
IN2-
IN3+
IN7+
IN6-
NOTE:
Exar recommends grounding the exposed pad.
Pin Functions
Pin Number
Pin Name
VDD
IN1+
IN1-
Description
1
2
Digital Supply
Positive Input 1
Negative Input 1
Positive Input 2
Negative Input 2
Positive Input 3
Negative Input 3
Positive Input 4
Negative Input 4
Positive Input 5
Negative Input 5
Positive Input 6
Negative Input 6
Positive Input 7
Negative Input 7
Positive Input 8
Negative Input 8
BRDG Power Connection (LDO output)
Analog Ground
Output
3
4
IN2+
IN2-
5
6
IN3+
IN3-
7
8
IN4+
IN4-
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
IN5+
IN5-
IN6+
IN6-
IN7+
IN7-
IN8+
IN8-
BRDG
AGND
OUT
VCC
DGND
SCL
Analog Supply
Digital Ground
Serial Clock Input
Serial Data Input/Output
SDA
REV1A
8/19
XR18910
Typical Performance Characteristics
T = 25°C, V = 3.3V, V = 1.8V, R = 10kΩ to 1.5V, G = 760, unless otherwise noted.
A
CC
DD
L
2
1.75
1.5
G = 2, VOUT = 2.5VP-P
G = 2, VOUT = 0.5VP-P
3
2.5
2
1.5
1
1.25
1
0.5
0
0
10
20
30
40
0
10
20
30
40
Time (µs)
Time (µs)
Figure 4. Small Signal Pulse Response at G = 2
Figure 5. Large Signal Pulse Response at G = 2
2
G = 300, VOUT = 2.5VP-P
3
G = 300, VOUT = 0.5VP-P
2.5
2
1.75
1.5
1.25
1
1.5
1
0.5
0
0
20
40
60
Time (µs)
80
100
0
20
40
60
80
100
Time (µs)
Figure 6. Small Signal Pulse Response at G = 300
Figure 7. Large Signal Pulse Response at G = 300
3
3
G = 2
G = 300
0
0
-3
-6
-3
-6
VOUT = 0.5VP-P
VOUT = 0.5VP-P
VOUT = 1VP-P
VOUT = 2.5VP-P
VOUT = 1VP-P
-9
-9
VOUT = 2.5VP-P
-12
-12
0.1
1
10
100
1000
10000
0.1
1
10
100
1000
10000
Frequency (kHz)
Frequency (kHz)
Figure 8. Frequency Response at G = 2
Figure 9. Frequency Response at G = 300
REV1A
9/19
XR18910
Typical Performance Characteristics (Continued)
T = 25°C, V = 3.3V, V = 1.8V, R = 10kΩ to 1.5V, G = 760, unless otherwise noted.
A
CC
DD
L
3.5
3
4
3
2
1
0
G = 2
Current Sense Mode Active
2.5
2
VCC = 3.3V
VCC = 5V
1.5
0
5
10
15
20
25
0
10
20
30
ILDO (mA)
40
50
ILDO (mA)
Figure 10. LDO Current vs. Output Voltage
Figure 11. LDO Output Current
5
4
1.55
1.5
G = 2
3
2
1.45
1.4
G = 2
1
G = 300
G = 760
0
-1
1.35
-10
-5
0
5
10
0.25
0.75
1.25
1.75
2.25
2.75
Input Common Mode Voltage (V)
Output Current (mA)
Figure 12. Output Offset Voltage vs. Output Current
Figure 13. Output Offset vs. Input Common Mode Voltage
2.5
2
100
G = 760
90
80
70
60
50
40
30
20
10
0
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0.01
0.1
1
10
100
1000
0
2
4
6
8
10
Time (seconds)
Frequency (kHz)
Figure 14. Input Voltage Noise vs. Frequency
Figure 15. 0.1Hz to 10Hz RTI Voltage Noise
REV1A
10/19
XR18910
Typical Performance Characteristics (Continued)
T = 25°C, V = 3.3V, V = 1.8V, R = 10kΩ to 1.5V, G = 760, unless otherwise noted.
A
CC
DD
L
4
3.5
3
2.5
2
G = 2
Stop Time = 1% Settling
Stop Time = 1% Settling
SDA
1.5
1
2.5
2
DUT Output
DUT Output
SDA
1.5
1
0.5
0
Start Time = 50% Acknowledge
0.5
0
Start Time = 50% Acknowledge
-0.5
0
5
10
15
20
0
5
10
Time (µs)
15
20
Time (µs)
Figure 16. Sleep to Wake Time (DUT Output)
Figure 17. Set-up Time - from G = 2 to G = 300
(DUT Output)
4
3.5
3
3.5
3
2.5
2
LDO Output
SDA
Stop Time = 1% Settling
2.5
2
1.5
1
1.5
1
LDO Output
SDA
Stop Time = 1% Settling
0.5
0
0.5
0
Start Time = 50% Acknowledge
Start Time = 50ꢀ Acknowledge
-0.5
-0.5
0
50
100
150
Time (µs)
200
250
0
10
20
30
Time (µs)
40
50
Figure 18. LDO Enable to Disable Time
Figure 19. LDO Disable to Enable Time
REV1A
11/19
XR18910
Functional Block Diagram
V
LDO Output
CC
1.5V
Reference
LDO Enable
LDO Select ( 3V, 2.65V )
AGND
PGA
Input 1 +/-
Input 2 +/-
Output
Input 8 +/-
10-Bit Offset DAC
VDD
SDA
SCL
2
I C Serial Digital Interface
DGND
Figure 20. Functional Block Diagram
Application Information
The XR18910 also provides the ability to monitor the LDO
current. When the XR18910 is in current sense mode, an
internal 2:1 MUX allows a voltage proportional to the LDO
current to be present at the output. Once all channels have
been calibrated, the LDO current can be used to indirectly
monitor any voltage or resistive changes seen by the inputs.
The XR18910 sensor interface includes a 8:1 differential
multiplexer (MUX), a programmable gain instrumentation
amplifier, a 10-bit offset correction DAC and an LDO. An
I2C interface controls the many functions and features of the
XR18910. The XR18910 is designed to integrate multiple
bridge sensors with an ADC/MCU or FPGA.
The XR18910 also includes an internal 1.5V reference that
is used by the internal LDO circuitry and used to set the
referencevoltagefortheprogrammablegaininstrumentation
amplifier.
Each bridge sensor connected to the XR18910 has its
own inherent offset that if not calibrated out can decrease
sensitivityandoverallperformanceofthesensorsystem.The
on-board DAC introduces an offset into the instrumentation
amplifier to calibrate the offset voltage generated by the
sensors. An independent offset can be set for each of the
8 channels. Only the offset voltage of the active channel is
applied to the PGA.
During sleep mode, the analog components of the XR18910
are powered down for added power savings.
The XR18910 offers many functions, each controlled by the
I2C compatible serial interface:
■■
The programmable gain instrumentation amplifier offers 8
selectable gains from 2V/V to 760V/V to amplify the signal
such that it falls within the input range of the ADC.
Input Selection
■■
Gain Selection
■■
Offset Correction
An integrated LDO provides a regulated voltage to power
the input bridge sensors and is selectable, between 3V and
2.65V. The LDO can be set to turn off when the XR18910 is
in sleep mode to save power.
■■
LDO Enable/Select
■■
Current Sense Mode
■■
Sleep Mode (analog power down)
REV1A
12/19
XR18910
Application Information (Continued)
I2C Bus Interface
Stop Condition
The I2C-bus interface consists of two lines: serial data (SDA)
and serial clock (SCL). The XR18910 works as a slave and
supports both standard mode transfer rates (100 kbps) and
fast mode transfer rates (400 kbps) as defined in the I2C-
Bus specification. The I2C-bus interface follows all standard
I2C protocols. Some information is provided below, for
additional information, refer to the I2C-bus specifications.
To signal the end of the data transfer, the master generates
a stop condition by pulling the SDA line from low to high
while the SCL line is high, as shown in Figure 21.
Figures 22 and 23 illustrate a write and a read cycle. For
complete details, see the I2C-bus specifications.
SLAVE
ADDRESS
REGISTER
ADDRESS
S
W
A
A
nDATA
A
P
NOTES:
SDA
SCL
White Block = host to XR18910, Orange Block = XR18910 to host.
Figure 22. Master Writes to Slave (XR18910)
S
P
START condition
STOP condition
SLAVE
ADDRESS
REGISTER
ADDRESS
SLAVE
ADDRESS
LAST
DATA
S
W A
A S
R A nDATA
A
NA P
Figure 21. I2C Start and Stop Conditions
NOTES:
White Block = host to XR18910, Orange Block = XR18910 to host.
The basic I2C access cycle for the XR18910 consists of:
■■
Figure 23. Master Reads from Slave (XR18910)
I2C Bus Addressing
A start condition
■■
A slave address cycle
The XR18910 uses a 7-bit address space. For the standard
XR18910, the default address is 0x67 (0110 111). There
are three alternative addresses available to help insure that
the XR18910 can be identified from the other devices on
the I2C-bus. Table 4 shows the different addresses that are
available.
■■
Zero, one, or two data cycles - depending on the XR18910
register accessed
■■
A stop condition
Start Condition
The master initiates data transfer by generating a start
condition. The start condition is when a high-to-low transition
occurs on the SDA line while SCL is high, as shown in
Figure 21.
Table 4. XR18910 I2C Address Map
I2C Address
Orderable Part Number
0x67 (0110 111x)
0x66 (0110 110x)
0x65 (0110 101x)
0x64 (0110 100x)
XR18910IL-67
XR18910IL-66
XR18910IL-65
XR18910IL-64
Slave Address Cycle
After the start condition, the first byte sent by the master
is the 7-bit address and the read/write direction bit R/W
on the SDA line. If the address matches the XR18910’s
internal fixed address, the XR18910 will respond with an
acknowledge by pulling the SDA line low for one clock cycle
while SCL is high.
A read or write transaction is determined by bit-0 of the
slave address, (shown as an “x” in the table above). If bit-0
is ’0’, then it is a write transaction. If bit-0 is ’1’, then it is a
read transaction.
Data Cycle
After the master detects this acknowledge, the next byte
transmitted by the master is the sub-address. This 8-bit
sub-address contains the address of the register to access.
The XR18910 Register List is shown in Table 1. Depending
on the register accessed, there will be up to two additional
data bytes transmitted by the master. Refer to the “Byte of
Parameter” column in the Register Table. The XR18910 will
respond to each write with an acknowledge.
An I2C sub-address is sent by the I2C master following the
slave address. The sub-address contains the XR18910
register address being accessed. Table 1 illustrates the
available XR18910 register addresses.
After the last read or write transaction, the I2C-bus master
will set the SCL signal back to its idle state (HIGH).
REV1A
13/19
XR18910
Application Information (Continued)
Inputs and Input Selection
Gain Selection
The XR18910 includes 8 differential inputs and a 8:1
differential MUX that is controlled by an I2C compatible 2
wire serial interface. The XR18910 is designed to accept 8
differential inputs.
The XR18910 offers 8 selectable fixed gains ranging from
2V/V to 760V/V. When the XR18910 is powered-up, the
default gain is 2V/V.
The gain is selected via I2C using the register address 0x06
followed by another byte of data to select the gain. Refer
to the Register List in Table 1 and the Gain Register list in
Table 3.
■■
If fewer than 4 differential inputs are required, tie the unused
inputs to GND.
■■
If single ended inputs are required, tie the unused inputs to 1.5V.
The input common mode range of the XR18910 is typically
0.6V to 2.4V when running from a 3.3V supply. The
XR18910 offers a very wide gain range. In most cases, the
output voltage swing will be the limiting factor.
Example: The example below illustrates how to select a
gain of 150V/V.
To start communication with the XR18910, repeat steps 1-3 as
shown in the Inputs and Input Selection section on page 14.
When the XR18910 is powered-up, the default input
selected is Channel 1.
Inputs are selected via I2C using one of 8 register addresses
0x10, 0x12, 0x14, 0x15, 0x18, 0x1A, 0x1C, or 0x1E. Refer
to the Register List in Table 1.
Step 4
7
0
6
0
5
0
4
0
3
0
2
1
1
1
0
0
Master sends address of register to access
Gain Select register address =
0x06
Step 5
9
A
Example: The example below illustrates how to select
Channel 4.
XR18910 sends acknowledge
Step 1
0
S
Since the Gain Select register was accessed, the XR18910
is expecting another byte of data from the master to complete
the command. Refer to the “Byte of Parameter” column in
the Register List (Table 1). D0 thru D2 are used to select
the gain. Refer to the Gain Register list in Table 3, 150V/V
is D2 = 1, D1 = 0, and D0 = 0. This translates to a hex code
of 0x04, since a full byte of data (8-bits) will be sent.
Master sends start condition
Step 2
7
0
6
1
5
1
4
0
3
1
2
1
7
1
1
0
0
Master sends XR18910 address with write bit
6
W
7-bit XR18910 Address = 0x67
Step 6
7
0
6
0
5
0
4
0
3
0
2
1
1
0
0
0
Step 3
9
A
Master sends gain register data to select G=150
XR18910 sends acknowledge
Gain of 150V/V = 0x04
Step 4
7
0
6
0
5
0
4
1
3
0
2
1
1
0
0
1
Step 7
9
A
Master sends address of register to access
XR18910 sends acknowledge
Select_Input 4 register address
= 0x15
Step 8
0
P
Master sends stop condition
Step 5
9
A
XR18910 sends acknowledge
NOTES:
White Block = host to XR18910, Orange Block = XR18910 to host, Grey Block =
Notes.
Step 6
0
P
Master sends stop condition
NOTES:
White Block = host to XR18910, Orange Block = XR18910 to host, Grey Block =
Notes.
REV1A
14/19
XR18910
Application Information (Continued)
Offset Correction
The XR18910 has a 10-bit offset correction DAC that can
be used to provide digital calibration on each of the 8 inputs.
Only the offset voltage of the active channel is applied to
the PGA.
The DAC offset of each channel is controlled by the I2C
compatible interface. At any time, the master can read or
write to any of the DAC offset registers. The DAC offset
for each channel is set via I2C using the register addresses
0x20 thru 0x2F followed by another two bytes of data to set
the polarity and value of the offset voltage. Refer to the
Register List in Table 1.
Step 5
9
A
XR18910 sends acknowledge
Since a DAC Offset register was accessed, the XR18910
is expecting another two bytes of data from the master to
complete the command. Refer to the “Byte of Parameter”
column in the Register List (Table 1). D0 thru D9 are used
to set the offset voltage and D10 is used to set the sign of
the offset voltage, 0 = positive and 1 = negative. Refer to
the DAC Offset register list in Table 2.
To determine what DAC output level corresponds to 75mV,
use the following equation:
A
560mV offset correction range is available. The full
range of the DAC offset is only available at a gain of 2.
At higher gains, the output voltage range of the XR18910
will be exceeded if the full range of the DAC offset is used.
The internal 10-bit DAC allows 1,024 different offset voltage
settings between 0mV and 560mV. The polarity of the
offset correction is set with an additional bit. The unit offset
is determined by the following:
Desired Offset
Unit Offset
75mV
547µV
=
=
=
DAC Output Level
137
A decimal value of 137 corresponds to 75mV. Therefore:
■■
0x89 (hex) or 0 00 1000 1001 (binary) applies a 75mV offset
■■
0x489 (hex) or 1 00 1000 1001 (binary) applies a -75mV offset
15 14 13 12 11 10
9
8
Step 6
Total Offset
DAC Output Levels
560mV
1024
=
=
547µV
=
Unit Offset
Master sends 1st byte of
DAC offset register data to
select an offset of +75mV
0
0
0
0
0
0
0
0
From Table 3:
2 MSBs of 10-bit
DAC output level that
corresponds to 137 (0x89)
■■
0x00 (hex) or 0 00 0000 0000 (binary) applies a 0mV offset
0x3FF (hex) or 0 11 1111 1111 (binary) applies a +560mV offset
0x7FF (hex) or 1 11 1111 1111 (binary) applies a -560mV offset
Sign
■■
■■
Step 7
9
A
Each DAC output level provides an additional 547µV of
offset. To determine what DAC output level corresponds to
a specific desired offset, use the following equation:
XR18910 sends acknowledge
7
1
6
5
0
4
0
3
1
2
0
1
0
0
1
Step 8
Master sends 2nd byte of DAC offset register data
to select an offset of +75mV
0
Desired Offset
=
x
Unit Offset
8 LSBs of 10-bit DAC output level
that corresponds to 137 (0x89)
See example below for additional information.
Example: The example below illustrates how to set the
DAC offset for channel 4 to a value of 75mV.
Step 9
9
A
XR18910 sends acknowledge
To start communication with the XR18910, repeat steps 1-3
as shown in the Inputs and Input Selection section on page
14.
Step 10
0
P
Master sends stop condition
Step 4
7
0
6
0
5
1
4
0
3
0
2
1
1
0
0
1
NOTES:
White Block = host to XR18910, Orange Block = XR18910 to host, Grey Block =
Notes.
Master sends address of register to access
DAC4 register address = 0x25
REV1A
15/19
XR18910
Application Information (Continued)
LDO Enable / Select (Power to External Bridge Sensors)
The XR18910 includes an on-board LDO that provides a
regulated voltage that can be used to power external input
bridge sensors. Two voltage options are available, 3V and
2.65V. The LDO voltage is selected via the I2C compatible
two-wire serial interface.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Step 6
Master sends code to select LDO
voltage of 2.65V and Enable LDO
during Sleep Mode
0 = Enable 1 = 2.65V
When the XR18910 is powered-up, the default LDO voltage
is 3V.
Step 7
9
A
XR18910 sends acknowledge
When the XR18910 is active (not in sleep mode), the LDO
is always on. If the LDO voltage is not used, the LDO output
can be left floating. The LDO can either stay on or shut
down while the XR18910 is in Sleep Mode.
Step 8
0
P
Master sends stop condition
NOTES:
■■
Set LDO to shut down while XR18910 is in Sleep Mode to
White Block = host to XR18910, Orange Block = XR18910 to host, Grey Block =
Notes.
save power
■■
Set LDO to stay on while XR18910 is in Sleep Mode to
improve wake-up time
Current Sense Mode (Monitoring the LDO Current)
Current Sense Mode is activated via I2C using the register
address 0x08. When activated, the LDO current is sensed
and a proportional voltage is present at the output of the
XR18910 (ILDO = VOUT/RL). Current Sense Mode stays
active until the XR18910 receives any input select command
0x10, 0x12, 0x14, 0x15, 0x18, 0x1A, 0x1C, or 0x1E).
The LDO voltage and disable setting are selected via I2C
using the register address 0x07 followed by another byte
of data to select the voltage and disable setting. Refer to
the Register List in Table 1 and the example below for more
information.
Example: The example below illustrates how to select an
LDO voltage of 2.65V and keep the LDO enabled during
Sleep Mode.
Current sense mode can be used to monitor the change
over time of the bridge impedance.
To start communication with the XR18910, repeat steps 1-3 as
shown in the Inputs and Input Selection section on page 14.
Sleep Mode (Analog Power Down)
Sleep mode is activated via I2C using the register address
0x05. When activated, the XR18910 will enter sleep mode.
During sleep mode, the analog portion of the XR18910
is disabled. All register settings are retained during sleep
mode.
Step 4
7
0
6
0
5
0
4
0
3
0
2
1
1
1
0
1
Master sends address of register to access
LDO Settings register address
= 0x07
During sleep mode, the nominal supply current will drop
below 70µA (with LDO on) and below 45µA (with LDO off).
Step 5
9
A
XR18910 sends acknowledge
During sleep mode, the master can read the value in any
register that saves a value during sleep mode. The only
I2C commands that can be received or processed are the
SLEEP_OUT (wake up) command (0x04) and the LDO
on/off and voltage command (0x07). All other register
addresses will be ignored.
Since the LDO Settings register was accessed, the
XR18910 is expecting another byte of data from the master
to complete the command. Refer to the “Byte of Parameter”
column in the Register List (Table 1). D0 and D1 are used to
select the LDO voltage and enable/disable the LDO during
Sleep Mode. Bit 0 (D0) controls the LDO voltage (0: 3V;
1: 2.65V). Bit 1 (D1) is only applicable in Sleep Mode. Bit
1 controls whether the LDO shuts down or stays on during
sleep mode (0: Enable; 1: Disable). When the XR18910 is
active, the LDO is always on.
Register address 0x04 is used to return to normal operation
(exit Sleep Mode).
By default, the XR18910 is active.
REV1A
16/19
XR18910
Application Information (Continued)
Typical Application – 8:1 Bridge Sensor Interface
The XR18910 was designed to interface multiple bridge sensors with a microcontroller or FPGA as illustrated in Figure 24.
The bridge output signal is differential (V and V ). Ideally, the unloaded bridge output is zero (V and V are identical).
O+
O-
O+
O-
However, in-exact resistive values result in a difference between V and V . This bridge offset voltage can be substantial
O+
O-
and vary between sensors. The XR18910 provides the ability to calibrate the bridge offset on each of the 8 bridge sensors
using the on-board DAC.
m
DD
m
CC
5.8μF
5.8μF
+
+
6.1μF
6.1μF
BRDG
mCC
mDD
6.1μF
16k
BRIDGE 8
LDO
IN8+
IN8-
OUT
INA /
PGA
ADC
µC
16nF
8:1
MUX
±±560m
OFFSET TRIM
m
m
DD
DD
BRIDGE 1
16-BIT
DAC
PGA
4.7k
4.7k
IN1+
IN1-
SDA
SCL
2
I C
CONTROL
XR18910
AGND
DGND
Figure 24. 8:1 Bridge Sensor Interface
Layout Considerations
General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for
high frequency layout:
■■
Include 6.8µF and 0.1µF ceramic capacitors for power supply decoupling
■■
Place the 6.8µF capacitor within 0.75 inches of the power pin
■■
Place the 0.1µF capacitor within 0.1 inches of the power pin
■■
Connection to the exposed pad is not required. Exposed pad can be connected to ground (GND).
■■
Minimize all trace lengths to reduce series inductances
REV1A
17/19
XR18910
Package Description
REV1A
18/19
XR18910
Ordering Information
Operating
Temperature Range
Environmental
Rating
Part Number
Package
Packaging Quantity
XR18910IL-67
Tray
XR18910ILMTR-67
XR18910ILTR-67
XR18910IL-66
250/tape and reel
3k/tape and reel
Tray
XR18910ILMTR-66
XR18910ILTR-66
XR18910IL-65
250/tape and reel
3k/tape and reel
Tray
RoHS-compliant
halogen free
-40°C to 85°C
3.5mm x 3.5mm QFN-24
XR18910ILMTR-65
XR18910ILTR-65
XR18910IL-64
250/tape and reel
3k/tape and reel
Tray
XR18910ILMTR-64
XR18910ILTR-64
XR18910ILEVB
250/tape and reel
3k/tape and reel
Evaluation board
www.exar.com
48760 Kato Road
Fremont, CA 94538
USA
Tel.: +1 (510) 668-7000
Fax: +1 (510) 668-7001
Email: hpatechsupport@exar.com
Exar Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. Exar Corporation conveys
no license under any patent or other right and makes no representation that the circuits are free of patent infringement. While the information in this publication has been
carefully checked, no responsibility, however, is assumed for inaccuracies.
Exar Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected
to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Exar Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of
Exar Corporation is adequately protected under the circumstances.
Reproduction, in part or whole, without the prior written consent of Exar Corporation is prohibited. Exar, XR and the XR logo are registered trademarks of Exar Corporation.
All other trademarks are the property of their respective owners.
©2016 Exar Corporation
XR18910_DS
REV1A
19/19
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