XR16V554_技术文档

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

MAY 2007

REV. 1.0.1

FEATURES

GENERAL DESCRIPTION

• Pin-to-pin compatible with ST16C454, ST16C554,

The XR16V554 (V554) is

a

quad Universal

TI’s TL16C554A and Philip’s SC16C554B

Asynchronous Receiver and Transmitter (UART) with

16 bytes of transmit and receive FIFOs, selectable

receive FIFO trigger levels and data rates of up to 4

Mbps at 3.3 V. Each UART has a set of registers that

provide the user with operating status and control,

receiver error indications, and modem serial interface

controls. An internal loopback capability allows

onboard diagnostics. The V554 is available in a 48-

pin QFN, 64-pin LQFP, 68-pin PLCC and 80-pin

LQFP packages. The 64-pin and 80-pin packages

only offer the 16 mode interface, but the 48- and 68-

pin packages offer an additional 68 mode interface

which allows easy integration with Motorola

processors. The XR16V554IV (64-pin) offers three

state interrupt output while the XR16V554DIV

provides continuous interrupt output. The XR16V554

is compatible with the industry standard ST16C554.

• Intel or Motorola Data Bus Interface select

• Four independent UART channels

■ Register Set Compatible to 16C550

■ Data rates of up to 4 Mbps at 3.3 V and 3.125

Mbps at 2.5 V

■ 16 byte Transmit FIFO

■ 16 byte Receive FIFO with error tags

■ 4 Selectable RX FIFO Trigger Levels

■ Full modem interface

• 2.25V to 3.6V supply operation

• Crystal oscillator or external clock input

APPLICATIONS

• Portable Appliances

• Telecommunication Network Routers

• Ethernet Network Routers

• Cellular Data Devices

• Factory Automation and Process Controls

FIGURE 1. XR16V554 BLOCK DIAGRAM

2.25V to 3.6 V VCC

GND

* 5 Volt Tolerant Inputs

( Except XTAL1input)

A2:A0

D7:D0

IOR#

UART Channel A

16 Byte TX FIFO

UART

Regs

TXA, RXA, DTRA#,

DSRA#, RTSA#, CTSA#,

CDA#, RIA#

IOW#

CSA#

CSB#

TX &RX

BRG

16 Byte RX FIFO

CSC#

CSD#

INTA

TXB, RXB, DTRB#,

DSRB#, RTSB#, CTSB#,

CDB#, RIB#

UART Channel B

(same as Channel A)

Data Bus

Interface

INTB

INTC

TXC, RXC, DTRC#,

DSRC#, RTSC#, CTSC#,

CDC#, RIC#

UART Channel C

(same as Channel A)

INTD

TXRDY#A-D

RXRDY#A-D

Reset

TXD, RXD, DTRD#,

DSRD#, RTSD#, CTSD#,

CDD#, RID#

UART Channel D

(same as Channel A)

16 68#

/

XTAL1

XTAL2

Crystal Osc Buffer

/

INTSEL

554BLK

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

REV. 1.0.1

FIGURE 2. PIN OUT ASSIGNMENT FOR 68-PIN PLCC PACKAGES IN 16 AND 68 MODE AND 64-PIN LQFP PACKAGES

DSRA# 10

CTSA# 11

DTRA# 12

VCC 13

60

59

58

DSRD#

CTSD#

DTRD#

DSRA# 10

CTSA# 11

DTRA# 12

VCC 13

60 DSRD#

59 CTSD#

58 DTRD#

57 GND

RTSA# 14

IRQ# 15

CS# 16

56

RTSD#

RTSA# 14

INTA 15

CSA# 16

TXA 17

56 RTSD#

55 INTD

55 N.C.

54 N.C.

53 TXD

52 N.C.

51 TXC

50 A4

49 N.C.

54 CSD#

53 TXD

XR16V554

68-pin PLCC

Motorola Mode

XR16V554

68-pin PLCC

Intel Mode

TXA 17

R/W# 18

TXB 19

IOW# 18

TXB 19

52 IOR#

51 TXC

(16/68# pin connected to GND)

(16/68# pin connected to VCC)

A3 20

CSB# 20

INTB 21

RTSB# 22

GND 23

50 CSC#

49 INTC

N.C. 21

RTSB# 22

GND 23

DTRB# 24

CTSB# 25

DSRB# 26

48

RTSC#

48 RTSC#

47 VCC

46

45

44

DTRC#

DTRB# 24

CTSB# 25

DSRB# 26

46 DTRC#

45 CTSC#

44 DSRC#

CTSC#

DSRC#

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DSRD#

CTSD#

DTRD#

GND

DSRA#

CTSA#

DTRA#

VCC

3

4

RTSA#

INTA

5

RTSD#

INTD

6

CSA#

TXA

7

CSD#

TXD

XR16V554/554D

64-pin TQFP

Intel Mode Only

8

IOR#

IOW#

TXB

9

TXC

10

11

12

13

14

15

16

CSC#

INTC

CSB#

INTB

RTSC#

VCC

RTSB#

GND

DTRB#

CTSB#

DTRC#

CTSC#

2

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

FIGURE 3. PIN OUT ASSIGNMENT FOR 48-PIN QFN PACKAGE AND 80-PIN LQFP PACKAGE

RXD

36

35

34

33

36

35

34

33

CTSA#

VCC

1

2

CTSA#

VCC

1

2

CTSD#

GND

CTSD#

GND

RTSA#

INTA

CSA#

TXA

3

RTSA#

INTA

CSA#

TXA

3

4

5

6

7

8

9

4

5

6

7

8

9

RTSD#

32 INTD

CSD#

32 INTD

CSD#

XR16V554

48-pin QFN

Intel Mode

XR16V554

48-pin QFN

Motorola Mode

31

IOW#

TXB

IOW#

TXB

30 TXD

(16/68# pin connected to VCC)

(16/68# pin connected to GND)

29 IOR#

CSB#

28

27

26

25

CSB#

28

27

26

25

TXC

INTB

RTSB#

CTSB#

INTB

RTSB#

CTSB#

CSC#

INTC

CSC#

INTC

10

11

12

10

11

12

RTSC#

N.C.

60

NC

1

DSRD#

59

NC

2

DSRA#

CTSA#

DTRA#

VCC

58 CTSD#

3

DTRD#

56 GND

57

4

5

RTSD#

55

6

RTSA#

INTA

54 INTD

53 CSD#

7

8

XR16V554

CSA#

TXA

TXD

IOR#

TXC

52

51

50

9

80-pin LQFP

Intel Mode Only

10

11

12

13

14

15

16

17

18

19

20

IOW#

TXB

49 CSC#

48 INTC

CSB#

INTB

RTSC#

VCC

47

46

45

44

43

42

41

RTSB#

GND

DTRC#

CTSC#

DTRB#

CTSB#

DSRB#

DSRC#

N.C.

NC

N.C.

3

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

ORDERING INFORMATION

REV. 1.0.1

OPERATING TEMPERATURE

RANGE

PART NUMBER

PACKAGE

DEVICE STATUS

XR16V554IJ

XR16V554IV

68-Lead PLCC

64-Lead LQFP

-40°C to +85°C

Active

XR16V554DIV

XR16V554IL

64-Lead LQFP

48-pin QFN

-40°C to +85°C

Active

XR16V554IV80

80-Lead LQFP

PIN DESCRIPTIONS

Pin Description

48-QFN 64-LQFP 68-PLCC 80-LQFP

NAME

TYPE

DESCRIPTION

PIN #

PIN#

PIN #

DATA BUS INTERFACE

A2

A1

A0

15

16

17

22

23

24

32

33

34

28

29

30

I

Address data lines [2:0]. These 3 address lines select

one of the internal registers in UART channel A-D dur-

ing a data bus transaction.

D7

D6

D5

D4

D3

D2

D1

D0

46

45

44

43

42

41

40

39

60

59

58

57

56

55

54

53

5

4

75

74

73

72

71

70

69

68

I/O Data bus lines [7:0] (bidirectional).

3

2

1

68

67

66

IOR#

29

40

52

51

I

When 16/68# pin is HIGH, the Intel bus interface is

selected and this input becomes read strobe (active

low). The falling edge instigates an internal read cycle

and retrieves the data byte from an internal register

pointed by the address lines [A2:A0], puts the data byte

on the data bus to allow the host processor to read it on

the rising edge.

(VCC)

When 16/68# pin is LOW, the Motorola bus interface is

selected and this input is not used and should be con-

nected to VCC.

IOW#

7

9

18

11

I

When 16/68# pin is HIGH, it selects Intel bus interface

and this input becomes write strobe (active low). The

falling edge instigates the internal write cycle and the

rising edge transfers the data byte on the data bus to

an internal register pointed by the address lines.

(R/W#)

When 16/68# pin is LOW, the Motorola bus interface is

selected and this input becomes read (HIGH) and write

(LOW) signal.

CSA#

(CS#)

5

7

16

9

I

When 16/68# pin is HIGH, this input is chip select A

(active low) to enable channel A in the device.

When 16/68# pin is LOW, this input becomes the chip

select (active low) for the Motorola bus interface.

4

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

Pin Description

48-QFN 64-LQFP 68-PLCC 80-LQFP

NAME

TYPE

DESCRIPTION

PIN #

PIN#

PIN #

CSB#

(A3)

9

11

20

13

I

When 16/68# pin is HIGH, this input is chip select B

(active low) to enable channel B in the device.

When 16/68# pin is LOW, this input becomes address

line A3 which is used for channel selection in the Motor-

ola bus interface.

CSC#

(A4)

27

38

50

49

I

When 16/68# pin is HIGH, this input is chip select C

(active low) to enable channel C in the device.

When 16/68# pin is LOW, this input becomes address

line A4 which is used for channel selection in the Motor-

ola bus interface.

CSD#

(VCC)

31

4

42

6

54

15

53

8

When 16/68# pin is HIGH, this input is chip select D

(active low) to enable channel D in the device.

When 16/68# pin is LOW, this input is not used and

should be connected VCC.

INTA

O

When 16/68# pin is HIGH for Intel bus interface, this

ouput becomes channel A interrupt output. The output

state is defined by the user and through the software

setting of MCR[3]. INTA is set to the active mode when

MCR[3] is set to a logic 1. INTA is set to the three state

mode when MCR[3] is set to a logic 0 (default). See

MCR[3].

(IRQ#)

(OD)

When 16/68# pin is LOW for Motorola bus interface,

this output becomes device interrupt output (active low,

open drain). An external pull-up resistor is required for

proper operation.

INTB

INTC

INTD

(N.C.)

10

26

32

12

37

43

21

49

55

14

48

54

O

When 16/68# pin is HIGH for Intel bus interface, these

ouputs become the interrupt outputs for channels B, C,

and D. The output state is defined by the user through

the software setting of MCR[3]. The interrupt outputs

are set to the active mode when MCR[3] is set to a logic

1 and are set to the three state mode when MCR[3] is

set to a logic 0 (default). See MCR[3].

When 16/68# pin is LOW for Motorola bus interface,

these outputs are unused and will stay at logic zero

level. Leave these outputs unconnected.

TXRDY#

RXRDY#

-

39

38

35

34

O

Transmitter Ready (active low). This output is a logi-

cally ANDed status of TXRDY# A-D. See Table 5. If this

output is unused, leave it unconnected.

Receiver Ready (active low). This output is a logically

ANDed status of RXRDY# A-D. See Table 5. If this out-

put is unused, leave it unconnected.

5

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

Pin Description

REV. 1.0.1

48-QFN 64-LQFP 68-PLCC 80-LQFP

NAME

TYPE

DESCRIPTION

PIN #

PIN#

PIN #

INTSEL

38

-

65

67

I

Interrupt Select (active high, input with internal pull-

down).

When 16/68# pin is HIGH for Intel bus interface, this pin

can be used in conjunction with MCR bit-3 to enable or

disable the INT A-D pins or override MCR bit-3 and

enable the interrupt outputs. Interrupt outputs are

enabled continuously when this pin is HIGH. MCR bit-3

enables and disables the interrupt output pins. In this

mode, MCR bit-3 is set to a logic 1 to enable the contin-

uous output. See MCR bit-3 description for full detail.

This pin must be LOW in the Motorola bus interface

mode. For the 64 pin packages, this pin is bonded to

VCC internally in the XR16V554D so the INT outputs

operate in the continuous interrupt mode. This pin is

bonded to GND internally in the XR16V554 and there-

fore requires setting MCR bit-3 for enabling the inter-

rupt output pins.

MODEM OR SERIAL I/O INTERFACE

TXA

TXB

TXC

TXD

6

8

17

19

51

53

10

12

50

52

O

I

UART channels A-D Transmit Data and infrared trans-

mit data. In this mode, the TX signal will be HIGH dur-

ing reset, or idle (no data).

10

39

41

28

30

RXA

RXB

RXC

RXD

48

13

22

36

62

20

29

51

7

77

25

37

65

UART channel A-D Receive Data. Normal receive data

input must idle HIGH.

29

41

63

RTSA#

RTSB#

RTSC#

RTSD#

3

5

14

22

48

56

7

O

I

UART channels A-D Request-to-Send (active low) or

general purpose output. If these outputs are not used,

leave them unconnected.

11

25

33

13

36

44

15

47

55

CTSA#

CTSB#

CTSC#

CTSD#

1

2

11

25

45

59

4

UART channels A-D Clear-to-Send (active low) or gen-

eral purpose input. These inputs should be connected

to VCC when not used.

12

23

35

16

33

47

18

44

58

DTRA#

DTRB#

DTRC#

DTRD#

-

3

12

24

46

58

5

O

I

UART channels A-D Data-Terminal-Ready (active low)

or general purpose output. If these outputs are not

used, leave them unconnected.

15

34

46

17

45

57

DSRA#

DSRB#

DSRC#

DSRD#

-

1

10

26

44

60

3

UART channels A-D Data-Set-Ready (active low) or

general purpose input. This input should be connected

to VCC when not used. This input has no effect on the

UART.

17

32

48

19

43

59

6

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

Pin Description

48-QFN 64-LQFP 68-PLCC 80-LQFP

NAME

TYPE

DESCRIPTION

PIN #

PIN#

PIN #

CDA#

CDB#

CDC#

CDD#

-

64

18

31

49

9

79

23

39

63

I

UART channels A-D Carrier-Detect (active low) or gen-

eral purpose input. This input should be connected to

VCC when not used. This input has no effect on the

UART.

27

43

61

RIA#

RIB#

RIC#

RID#

-

63

19

30

50

8

78

24

38

64

I

UART channels A-D Ring-Indicator (active low) or gen-

eral purpose input. This input should be connected to

VCC when not used. This input has no effect on the

UART.

28

42

62

ANCILLARY SIGNALS

XTAL1

18

25

35

31

I

Crystal or external clock input. Caution: this input is not

5V tolerant.

XTAL2

16/68#

19

14

26

-

36

31

32

-

O

I

Crystal or buffered clock output.

Intel or Motorola Bus Select (input with internal pull-up).

When 16/68# pin is HIGH, 16 or Intel Mode, the device

will operate in the Intel bus type of interface.

When 16/68# pin is LOW, 68 or Motorola mode, the

device will operate in the Motorola bus type of interface.

Motorola bus interface is not available on the 64 pin

package.

RESET

20

27

37

33

I

When 16/68# pin is HIGH for Intel bus interface, this

input becomes the Reset pin (active high). In this case,

a 40 ns minimum HIGH pulse on this pin will reset the

internal registers and all outputs. The UART transmitter

output will be held HIGH, the receiver input will be

ignored and outputs are reset during reset period

(Table 13). When 16/68# pin is at LOW for Motorola

bus interface, this input becomes Reset# pin (active

low). This pin functions similarly, but instead of a HIGH

pulse, a 40 ns minimum LOW pulse will reset the inter-

nal registers and outputs.

(RESET#)

Motorola bus interface is not available on the 64 pin

package.

VCC

2, 24, 37 4, 21, 35,

52

13, 30, 6, 30, 46, Pwr 2.25V to 3.6V power supply. All inputs, except XTAL1,

47, 64

66

are 5V tolerant.

GND

21, 47

14, 28, 6, 23, 40, 16, 36,

Pwr Power supply common, ground.

45, 61

57

56, 76

Center

Pad

N/A

Pwr

The center pad on the backside of the QFN package is

metallic and should be connected to GND on the PCB.

The thermal pad size on the PCB should be the approx-

imate size of this center pad and should be solder mask

defined. The solder mask opening should be at least

0.0025" inwards from the edge of the PCB thermal pad.

7

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

Pin Description

REV. 1.0.1

48-QFN 64-LQFP 68-PLCC 80-LQFP

NAME

TYPE

DESCRIPTION

PIN #

PIN#

PIN #

N.C.

-

1, 2, 20,

21, 22,

26, 27,

40, 41,

42, 60,

61, 62,

80

No Connection. These pins are not used in either the

Intel or Motorola bus modes.

Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.

8

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

1.0 PRODUCT DESCRIPTION

The XR16V554 (V554) integrates the functions of 4 enhanced 16C550 Universal Asynchrounous Receiver and

Transmitter (UART). Each UART is independently controlled and has its own set of device configuration

registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.

Additionally, each UART channel has 16 bytes of transmit and receive FIFOs, programmable baud rate

generator and data rate up to 4 Mbps at 3.3 V. The XR16V554 can operate from 2.25 to 3.6 volts. The V554 is

fabricated with an advanced CMOS process.

Enhanced FIFO

The V554 QUART provides a solution that supports 16 bytes of transmit and receive FIFO memory, instead of

one byte in the ST16C454. The V554 is designed to work with high performance data communication systems,

that require fast data processing time. Increased performance is realized in the V554 by the larger transmit and

receive FIFOs and Receiver FIFO trigger level control. This allows the external processor to handle more

networking tasks within a given time. This increases the service interval giving the external CPU additional time

for other applications and reducing the overall UART interrupt servicing time.

Data Bus Interface, Intel or Motorola Type

The V554 provides a single host interface for the 4 UARTs and supports Intel or Motorola microprocessor

(CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type

of CPUs using IOR#, IOW# and CSA#, CSB#, CSC# or CSD# inputs for data bus operation. The Motorola bus

compatible interface instead uses the R/W#, CS#, A3 and A4 signals for data bus transactions. Few data bus

interface signals change their functions depending on user’s selection, see pin description for details. The Intel

and Motorola bus interface selection is made through the pin 16/68#.

Data Rate

The V554 is capable of operation up to 4 Mbps at 3.3V. The device can operate at 3.3V with a crystal oscillator

of up to 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of 64 MHz on XTAL1 pin. With a

typical crystal of 14.7456 MHz and through a software option, the user can set the sampling rate for data rates

of up to 921.6 Kbps.

Enhanced Features

The rich feature set of the V554 is available through the internal registers. Selectable receive FIFO trigger

levels, programmable baud rates, infrared encoder/decoder interface and modem interface controls are all

standard features. In the 16 mode INTSEL and MCR bit-3 can be configured to provide a software controlled or

continuous interrupt capability. For backward compatibility to the ST16C554, the 64-pin LQFP does not have

the INTSEL pin. Instead, two different LQFP packages are offered. The XR16V554DIV operates in the

continuous interrupt enable mode by internally bonding INTSEL to VCC. The XR16V554IV operates in

conjunction with MCR bit-3 by internally bonding INTSEL to GND.

9

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

2.0 FUNCTIONAL DESCRIPTIONS

REV. 1.0.1

2.1

CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and

write transactions. The V554 data interface supports the Intel compatible types of CPUs and it is compatible to

the industry standard 16C550 UART. No clock (oscillator nor external clock) is required for a data bus

transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs.

All four UART channels share the same data bus for host operations. A typical data bus interconnection for

Intel and Motorola mode is shown in Figure 4.

FIGURE 4. XR16V554 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

VCC

TXA

RXA

DTRA#

RTSA#

CTSA#

DSRA#

CDA#

RIA#

UART

Channel A

Serial Interface of

RS-232

A0

A1

A2

A0

A1

A2

IOR#

IOW#

UART

IOW#

Channel B

Similar

CSA#

CSB#

CSC#

CSD#

UART_CSA#

UART_CSB#

UART_CSC#

UART_CSD#

to Ch A

UART

Channel C

Serial Interface of

RS-232

Similar

to Ch A

UART_INTA

UART_INTB

UART_INTC

UART_INTD

INTA

INTB

INTC

INTD

UART

Channel D

Similar

to Ch A

UART_RESET

VCC

RESET

16/68#

GND

Intel Data Bus (16 Mode) Interconnections

VCC

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

TXA

RXA

DTRA#

RTSA#

CTSA#

DSRA#

CDA#

RIA#

D6

UART

Channel A

Serial Interface of

RS-232

D7

A0

A1

A0

A1

A2

A3

A4

CSB#

CSC#

CSD#

UART

Channel B

VCC

Similar

to Ch A

IOR#

IOW#

R/W#

UART

Channel C

CSA#

UART_CS#

Similar

to Ch A

Serial Interface of

RS-232

VCC

UART_IRQ#

INTA

UART

Channel D

INTB

INTC

INTD

(no connect)

Similar

to Ch A

UART_RESET#

RESET#

16/68#

GND

Motorola Data Bus (68 Mode) Interconnections

10

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

2.2

Device Reset

The RESET input resets the internal registers and the serial interface outputs in all channels to their default

state (see Table 13). An active high pulse of longer than 40 ns duration will be required to activate the reset

function in the device. Following a power-on reset or an external reset, the V554 is software compatible with

previous generation of UARTs, 16C454 and 16C554.

2.3

Channel Selection

The UART provides the user with the capability to bi-directionally transfer information between an external

CPU and an external serial communication device. During Intel Bus Mode (16/68# pin is connected to VCC), a

logic 0 on chip select pins, CSA#, CSB#, CSC# or CSD# allows the user to select UART channel A, B, C or D

to configure, send transmit data and/or unload receive data to/from the UART. Selecting all four UARTs can be

useful during power up initialization to write to the same internal registers, but do not attempt to read from all

four uarts simultaneously. Individual channel select functions are shown in Table 1.

TABLE 1: CHANNEL A-D SELECT IN 16 MODE

CSA# CSB# CSC# CSD#

FUNCTION

1

0

1

0

1

0

1

0

1

0

1

0

1

0

UART de-selected

Channel A selected

Channel B selected

Channel C selected

Channel D selected

Channels A-D selected

During Motorola Bus Mode (16/68# pin is connected to GND), the package interface pins are configured for

connection with Motorola, and other popular microprocessor bus types. In this mode the V554 decodes two

additional addresses, A3 and A4, to select one of the four UART ports. The A3 and A4 address decode

function is used only when in the Motorola Bus Mode. See Table 2.

TABLE 2: CHANNEL A-D SELECT IN 68 MODE

CS#

A4

X

0

A3

X

0

FUNCTION

1

0

UART de-selected

Channel A selected

Channel B selected

Channel C selected

Channel D selected

0

1

0

1

11

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

REV. 1.0.1

2.4

Channels A-D Internal Registers

Each UART channel in the V554 has a set of enhanced registers for controlling, monitoring and data loading

and unloading. The configuration register set is compatible to those already available in the standard single

16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers

(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status

and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user

accessible scratchpad register (SPR). All the register functions are discussed in full detail later in “Section 3.0,

UART INTERNAL REGISTERS” on page 19.

2.5

INT Ouputs for Channels A-D

The interrupt outputs change according to the operating mode and enhanced features setup. Table 3 and 4

summarize the operating behavior for the transmitter and receiver. Also see Figure 18 through 23.

TABLE 3: INT PIN OPERATION FOR TRANSMITTER FOR CHANNELS A-D

FCR BIT-0 = 1 (FIFO ENABLED)

FCR BIT-0 = 0

FCR Bit-3 = 0

FCR Bit-3 = 1

(FIFO DISABLED)

(DMA Mode Disabled)

(DMA Mode Enabled)

INT Pin

LOW = a byte in THR

HIGH = THR empty

LOW = FIFO above trigger level

HIGH = FIFO below trigger level or

FIFO empty

HIGH = FIFO below trigger level or

FIFO empty

TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D

FCR BIT-0 = 0

(FIFO DISABLED)

FCR BIT-0 = 1 (FIFO ENABLED)

FCR Bit-3 = 0

FCR Bit-3 = 1

(DMA Mode Disabled)

(DMA Mode Enabled)

INT Pin

LOW = no data

HIGH = 1 byte

LOW = FIFO below trigger level

HIGH = FIFO above trigger level

LOW = FIFO below trigger level

HIGH = FIFO above trigger level

2.6

DMA Mode

The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not

mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of

the RXRDY# A-D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide

additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the

transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit

and receive FIFO in the DMA mode (FCR bit-3 = 1). When the transmit and receive FIFOs are enabled and the

DMA mode is disabled (FCR bit-3 = 0), the V554 is placed in single-character mode for data transmit or receive

operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by

loading or unloading the FIFO in a block sequence determined by the programmed trigger level. The following

table show their behavior. Also see Figure 18 through 23.

12

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D

FCR BIT-0=0

PINS

FCR BIT-0=1 (FIFO ENABLED)

(FIFO DISABLED)

FCR BIT-3 = 0

FCR BIT-3 = 1

(DMA MODE DISABLED)

(DMA MODE ENABLED)

RXRDY#

LOW = 1 byte

LOW = at least 1 byte in FIFO

HIGH = FIFO empty

HIGH to LOW transition when FIFO reaches the

trigger level, or timeout occurs

HIGH = no data

LOW to HIGH transition when FIFO empties

TXRDY#

LOW = THR empty

LOW = FIFO empty

LOW = FIFO has at least 1 empty location

HIGH = FIFO is full

HIGH = byte in THR HIGH = at least 1 byte in FIFO

2.7

Crystal Oscillator or External Clock Input

The V554 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the

device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a

system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the

oscillator or external clock buffer input with XTAL2 pin being the output. Caution: the XTAL1 input is not 5V

tolerant. For programming details, see “Section 2.8, Programmable Baud Rate Generator” on page 13.

FIGURE 5. TYPICAL CRYSTAL CONNECTIONS

R=300K to 400K

14.7456

MHz

XTAL2

XTAL1

C1

C2

22-47pF

The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,

fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency

tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown

in Figure 5. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate

generator for standard or custom rates. For further reading on oscillator circuit please see application note

DAN108 on EXAR’s web site.

2.8

Programmable Baud Rate Generator

Each UART has its own Baud Rate Generator (BRG) for the transmitter and receiver. The BRG further divides

this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to obtain a

16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter for data bit

shifting and receiver for data sampling. The BRG divisor defaults to the maximum baud rate (DLL = 0x01 and

DLM = 0x00) upon power up and reset. Programming the Baud Rate Generator Registers DLL and DLM

provides the capability for selecting the operating data rate. Table 6 shows the standard data rates available

with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used (MCR bit-7 = 1), the output

data rate will be 4 times less than that shown in Table 6.

13

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

REV. 1.0.1

FIGURE 6. BAUD RATE GENERATOR

To Other

Channels

DLL and DLM

Registers

Crystal

Osc/

Buffer

XTAL1

XTAL2

16 X Sampling

Rate Clock

to Transmitter

and Receiver

Programmable Baud

Rate Generator Logic

TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK

OUTPUT Data Rate

MCR Bit-7=0

DATA RATE

ERROR (%)

DIVISOR FOR 16x

Clock (Decimal)

DIVISOR FOR 16x

Clock (HEX)

DLM PROGRAM

VALUE (HEX)

DLL PROGRAM

VALUE (HEX)

(DEFAULT)

400

2304

384

192

96

48

24

12

6

900

180

C0

60

09

01

00

80

C0

60

30

18

0C

06

04

02

01

0

2400

4800

9600

19.2k

38.4k

76.8k

153.6k

230.4k

460.8k

921.6k

30

18

0C

06

4

04

2

02

1

01

2.9

Transmitter

The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which

includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal

sampling clock. A bit time is 16X clock periods. The transmitter sends the start-bit followed by the number of

data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are

reported in the Line Status Register (LSR bit-5 and bit-6).

14

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

2.9.1

Transmit Holding Register (THR) - Write Only

The transmit holding register is an 8-bit register providing a data interface to the host processor. The host

writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,

parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input

register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write

operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data

location.

2.9.2

Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the

data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled

by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.

FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE

Data

Byte

Transmit

Holding

Register

(THR)

THR Interrupt (ISR bit-1)

Enabled by IER bit-1

16X Clock

M

S

B

L

S

B

Transmit Shift Register (TSR)

TXNOFIFO1

2.9.3

Transmitter Operation in FIFO Mode

The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set

whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the

FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set

when TSR/FIFO becomes empty.

FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE

Transmit

FIFO

Transmit

Data Byte

THR Interrupt (ISR bit-1)

When it becomes empty.

FIFO is Enabled by FCR

Bit-0=1

16X Clock

Transmit Data Shift Register

(

)

TSR

TXFIFO1

15

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

2.10 Receiver

REV. 1.0.1

The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a

byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates

every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,

an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at

the center of the start bit. At this time the start bit is sampled and if it is still LOW it is validated. Evaluating the

start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and

stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s),

they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive

FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in

RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it

reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready

time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is

equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0. See Figure 9 and Figure 10

below.

2.10.1 Receive Holding Register (RHR) - Read-Only

The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift

Register. It provides the receive data interface to the host processor. The RHR register is part of the receive

FIFO of 16 bytes by 11-bit wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When

the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the

RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data

byte are immediately updated in the LSR bits 2-4.

FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE

16X Clock

Receive Data Shift

Register (RSR)

Data Bit

Validation

Receive Data Characters

Error

Receive

Data Byte

and Errors

Receive Data

Holding Register

(RHR)

Tags in

LSR bits

4:2

RHR Interrupt (ISR bit-2)

RXFIFO1

16

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

FIGURE 10. RECEIVER OPERATION IN FIFO

16X Clock

Receive Data Shift

Register (RSR)

Data Bit

Validation

Receive Data Characters

Example

- RX FIFO trigger level selected at 8 bytes

:

(See Note Below)

16 bytes by 11-bit wide

FIFO

Data falls to

4

Asking for sending data when data falls below the flow

control trigger level to restart remote transmitter.

Receive

Data FIFO

FIFO

Trigger=8

RHR Interrupt (ISR bit-2) programmed for

desired FIFO trigger level.

FIFO is Enabled by FCR bit-0=1

Data fills to

14

Asking for stopping data when data fills above the flow

control trigger level to suspend remote transmitter.

Receive

Data

Receive Data

Byte and Errors

RXFIFO1

17

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

REV. 1.0.1

2.11

Internal Loopback

The V554 UART provides an internal loopback capability for system diagnostic purposes. The internal

loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.

Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register

output is internally routed to the receive shift register input allowing the system to receive the same data that it

was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#,

DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else

upon exiting the loopback test the UART may detect and report a false “break” signal.

FIGURE 11. INTERNAL LOOP BACK IN CHANNEL A AND B

VCC

TX A-D

Transmit Shift Register

(THR/FIFO)

MCR bit-4=1

Receive Shift Register

(RHR/FIFO)

RX A-D

VCC

RTS# A-D

RTS#

CTS#

CTS# A-D

VCC

DTR# A-D

DTR#

DSR#

DSR# A-D

OP1#

RI#

RI# A-D

OP2#

CD#

CD# A-D

18

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

3.0 UART INTERNAL REGISTERS

Each UART channel in the V554 has its own set of configuration registers selected by address lines A0, A1

and A2 with a specific channel selected (See Table 1 and Table 2). The complete register set is shown on

Table 7 and Table 8.

TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS

A2,A1,A0 ADDRESSES

REGISTER

READ/WRITE

COMMENTS

16C550 COMPATIBLE REGISTERS

0 0 0

RHR - Receive Holding Register

Read-only

Write-only

LCR[7] = 0

THR - Transmit Holding Register

0 0 0

0 0 1

0 1 0

DLL - Divisor LSB

Read/Write

LCR[7] = 1, LCR ≠ 0xBF

DLM - Divisor MSB

IER - Interrupt Enable Register

LCR[7] = 0

ISR - Interrupt Status Register

FCR - FIFO Control Register

Read-only

Write-only

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

LCR - Line Control Register

MCR - Modem Control Register

LSR - Line Status Register

MSR - Modem Status Register

SPR - Scratch Pad Register

Read/Write

Read-only

Read/Write

LCR[7] = 0

19

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

REV. 1.0.1

TABLE 8: INTERNAL REGISTERS DESCRIPTION.

ADDRESS

REG

READ/

WRITE

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

COMMENT

A2-A0

NAME

16C550 Compatible Registers

0 0 0

0 0 1

RHR

THR

RD

Bit-7

0

Bit-6

0

Bit-5

0

Bit-4

0

Bit-3

Bit-2

Bit-1

Bit-0

WR

IER RD/WR

Modem RXLine

Stat. Int. Stat.

Enable

TX

Empty

Int

RX

Data

Int.

Enable Enable Enable

LCR[7] = 0

0 1 0

0 1 1

ISR

RD

FIFOs

Enabled Enabled

FIFOs

0

INT

Source Source Source Source

Bit-3

Bit-2

Bit-1

Bit-0

FCR

WR RXFIFO RXFIFO

Trigger Trigger

DMA

Mode

Enable

TX

FIFO

Reset Reset

RX

FIFOs

FIFO Enable

LCR RD/WR Divisor Set TX

Set

Even

Parity

Enable

Stop

Bits

Word

Length Length

Bit-1 Bit-0

Word

Enable

Break

Parity

1 0 0

1 0 1

MCR RD/WR

LSR RD/WR

0

Internal

Lopback

Enable

INT

Rsvd

RTS# DTR#

Output Output

Control Control

Output (OP1#)

Enable

(OP2#)

RX

THR &

TSR

Empty

THR

Empty

RX Break

RX

Parity Over-

Error

Data

FIFO

Global

Error

Framing

Error

LCR[7] = 0

run

Ready

Error

1 1 0

1 1 1

MSR RD/WR

SPR RD/WR

CD# RI# Input DSR#

CTS#

Input

Delta

CD#

Delta

RI#

Delta

DSR# CTS#

Delta

Input

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

Baud Rate Generator Divisor

0 0 0

0 0 1

DLL RD/WR

DLM RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

LCR[7]=1

LCR≠0xBF

4.0 INTERNAL REGISTER DESCRIPTIONS

4.1 Receive Holding Register (RHR) - Read- Only

SEE”RECEIVER” ON PAGE 16.

4.2 Transmit Holding Register (THR) - Write-Only

SEE”TRANSMITTER” ON PAGE 14.

4.3 Interrupt Enable Register (IER) - Read/Write

The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status

and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).

20

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

4.3.1

IER versus Receive FIFO Interrupt Mode Operation

When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts

(see ISR bits 2 and 3) status will reflect the following:

A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed

trigger level. It will be cleared when the FIFO drops below the programmed trigger level.

B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register

status bit and the interrupt will be cleared when the FIFO drops below the trigger level.

C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to

the receive FIFO. It is reset when the FIFO is empty.

4.3.2

IER versus Receive/Transmit FIFO Polled Mode Operation

When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16V554 in the FIFO

polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can

be used in the polled mode by selecting respective transmit or receive control bit(s).

A. LSR BIT-0 indicates there is data in RHR or RX FIFO.

B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.

C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.

D. LSR BIT-5 indicates THR is empty.

E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.

F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.

IER[0]: RHR Interrupt Enable

The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when

the receive FIFO has reached the programmed trigger level in the FIFO mode.

• Logic 0 = Disable the receive data ready interrupt (default).

• Logic 1 = Enable the receiver data ready interrupt.

IER[1]: THR Interrupt Enable

This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty. If the THR is

empty when this bit is enabled, an interrupt will be generated.

• Logic 0 = Disable Transmit Ready interrupt (default).

• Logic 1 = Enable Transmit Ready interrupt.

IER[2]: Receive Line Status Interrupt Enable

If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller

about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when an

overrun occurs. LSR bits 2-4 generate an interrupt when the character in the RHR has an error.

• Logic 0 = Disable the receiver line status interrupt (default).

• Logic 1 = Enable the receiver line status interrupt.

IER[3]: Modem Status Interrupt Enable

• Logic 0 = Disable the modem status register interrupt (default).

• Logic 1 = Enable the modem status register interrupt.

IER[7:4]: Reserved (Default 0)

21

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

REV. 1.0.1

4.4

Interrupt Status Register (ISR)

The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The

Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the

ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be

serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt

Source Table, Table 9, shows the data values (bit 0-3) for the interrupt priority levels and the interrupt sources

associated with each of these interrupt levels.

4.4.1

Interrupt Generation:

• LSR is by any of the LSR bits 1, 2, 3 and 4.

• RXRDY Data Ready is by RX trigger level.

• RXRDY Data Time-out is by a 4-char plus 12 bits delay timer.

• TXRDY is by TX FIFO empty.

• MSR is by any of the MSR bits 0, 1, 2 and 3.

4.4.2

Interrupt Clearing:

• LSR interrupt is cleared by a read to the LSR register.

• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.

• RXRDY Time-out interrupt is cleared by reading RHR.

• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.

• MSR interrupt is cleared by a read to the MSR register.

]

TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL

PRIORITY

ISR REGISTER STATUS BITS

SOURCE OF INTERRUPT

LEVEL

BIT-3

BIT-2

BIT-1

BIT-0

1

2

3

4

5

-

0

1

0

1

0

1

0

1

0

1

LSR (Receiver Line Status Register)

RXRDY (Receive Data Time-out)

RXRDY (Received Data Ready)

TXRDY (Transmit Ready)

MSR (Modem Status Register)

None (default)

ISR[0]: Interrupt Status

• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt

service routine.

• Logic 1 = No interrupt pending (default condition).

ISR[3:1]: Interrupt Status

These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9).

ISR[4]: Reserved (Default 0)

ISR[5]: Reserved (Default 0)

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XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

ISR[7:6]: FIFO Enable Status

These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are

enabled.

4.5

FIFO Control Register (FCR) - Write-Only

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the

DMA mode. The DMA, and FIFO modes are defined as follows:

FCR[0]: TX and RX FIFO Enable

• Logic 0 = Disable the transmit and receive FIFO (default).

• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are

written or they will not be programmed.

FCR[1]: RX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

• Logic 0 = No receive FIFO reset (default).

• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[2]: TX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

• Logic 0 = No transmit FIFO reset (default).

• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[3]: DMA Mode Select

Controls the behavior of the TXRDY and RXRDY pins. See DMA operation section for details.

• Logic 0 = Normal Operation (default).

• Logic 1 = DMA Mode.

FCR[5:4]: Reserved (Default 0)

FCR[7:6]: Receive FIFO Trigger Select

(logic 0 = default, RX trigger level =1)

These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when

the number of the characters in the FIFO crosses the trigger level. Table 10 shows the complete selections.

TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION

FCR BIT-7

FCR BIT-6

RECEIVE TRIGGER LEVEL

0

1

0

1

0

1

4

8

14

23

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

REV. 1.0.1

4.6

Line Control Register (LCR) - Read/Write

The Line Control Register is used to specify the asynchronous data communication format. The word or

character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this

register.

LCR[1:0]: TX and RX Word Length Select

These two bits specify the word length to be transmitted or received.

BIT-1

BIT-0

WORD LENGTH

0

1

0

1

0

1

5 (default)

6

7

8

LCR[2]: TX and RX Stop-bit Length Select

The length of stop bit is specified by this bit in conjunction with the programmed word length.

STOP BIT LENGTH

(BIT TIME(S))

WORD

LENGTH

BIT-2

0

1

5,6,7,8

5

1 (default)

1-1/2

2

6,7,8

LCR[3]: TX and RX Parity Select

Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data

integrity check. See Table 11 for parity selection summary below.

• Logic 0 = No parity.

• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the

data character received.

LCR[4]: TX and RX Parity Select

If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.

• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format (default).

• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format.

24

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

LCR[5]: TX and RX Parity Select

If the parity bit is enabled, LCR BIT-5 selects the forced parity format.

• LCR BIT-5 = logic 0, parity is not forced (default).

• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to HIGH for the transmit and receive data.

• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to LOW for the transmit and receive data.

TABLE 11: PARITY SELECTION

LCR BIT-5 LCR BIT-4 LCR BIT-3

PARITY SELECTION

No parity

X

0

1

X

0

1

0

1

0

1

Odd parity

Even parity

Force parity to mark, HIGH

Forced parity to space, LOW

LCR[6]: Transmit Break Enable

When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a

“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.

• Logic 0 = No TX break condition. (default)

• Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line

break condition.

LCR[7]: Baud Rate Divisors Enable

Baud rate generator divisor (DLL/DLM) enable.

• Logic 0 = Data registers are selected (default).

• Logic 1 = Divisor latch registers are selected.

4.7

Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write

The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.

MCR[0]: DTR# Output

The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a

general purpose output.

• Logic 0 = Force DTR# output HIGH (default).

• Logic 1 = Force DTR# output LOW.

MCR[1]: RTS# Output

The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a

general purpose output.

• Logic 0 = Force RTS# output HIGH (default).

• Logic 1 = Force RTS# output LOW.

MCR[2]: Reserved

OP1# is not available as an output pin on the V554. But it is available for use during Internal Loopback Mode.

In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.

25

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

MCR[3]: INT Output Enable

REV. 1.0.1

Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL

input, see below table for details. This bit is also used to control the OP2# signal during internal loopback

mode. INTSEL pin must be LOW during 68 mode.

• Logic 0 = INT (A-D) outputs disabled (three state) in the 16 mode (default). During internal loopback mode,

OP2# is HIGH.

• Logic 1 = INT (A-D) outputs enabled (active) in the 16 mode. During internal loopback mode, OP2# is LOW.

TABLE 12: INT OUTPUT MODES

INTSEL MCR

INT A-D OUTPUTS IN 16 MODE

BIT-3

0

1

X

Three-State

Active

0

1

Active

MCR[4]: Internal Loopback Enable

• Logic 0 = Disable loopback mode (default).

• Logic 1 = Enable local loopback mode, see loopback section and Figure 11.

MCR[7:5]: Reserved (Default 0)

4.8

Line Status Register (LSR) - Read/Write

This register is writeable but it is not recommended. The LSR provides the status of data transfers between the

UART and the host. If IER bit-2 is enabled, LSR bit-1 will generate an interrupt immediately and LSR bits 2-4

will generate an interrupt when a character with an error is in the RHR.

LSR[0]: Receive Data Ready Indicator

• Logic 0 = No data in receive holding register or FIFO (default).

• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.

LSR[1]: Receiver Overrun Flag

• Logic 0 = No overrun error (default).

• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens

when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register

is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

LSR[2]: Receive Data Parity Error Tag

• Logic 0 = No parity error (default).

• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.

This error is associated with the character available for reading in RHR.

LSR[3]: Receive Data Framing Error Tag

• Logic 0 = No framing error (default).

• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with

the character available for reading in RHR.

26

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

LSR[4]: Receive Break Tag

• Logic 0 = No break condition (default).

• Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the

FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX

input returns to the idle condition, “mark” or HIGH.

LSR[5]: Transmit Holding Register Empty Flag

This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte

is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0

concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set

when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.

LSR[6]: THR and TSR Empty Flag

This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or

TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and

transmit shift register are both empty.

LSR[7]: Receive FIFO Data Error Flag

• Logic 0 = No FIFO error (default).

• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error

or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the

RX FIFO.

4.9

Modem Status Register (MSR) - Read/Write

This register is writeable but it is not recommended. The MSR provides the current state of the modem

interface input signals. Lower four bits of this register are used to indicate the changed information. These bits

are set to a logic 1 whenever a signal from the modem changes state. These bits may be used for general

purpose inputs when they are not used with modem signals.

MSR[0]: Delta CTS# Input Flag

• Logic 0 = No change on CTS# input (default).

• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[1]: Delta DSR# Input Flag

• Logic 0 = No change on DSR# input (default).

• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[2]: Delta RI# Input Flag

• Logic 0 = No change on RI# input (default).

• Logic 1 = The RI# input has changed from LOW to HIGH, ending of the ringing signal. A modem status

interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[3]: Delta CD# Input Flag

• Logic 0 = No change on CD# input (default).

• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem

status interrupt will be generated if MSR interrupt is enabled (IER bit-3).

27

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

MSR[4]: CTS Input Status

REV. 1.0.1

A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has finished

transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the compliment of the CTS#

input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input

may be used as a general purpose input when the modem interface is not used.

MSR[5]: DSR Input Status

Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#

bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is

not used.

MSR[6]: RI Input Status

Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the

MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.

MSR[7]: CD Input Status

Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the

MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.

4.10 Scratch Pad Register (SPR) - Read/Write

This is a 8-bit general purpose register for the user to store temporary data.

4.11 Baud Rate Generator Registers (DLL and DLM) - Read/Write

These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL

gives the 16-bit divisor value. See ”Section 2.8, Programmable Baud Rate Generator” on page 13.

28

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

TABLE 13: UART RESET CONDITIONS FOR CHANNELS A-D

REGISTERS

RESET STATE

DLM, DLL

DLM = 0x00 and DLL = 0x01. Only resets to these val-

ues during a power up. They do not reset when the

Reset Pin is asserted.

RHR

THR

IER

Bits 7-0 = 0xXX

Bits 7-0 = 0x00

Bits 7-0 = 0x01

Bits 7-0 = 0x00

Bits 7-0 = 0x60

FCR

ISR

LCR

MCR

LSR

MSR

Bits 3-0 = Logic 0

Bits 7-4 = Logic levels of the inputs inverted

SPR

I/O SIGNALS

TX

Bits 7-0 = 0xFF

RESET STATE

HIGH

RTS#

HIGH

DTR#

HIGH

RXRDY#

TXRDY#

HIGH

LOW

INT

XR16V554 = Three-State Condition (INTSEL = LOW)

XR16V554 = LOW (INTSEL = HIGH)

XR16V554D = LOW

(16 Mode)

IRQ#

HIGH (INTSEL = LOW)

(68 Mode)

29

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

REV. 1.0.1

ABSOLUTE MAXIMUM RATINGS

Power Supply Range

Voltage at Any Pin

4 Volts

GND-0.3 V to 5.5 V

-40^oto +85^oC

Operating Temperature

-65^oto +150^oC

500 mW

Storage Temperature

Package Dissipation

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)

theta-ja = 28^oC/W, theta-jc = 10.5^oC/W

Thermal Resistance (48-QFN)

theta-ja = 50^oC/W, theta-jc = 11^oC/W

Thermal Resistance (64-LQFP)

theta-ja = 46^oC/W, theta-jc = 17^oC/W

Thermal Resistance (68-PLCC)

theta-ja = 37^oC/W, theta-jc = 7^oC/W

Thermal Resistance (80-LQFP)

ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS

UNLESS OTHERWISE NOTED: TA = -40^OTO +85^OC, VCC IS 2.25 TO 3.6V

LIMITS

2.5V

LIMITS

3.3V

SYMBOL

PARAMETER

UNITS

CONDITIONS

MIN

MAX

MIN

MAX

V_ILCK

V_IHCK

V_IL

Clock Input Low Level

Clock Input High Level

Input Low Voltage

-0.3

0.4

VCC

0.5

-0.3

0.6

VCC

0.7

V

2.0

-0.3

1.8

2.4

-0.3

2.0

V_IH

Input High Voltage

Output Low Voltage

5.5

V_OL

0.4

V

I_OL= 6 mA

I_OL= 4 mA

0.4

V_OH

Output High Voltage

2.0

V

I_OH= -4 mA

I_OH= -2 mA

1.8

I_IL

I_IH

Input Low Leakage Current

Input High Leakage Current

Input Pin Capacitance

±15

5

±15

5

uA

pF

C_IN

I_CC

Power Supply Current

1.7

3

mA

Ext Clk = 2MHz

30

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

AC ELECTRICAL CHARACTERISTICS

TA = -40^OTO +85^OC, VCC IS 2.25 TO 3.6V, 70 PF LOAD WHERE APPLICABLE

LIMITS

SYMBOL

PARAMETER

2.5V ± 10%

3.3V ± 10%

UNIT

MIN

MAX

MIN

MAX

XTAL1

ECLK

T_ECLK

UART Crystal Frequency

24

MHz

ns

External Clock Frequency

External Clock Time Period

50

64

10

0

7

0

T_AS

T_AH

Address Setup Time (16 Mode)

Address Hold Time (16 Mode)

Chip Select Width (16 Mode)

IOR# Strobe Width (16 Mode)

Read Cycle Delay (16 Mode)

Data Access Time (16 Mode)

Data Disable Time (16 Mode)

IOW# Strobe Width (16 Mode)

Write Cycle Delay (16 Mode)

Data Setup Time (16 Mode)

Data Hold Time (16 Mode)

ns

0

T_CS

50

40

T_RD

T_DY

T_RDV

T_DD

45

10

35

10

T_WR

T_DY

50

10

5

40

10

5

T_DS

T_DH

T_ADS

T_ADH

T_RWS

T_RDA

T_RDH

T_WDS

T_WDH

T_RWH

T_CSL

T_CSD

T_WDO

T_MOD

T_RSI

Address Setup (68 Mode)

0

Address Hold (68 Mode)

0

R/W# Setup to CS# (68 Mode)

Data Access Time (68 mode)

Data Disable Time (68 mode)

Write Data Setup (68 mode)

Write Data Hold (68 Mode)

0

45

10

35

10

5

10

5

CS# De-asserted to R/W# De-asserted (68 Mode)

CS# Strobe Width (68 Mode)

CS# Cycle Delay (68 Mode)

Delay From IOW# To Output

Delay To Set Interrupt From MODEM Input

Delay To Reset Interrupt From IOR#

10

50

5

40

50

31

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

AC ELECTRICAL CHARACTERISTICS

REV. 1.0.1

TA = -40^OTO +85^OC, VCC IS 2.25 TO 3.6V, 70 PF LOAD WHERE APPLICABLE

LIMITS

SYMBOL

PARAMETER

2.5V ± 10%

3.3V ± 10%

UNIT

MIN

MAX

MIN

MAX

T_SSI

T_RRI

T_SI

Delay From Stop To Set Interrupt

Delay From IOR# To Reset Interrupt

Delay From Start To Interrupt

1

Bclk

ns

45

24

45

1

45

24

45

1

ns

T_INT

T_WRI

T_SSR

T_RR

Delay From Initial INT Reset To Transmit Start

Delay From IOW# To Reset Interrupt

Delay From Stop To Set RXRDY#

Delay From IOR# To Reset RXRDY#

Delay From IOW# To Set TXRDY#

Delay From Center of Start To Reset TXRDY#

Reset Pulse Width

8

Bclk

ns

Bclk

ns

45

8

45

8

T_WT

T_SRT

T_RST

Bclk

ns

Bclk

ns

40

Baud Clock

16X data rate

Hz

FIGURE 12. CLOCK TIMING

CLK

EXTERNAL

CLOCK

OSC

32

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

FIGURE 13. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D

IO W #

IO W

A c tiv e

T _W

D O

R T S #

D T R #

C h a n g e o f s ta te

C D #

C T S #

D S R #

C h a n g e o f s ta te

T _{M O D}

IN T

A c tiv e

T _{R S I}

IO R #

A c tiv e

T _{M O D}

C h a n g e o f s ta te

R I#

FIGURE 14. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D

A0-A7

CS#

Valid Address

T_CS

Valid Address

T_CS

T_AS

T_AH

T_DY

T_RD

IOR#

D0-D7

T_DD

T_RDV

Valid Data

RDTm

33

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

REV. 1.0.1

FIGURE 15. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D

A0-A7

CS#

Valid Address

T_CS

Valid Address

T_CS

T_AS

T_AH

T_DY

T_WR

IOW#

D0-D7

T_DH

T_DS

Valid Data

T_DS

Valid Data

16Write

FIGURE 16. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D

A0-A7

CS#

Valid Address

TCSL

Valid Address

TADS

TADH

TCSD

TRWS

TRWH

R/W#

D0-D7

TRDH

TRDA

Valid Data

68Read

34

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

FIGURE 17. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D

A0-A7

CS#

Valid Address

TCSL

Valid Address

TADS

TADH

TCSD

TRWS

TRWH

R/W#

D0-D7

T

WDH

TWDS

Valid Data

68Write

FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D

RX

Stop

Bit

Start

Bit

D0:D7

T_SSR

1 Byte

in RHR

INT

T_SSR

Active

Data

Active

Data

Active

Data

RXRDY#

Ready

T_RR

IOR#

(Reading data

out of RHR)

RXNFM

35

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

REV. 1.0.1

FIGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D

TX

(Unloading)

Stop

Bit

Start

Bit

D0:D7

IER[1]

enabled

ISR is read

INT*

T_WRI

T_SRT

TXRDY#

T_WT

IOW#

(Loading data

into THR)

*INT is cleared when the ISR is read or when data is loaded into the THR.

TXNonFIFO

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D

Start

Bit

RX

S

T

D0:D7

T

D0:D7

T_SSI

D0:D7

S

T

S

D0:D7

T

D0:D7

T

Stop

Bit

RX FIFO drops

below RX

Trigger Level

INT

T_SSR

FIFO

Empties

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

RXRDY#

First Byte is

Received in

RX FIFO

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXINTDMA#

36

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D

Start

Bit

Stop

Bit

RX

S

T

D0:D7

T

D0:D7

T_SSI

D0:D7

S

T

S

D0:D7

T

D0:D7

T

RX FIFO drops

below RX

Trigger Level

INT

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

T_SSR

FIFO

Empties

RXRDY#

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXFIFODMA

FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX FIFO

Empty

TX

(Unloading)

T

S

T

S

T

S

D0:D7

T

S D0:D7

T

D0:D7

T

D0:D7

T

ISR is read

T_SI

IER[1]

enabled

ISR is read

T_SRT

INT*

TX FIFO

Empty

TX FIFO fills up

to trigger level

TX FIFO drops

below trigger level

T_WRI

Data in

TX FIFO

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.

TXDMA#

37

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

REV. 1.0.1

FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX

(Unloading)

S

D0:D7

S

D0:D7

S

D0:D7

T

D0:D7

S

D0:D7

T

S D0:D7

T

IER[1]

enabled

ISR Read

T_SI

T_SRT

INT*

TX FIFO fills up

to trigger level

TX FIFO drops

below trigger level

T_WRI

At least 1

empty location

in FIFO

TX FIFO

Full

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.

TXDMA

38

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

PACKAGE DIMENSIONS

48 LEAD QUAD FLAT NO LEAD (7 x 7 x 0.9 mm, 0.50 mm pitch QFN)

Note: The actual center pad is

metallic and the size (D2) is

device-dependent with a typical

tolerance of 0.3mm. The lead

may be half-etched terminal.

Note: The control dimension is the millimeter column

INCHES

MAX

MILLIMETERS

SYMBOL

MIN

0.80

0.00

0.15

6.85

5.10

0.18

MAX

1.00

0.05

0.25

7.15

5.30

0.30

A

A1

A3

D

0.031

0.000

0.006

0.270

0.201

0.007

0.039

0.002

0.010

0.281

0.209

0.012

D2

b

e

0.0197 BSC

0.50 BSC

L

0.012

0.008

0.020

-

0.30

0.20

0.50

-

k

39

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

64 LEAD LOW-PROFILE QUAD FLAT PACK (10 x 10 x 1.4 mm LQFP)

REV. 1.0.1

D

D₁

48

33

49

32

D₁

D

64

17

1

16

B

A₂

e

C

A

α

Seating Plane

A₁

L

Note: The control dimension is the millimeter column

INCHES

MAX

MILLIMETERS

SYMBOL

MIN

MAX

1.60

0.15

1.45

0.27

0.20

12.20

10.10

A

A1

A2

B

0.055

0.002

0.053

0.007

0.004

0.465

0.390

0.063

0.006

0.057

0.011

0.008

0.480

0.398

1.40

0.05

1.35

0.17

0.09

11.80

9.90

C

D

D1

e

0.020 BSC

0.50 BSC

L

0.018

0.030

0.45

0.75

α

0°

7°

0°

7°

40

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)

D

C

Seating Plane

D₁

45° x H

1

A₂

45° x H

2

2 1 68

B₁

B

D

3

D

2

D

1

e

R

D

3

A₁

A

Note: The control dimension is the inch column

INCHES MILLIMETERS

SYMBOL

MIN

0.165

0.090

MAX

0.200

0.130

MIN

MAX

5.08

3.30

A

4.19

2.29

A₁

A₂

0.020

---.

0.51

---

B

0.013

0.026

0.021

0.032

0.33

0.66

0.53

0.81

B₁

C

D

0.008

0.985

0.950

0.013

0.995

0.958

0.19

25.02

24.13

0.32

25.27

24.33

D₁

D₂

D₃

0.890

0.930

22.61

23.62

0.800 typ.

0.050 BSC

0.042

20.32 typ.

1.27 BSC

e

H₁

0.056

0.048

0.045

1.07

0.64

1.42

1.22

1.14

H₂

R

0.042

0.025

41

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

80 LEAD PLASTIC QUAD FLAT PACK (12 mm x 12 mm LQFP, 1.4 mm Form)

REV. 1.0.1

Note: The control dimension is the millimeter column

INCHES

MAX

MILLIMETERS

SYMBOL

MIN

MAX

1.60

0.15

1.45

0.27

0.20

14.20

12.20

A

A1

A2

B

0.055

0.002

0.053

0.007

0.004

0.543

0.465

0.063

0.006

0.057

0.011

0.008

0.559

0.480

1.40

0.05

1.35

0.17

0.09

13.80

11.80

C

D

D1

e

0.0197 BSC

0.50 BSC

L

0.018

0.030

0.45

0.75

α

0°

7°

0°

7°

42

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

REVISION HISTORY

DATE

REVISION

DESCRIPTION

April 2006

July 2006

Rev P1.0.0 Preliminary Data Sheet.

Rev P1.0.1 Updated AC Electrical Characterstics.

Rev P1.0.2 Updated DC Electrical Characteristics.

October 2006

January 2007

May 2007

Rev 1.0.0

Rev 1.0.1

Final Datasheet.

Updated QFN package dimensions drawing to show minimum "k" parameter.

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to

improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any

circuits described herein, conveys no license under any patent or other right, and makes no representation that

the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration

purposes and may vary depending upon a user’s specific application. While the information in this publication

has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the

failure or malfunction of the product can reasonably be expected to cause failure of the life support system or

to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless

EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has

been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately

protected under the circumstances.

Datasheet May 2007.

Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

43

XR16V554/554D

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

REV. 1.0.1

TABLE OF CONTENTS

GENERAL DESCRIPTION ................................................................................................ 1

FEATURES .................................................................................................................................................... 1

APPLICATIONS............................................................................................................................................... 1

FIGURE 1. XR16V554 BLOCK DIAGRAM ........................................................................................................................................... 1

FIGURE 2. PIN OUT ASSIGNMENT FOR 68-PIN PLCC PACKAGES IN 16 AND 68 MODE AND 64-PIN LQFP PACKAGES.......................... 2

FIGURE 3. PIN OUT ASSIGNMENT FOR 48-PIN QFN PACKAGE AND 80-PIN LQFP PACKAGE............................................................... 3

PIN DESCRIPTIONS ......................................................................................................... 4

ORDERING INFORMATION................................................................................................................................ 4

1.0 PRODUCT DESCRIPTION....................................................................................................................... 9

2.0 FUNCTIONAL DESCRIPTIONS............................................................................................................. 10

2.1 CPU INTERFACE............................................................................................................................................... 10

FIGURE 4. XR16V554 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS........................................................................... 10

2.2 DEVICE RESET ................................................................................................................................................. 11

2.3 CHANNEL SELECTION..................................................................................................................................... 11

TABLE 1: CHANNEL A-D SELECT IN 16 MODE ................................................................................................................................. 11

TABLE 2: CHANNEL A-D SELECT IN 68 MODE ................................................................................................................................. 11

2.4 CHANNELS A-D INTERNAL REGISTERS ....................................................................................................... 12

2.5 INT OUPUTS FOR CHANNELS A-D................................................................................................................. 12

TABLE 3: INT PIN OPERATION FOR TRANSMITTER FOR CHANNELS A-D ........................................................................................... 12

TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D ................................................................................................. 12

2.6 DMA MODE........................................................................................................................................................ 12

TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D ........................................................... 13

2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 13

FIGURE 5. TYPICAL CRYSTAL CONNECTIONS................................................................................................................................... 13

2.8 PROGRAMMABLE BAUD RATE GENERATOR.............................................................................................. 13

FIGURE 6. BAUD RATE GENERATOR ............................................................................................................................................... 14

TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 14

2.9 TRANSMITTER.................................................................................................................................................. 14

2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 15

2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE.................................................................................................... 15

FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 15

2.9.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 15

FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 15

2.10 RECEIVER ....................................................................................................................................................... 16

2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 16

FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................... 16

FIGURE 10. RECEIVER OPERATION IN FIFO.................................................................................................................................... 17

2.11 INTERNAL LOOPBACK................................................................................................................................. 18

FIGURE 11. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 18

3.0 UART INTERNAL REGISTERS ............................................................................................................. 19

TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS ....................................................................................... 19

TABLE 8: INTERNAL REGISTERS DESCRIPTION. ................................................................................................................... 20

4.0 INTERNAL REGISTER DESCRIPTIONS............................................................................................... 20

4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 20

4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 20

4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE................................................................................. 20

4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 21

4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 21

4.4 INTERRUPT STATUS REGISTER (ISR)........................................................................................................... 22

4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 22

4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 22

TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 22

4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 23

TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION ................................................................................................................... 23

4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 24

TABLE 11: PARITY SELECTION ........................................................................................................................................................ 25

4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE.. 25

TABLE 12: INT OUTPUT MODES ..................................................................................................................................................... 26

4.8 LINE STATUS REGISTER (LSR) - READ/WRITE ............................................................................................ 26

4.9 MODEM STATUS REGISTER (MSR) - READ/WRITE...................................................................................... 27

I

XR16V554/554D

REV. 1.0.1

2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 28

4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE................................................. 28

TABLE 13: UART RESET CONDITIONS FOR CHANNELS A-D ................................................................................................. 29

ABSOLUTE MAXIMUM RATINGS ................................................................................. 30

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 30

ELECTRICAL CHARACTERISTICS............................................................................... 30

DC ELECTRICAL CHARACTERISTICS............................................................................................................. 30

AC ELECTRICAL CHARACTERISTICS............................................................................................................. 31

TA = -40O TO +85OC, VCC IS 2.25 TO 3.6V, 70 PF LOAD WHERE APPLICABLE............................................. 31

FIGURE 12. CLOCK TIMING............................................................................................................................................................. 32

FIGURE 13. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D .................................................................................................... 33

FIGURE 14. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D ................................................................................... 33

FIGURE 15. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D.................................................................................. 34

FIGURE 16. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D........................................................................... 34

FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D ............................................................ 35

FIGURE 17. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D ......................................................................... 35

FIGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D .......................................................... 36

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D........................................... 36

FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D............................................ 37

FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D .............................. 37

FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D ............................... 38

PACKAGE DIMENSIONS................................................................................................................................ 39

REVISION HISTORY ..................................................................................................................................... 43

TABLE OF CONTENTS ..................................................................................................... I

II


型号：	XR16V554
厂家：	EXAR CORPORATION
描述：	2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 具有16字节FIFO 2.25V至3.6V UART QUAD 先进先出芯片
文件：	总45页 (文件大小：911K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XR16V554 [EXAR]

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