XR16V2750_技术文档

PRELIMINARY

XR16V2750

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

JUNE 2006

REV. P1.0.0

FEATURES

GENERAL DESCRIPTION

• 2.25 to 3.6 Volt Operation

• 5 Volt Tolerant Inputs

1

The XR16V2750 (V2750) is a high performance dual

universal asynchronous receiver and transmitter

(UART) with 64 byte TX and RX FIFOs. The device

operates from 2.25 to 3.6 volts with 5 Volt tolerant

inputs and is pin-to-pin compatible to Exar’s

ST16C2550 and XR16L2750. The V2750 register set

is identical to the XR16L2750 and is compatible to the

ST16C2550 and the XR16C2850 enhanced features.

It supports the Exar’s enhanced features of

programmable FIFO trigger level and FIFO level

counters, automatic hardware (RTS/CTS) and

software flow control, automatic RS-485 half duplex

direction control output and a complete modem

interface. Onboard registers provide the user with

operational status and data error flags. An internal

loopback capability allows system diagnostics.

Independent programmable baud rate generators are

provided in each channel to select data rates up to 8

Mbps at 3.3 Volt and 8X sampling clock. The V2750

is available in 48-pin TQFP and 32-pin QFN

packages.

• Pin-to-pin compatible to Exar’s XR16L2750 and

TI’s TL16C752B in the 48-TQFP package

• Two independent UART channels

■ Register set compatible to XR16L2750

■ Data rate of up to 8 Mbps at at 3.3 V, and

6.25 Mbps at 2.5 V with 8X sampling rate

■ Fractional Baud Rate Generator

■ Transmit and Receive FIFOs of 64 bytes

■ Programmable TX and RX FIFO Trigger Levels

■ Transmit and Receive FIFO Level Counters

■ Automatic Hardware (RTS/CTS) Flow Control

■ Selectable Auto RTS Flow Control Hysteresis

■ Automatic Software (Xon/Xoff) Flow Control

■ Automatic RS-485 Half-duplex Direction

Control Output via RTS#

■ Wireless Infrared (IrDA 1.0) Encoder/Decoder

■ Automatic sleep mode

NOTE: 1 Covered by U.S. Patent #5,649,122

APPLICATIONS

■ Full modem interface

• Portable Appliances

• Telecommunication Network Routers

• Ethernet Network Routers

• Device Identification and Revision

• Crystal oscillator (up to 32MHz) or external clock

(upto 64MHz) input

• 48-TQFP and 32-QFN packages

• Cellular Data Devices

• Factory Automation and Process Controls

FIGURE 1. XR16V2750 BLOCK DIAGRAM

* 5 Volt Tolerant Inputs

2.25 to 3.6 Volt VCC

A2:A0

D7:D0

GND

IOR#

IOW#

UART Channel A

TXA, RXA, DTRA#,

64 Byte TX FIFO

CSA#

CSB#

UART

DSRA#, RTSA#,

DTSA#, CDA#, RIA#,

OP2A#

Regs

IR

ENDEC

TX & RX

8-bit Data

Bus

Interface

INTA

INTB

BRG

64 Byte RX FIFO

TXRDYA#

TXRDYB#

RXRDYA#

RXRDYB#

TXB, RXB, DTRB#,

DSRB#, RTSB#,

CTSB#, CDB#, RIB#,

OP2B#

UART Channel B

(same as Channel A)

Reset

XTAL1

XTAL2

Crystal Osc/Buffer

2750BLK

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

FIGURE 2. PIN OUT ASSIGNMENT

RESET

DTRB#

DTRA#

RTSA#

OP2A#

RXRDYA#

INTA

1

2

3

4

5

6

36

35

34

33

32

31

30

29

28

D5

D6

D7

RXB

RXA

XR16V2750

48-pin TQFP

TXRDYB#

TXA

7

INTB

TXB

8

9

A0

OP2B#

CSA#

CSB#

10

11

27 A1

A2

26

25

NC

NC 12

1

2

3

4

5

6

7

8

24 RESET

23 RTSA#

D6

D7

INTA

21 INTB

22

RXB

RXA

TXA

TXB

XR16V2750

32-pin QFN

A0

A1

A2

20

19

18

CSA#

CSB#

17 NC

ORDERING INFORMATION

PART NUMBER

PACKAGE

OPERATING TEMPERATURE RANGE

DEVICE STATUS

XR16V2750IL32

XR16V2750IM

32-pin QFN

-40°C to +85°C

Active

48-Lead TQFP

2

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

PIN DESCRIPTIONS

Pin Description

32-QFN

48-TQFP

PIN #

NAME

PIN #

TYPE

DESCRIPTION

DATA BUS INTERFACE

A2

A1

A0

18

19

20

26

27

28

I

Address data lines [2:0]. These 3 address lines select one of the inter-

nal registers in UART channel A/B during a data bus transaction.

D7

D6

D5

D4

D3

D2

D1

D0

2

3

I/O

Data bus lines [7:0] (bidirectional).

1

2

32

31

30

29

28

27

1

48

47

46

45

44

IOR#

14

19

I

Input/Output Read Strobe (active low). The falling edge instigates an

internal read cycle and retrieves the data byte from an internal register

pointed to by the address lines [A2:A0]. The data byte is placed on the

data bus to allow the host processor to read it on the rising edge.

IOW#

12

15

Input/Output Write Strobe (active low). The falling edge instigates an

internal write cycle and the rising edge transfers the data byte on the

data bus to an internal register pointed by the address lines.

CSA#

CSB#

INTA

7

8

10

11

30

I

UART channel A select (active low) to enable UART channel A in the

device for data bus operation.

UART channel B select (active low) to enable UART channel B in the

device for data bus operation.

22

O

UART channel A Interrupt output. The output state is defined by the

user through the software setting of MCR[3]. INTA is set to the active

mode and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is

set to the three state mode and OP2A# output HIGH when MCR[3] is

set to a logic 0 (default). See MCR[3].

INTB

21

29

O

UART channel B Interrupt output. The output state is defined by the

user through the software setting of MCR[3]. INTB is set to the active

mode and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is

set to the three state mode and OP2B# output HIGH when MCR[3] is

set to a logic 0 (default). See MCR[3].

TXRDYA#

RXRDYA#

TXRDYB#

-

43

31

6

O

UART channel A Transmitter Ready (active low). The output provides

the TX FIFO/THR status for transmit channel A. See Table 2. If it is not

used, leave it unconnected.

UART channel A Receiver Ready (active low). This output provides the

RX FIFO/RHR status for receive channel A. See Table 2. If it is not

used, leave it unconnected.

UART channel B Transmitter Ready (active low). The output provides

the TX FIFO/THR status for transmit channel B. See Table 3. If it is not

used, leave it unconnected.

3

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

Pin Description

32-QFN

PIN #

48-TQFP

PIN #

NAME

TYPE

DESCRIPTION

RXRDYB#

-

18

O

UART channel B Receiver Ready (active low). This output provides the

RX FIFO/RHR status for receive channel B. See Table 2. If it is not

used, leave it unconnected.

MODEM OR SERIAL I/O INTERFACE

TXA

5

7

O

UART channel A Transmit Data or infrared encoder data. Standard

transmit and receive interface is enabled when MCR[6] = 0. In this

mode, the TX signal will be HIGH during reset or idle (no data). Infrared

IrDA transmit and receive interface is enabled when MCR[6] = 1. In the

Infrared mode, the inactive state (no data) for the Infrared encoder/

decoder interface is LOW. If it is not used, leave it unconnected.

RXA

6

5

I

UART channel A Receive Data or infrared receive data. Normal receive

data input must idle HIGH. The infrared receiver pulses typically idles at

LOW but can be inverted by software control prior going in to the

decoder, see MCR[6] and FCTR[2]. If this pin is not used, tie it to VCC

or pull it high via a 100k ohm resistor.

RTSA#

CTSA#

23

25

33

38

O

I

UART channel A Request-to-Send (active low) or general purpose out-

put. This output must be asserted prior to using auto RTS flow control,

see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and IER[6]. For auto

RS485 half-duplex direction control, see FCTR[3] and EMSR[3].

UART channel A Clear-to-Send (active low) or general purpose input.

It can be used for auto CTS flow control, see EFR[7], and IER[7]. This

input should be connected to VCC when not used.

DTRA#

DSRA#

-

34

39

O

I

UART channel A Data-Terminal-Ready (active low) or general purpose

output. If it is not used, leave it unconnected.

UART channel A Data-Set-Ready (active low) or general purpose input.

This input should be connected to VCC when not used. This input has

no effect on the UART.

CDA#

RIA#

-

40

41

32

I

UART channel A Carrier-Detect (active low) or general purpose input.

This input should be connected to VCC when not used. This input has

no effect on the UART.

UART channel A Ring-Indicator (active low) or general purpose input.

This input should be connected to VCC when not used. This input has

no effect on the UART.

OP2A#

O

Output Port 2 Channel A - The output state is defined by the user and

through the software setting of MCR[3]. INTA is set to the active mode

and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is set to

the three state mode and OP2A# output HIGH when MCR[3] is set to a

logic 0. See MCR[3]. If INTA is used, this output should not be used as

a general output else it will disturb the INTA output functionality.

TXB

6

8

O

UART channel B Transmit Data or infrared encoder data. Standard

transmit and receive interface is enabled when MCR[6] = 0. In this

mode, the TX signal will be HIGH during reset or idle (no data). Infrared

IrDA transmit and receive interface is enabled when MCR[6] = 1. In the

Infrared mode, the inactive state (no data) for the Infrared encoder/

decoder interface is LOW. If it is not used, leave it unconnected.

4

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

Pin Description

32-QFN

48-TQFP

PIN #

NAME

TYPE

DESCRIPTION

PIN #

RXB

3

4

I

UART channel B Receive Data or infrared receive data. Normal receive

data input must idle HIGH. The infrared receiver pulses typically idles at

logic 0 but can be inverted by software control prior going in to the

decoder, see MCR[6] and FCTR[2]. If this pin is not used, tie it to VCC

or pull it high via a 100k ohm resistor.

RTSB#

CTSB#

15

16

22

23

O

I

UART channel B Request-to-Send (active low) or general purpose out-

put. This port must be asserted prior to using auto RTS flow control,

see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and IER[6]. For auto

RS485 half-duplex direction control, see FCTR[3] and EMSR[3].

UART channel B Clear-to-Send (active low) or general purpose input.

It can be used for auto CTS flow control, see EFR[7], and IER[7]. This

input should be connected to VCC when not used.

DTRB#

DSRB#

-

35

20

O

I

UART channel B Data-Terminal-Ready (active low) or general purpose

output. If it is not used, leave it unconnected.

UART channel B Data-Set-Ready (active low) or general purpose input.

This input should be connected to VCC when not used. This input has

no effect on the UART.

CDB#

RIB#

-

16

21

9

I

UART channel B Carrier-Detect (active low) or general purpose input.

This input should be connected to VCC when not used. This input has

no effect on the UART.

UART channel B Ring-Indicator (active low) or general purpose input.

This input should be connected to VCC when not used. This input has

no effect on the UART.

OP2B#

O

Output Port 2 Channel B - The output state is defined by the user and

through the software setting of MCR[3]. INTB is set to the active mode

and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is set to

the three state mode and OP2B# output HIGH when MCR[3] is set to a

logic 0. See MCR[3]. If INTB is used, this output should not be used as

a general output else it will disturb the INTB output functionality.

ANCILLARY SIGNALS

XTAL1

XTAL2

RESET

10

11

24

13

14

36

I

O

I

Crystal or external clock input. Caution: this input is not 5V tolerant.

Crystal or buffered clock output.

Reset (active high) - A longer than 40 ns HIGH pulse on this pin will

reset the internal registers and all outputs. The UART transmitter output

will be held HIGH, the receiver input will be ignored and outputs are

reset during reset period (see Table 16).

VCC

26

42

17

Pwr

2.25V to 3.6V power supply. All input pins, except XTAL1, are 5V toler-

ant.

GND

N.C.

13

Power supply common, ground.

No Connection.

9, 17

12, 24, 25,

37

Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.

5

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

1.0 PRODUCT DESCRIPTION

The XR16V2750 (V2750) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver

and Transmitter (UART). Each UART is independently controlled having its own set of device configuration

registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.

Additionally, each UART channel has 64-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware

flow control with hysteresis control, automatic Xon/Xoff and special character software flow control,

programmable transmit and receive FIFO trigger levels, FIFO level counters, infrared encoder and decoder

(IrDA ver 1.0), programmable fractional baud rate generator with a prescaler of divide by 1 or 4, and data rate

up to 8 Mbps with 8X sampling clock rate or 4 Mbps in the 16X rate. The XR16V2750 is a 2.25 to 3.6V device

with 5 volt tolerant inputs. The V2750 is fabricated with an advanced CMOS process.

Enhanced Features

The V2750 DUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of

16 bytes in the ST16C2550 or one byte in the ST16C2450. The V2750 is designed to work with low supply

voltage and high performance data communication systems, that require fast data processing time. Increased

performance is realized in the V2750 by the larger transmit and receive FIFOs, FIFO trigger level control, FIFO

level counters and automatic flow control mechanism. This allows the external processor to handle more

networking tasks within a given time. For example, the ST16C2550 with a 16 byte FIFO, unloads 16 bytes of

receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at 115.2

Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However with

the 64 byte FIFO in the V2750, the data buffer will not require unloading/loading for 6.1 ms. This increases the

service interval giving the external CPU additional time for other applications and reducing the overall UART

interrupt servicing time. In addition, the programmable FIFO level trigger interrupt and automatic hardware/

software flow control is uniquely provided for maximum data throughput performance especially when

operating in a multi-channel system. The combination of the above greatly reduces the CPU’s bandwidth

requirement, increases performance, and reduces power consumption.

The V2750 supports a half-duplex output direction control signaling pin, RTS# A/B, to enable and disable the

external RS-485 transceiver operation. It automatically switches the logic state of the output pin to the receive

state after the last stop-bit of the last character has been shifted out of the transmitter. After receiving, the logic

state of the output pin switches back to the transmit state when a data byte is loaded in the transmitter. The

auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has

to set FCTR Bit-3 to “1”. This pin is normally high for receive state, low for transmit state.

Data Rate

The V2750 is capable of operation up to 4 Mbps at 3.3V with 16X internal sampling clock rate and 8 Mbps at

3.3V with 8X sampling clock rate. The device can operate with an external 32 MHz crystal at 2.5V on pins

XTAL1 and XTAL2, or external clock source of up to 64 MHz on XTAL1 pin. With a typical crystal of 14.7456

MHz and through a software option, the user can set the prescaler bit for data rates of up to 1.84 Mbps.

The rich feature set of the V2750 is available through the internal registers. Automatic hardware/software flow

control, selectable transmit and receive FIFO trigger levels, selectable TX and RX baud rates, infrared

encoder/decoder interface, modem interface controls, and a sleep mode are all standard features.

Following a power on reset or an external reset, the V2750 is software compatible with previous generation of

UARTs, 16C450, 16C550 and 16C650A as well as the 16C850.

6

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

2.0 FUNCTIONAL DESCRIPTIONS

2.1

CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and

write transactions. The V2750 data interface supports the Intel compatible types of CPUs and it is compatible

to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data

bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels

share the same data bus for host operations. The data bus interconnections are shown in Figure 3.

FIGURE 3. XR16V2750 DATA BUS INTERCONNECTIONS

VCC

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

TXA

RXA

DTRA#

RTSA#

CTSA#

DSRA#

UART

Channel A

Serial Interface of

RS-232, RS-485

A0

A1

A2

A0

A1

A2

CDA#

RIA#

OP2A#

IOR#

IOW#

IOR#

IOW#

TXB

RXB

CSA#

CSB#

UART_CSA#

UART_CSB#

DTRB#

RTSB#

CTSB#

DSRB#

CDB#

UART_INTA

UART_INTB

INTA

INTB

UART

Channel B

Serial Interface of

RS-232, RS-485

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

RIB#

OP2B#

UART_RESET

RESET

GND

2750int

2.2

5-Volt Tolerant Inputs

The V2750 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the V2750 is

operating at 2.5V, its V may not be high enough to meet the requirements of the V of a CPU or a serial

OH

IH

transceiver that is operating at 5V. Caution: XTAL1 is not 5 volt tolerant.

2.3 Device Reset

The RESET input resets the internal registers and the serial interface outputs in both channels to their default

state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset

function in the device.

2.4

Device Identification and Revision

The XR16V2750 provides a Device Identification code and a Device Revision code to distinguish the part from

other devices and revisions. To read the identification code from the part, it is required to set the baud rate

generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DLM will provide

0x0A for the XR16V2750 and reading the content of DLL will provide the revision of the part; for example, a

reading of 0x01 means revision A.

2.5

Channel A and B Selection

The UART provides the user with the capability to bi-directionally transfer information between an external

CPU and an external serial communication device. A LOW signal on the chip select pins, CSA# or CSB#,

allows the user to select UART channel A or B to configure, send transmit data and/or unload receive data to/

from the UART. Selecting both UARTs can be useful during power up initialization to write to the same internal

7

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

registers, but do not attempt to read from both uarts simultaneously. Individual channel select functions are

shown in Table 1.

TABLE 1: CHANNEL A AND B SELECT

CSA#

CSB#

FUNCTION

1

0

1

0

1

0

UART de-selected

Channel A selected

Channel B selected

Channel A and B selected

2.6

Channel A and B Internal Registers

Each UART channel in the V2750 has a set of enhanced registers for control, monitoring and data loading and

unloading. The configuration register set is compatible to those already available in the standard single

16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status

and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/

LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/

DLM/DLD), and a user accessible Scratchpad Register (SPR).

Beyond the general 16C2550 features and capabilities, the V2750 offers enhanced feature registers (EMSR,

FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware flow

control, Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO

trigger level control, and FIFO level counters. All the register functions are discussed in full detail later in

“Section 3.0, UART Internal Registers” on page 21.

2.7

DMA Mode

The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t

mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of

the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional

flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is

empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive

FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is

disabled (FCR bit-3 = 0), the V2750 is placed in single-character mode for data transmit or receive operation.

When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or

unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode, the V2750

sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO

becomes empty. The following table shows their behavior. Also see Figures 17 through 22.

TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE

FCR BIT-0=0

PINS

FCR BIT-0=1 (FIFO ENABLED)

(FIFO DISABLED)

FCR Bit-3 = 0

FCR Bit-3 = 1

(DMA Mode Disabled)

(DMA Mode Enabled)

RXRDY# A/B LOW = 1 byte.

HIGH = no data.

LOW = at least 1 byte in FIFO.

HIGH = FIFO empty.

HIGH to LOW transition when FIFO reaches the

trigger level, or time-out occurs.

LOW to HIGH transition when FIFO empties.

TXRDY# A/B LOW = THR empty. LOW = FIFO empty.

LOW = FIFO has at least 1 empty location.

HIGH = byte in THR. HIGH = at least 1 byte in FIFO. HIGH = FIFO is full.

8

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

2.8

INTA and INTB Outputs

The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.

Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see Figures 17

through 22.

TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER

Auto RS485

Mode

FCR BIT-0 = 0

FCR BIT-0 = 1 (FIFO ENABLED)

LOW = FIFO above trigger level

(FIFO DISABLED)

INTA/B Pin

NO

LOW = a byte in THR

HIGH = THR empty

HIGH = FIFO below trigger level or FIFO empty

YES

LOW = a byte in THR

LOW = FIFO above trigger level

HIGH = transmitter empty

HIGH = FIFO below trigger level or transmitter empty

TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER

FCR BIT-0 = 0

FCR BIT-0 = 1

(FIFO DISABLED)

(FIFO ENABLED)

INTA/B Pin

LOW = no data

HIGH = 1 byte

LOW = FIFO below trigger level

HIGH = FIFO above trigger level

2.9

Crystal Oscillator or External Clock Input

The V2750 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the

device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a

system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the

oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not

5V tolerant and so the maximum at the pin should be VCC. For programming details, see ““Section 2.10,

Programmable Baud Rate Generator with Fractional Divisor” on page 10.”

FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS

XTAL1

XTAL2

R1

0-120 Ω

(Optional)

R2

500 ΚΩ − 1 ΜΩ

1.8432 MHz

to

Y1

24 MHz

C1

C2

22-47 pF

9

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,

fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency

tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4). The programmable Baud

Rate Generator is capable of operating with a crystal oscillator frequency of up to 32 MHz at 2.5V. However,

with an external clock input on XTAL1 pin, it can extend its operation up to 64 MHz (8 Mbps serial data rate) at

3.3V with an 8X sampling rate. For further reading on the oscillator circuit please see the Application Note

DAN108 on the EXAR web site at http://www.exar.com.

2.10 Programmable Baud Rate Generator with Fractional Divisor

Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The

prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide

the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further

divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to

obtain a 16X or 8X sampling clock of the serial data rate. The sampling clock is used by the transmitter for data

bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the value

of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during

initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and

the DLD register provides the fractional part of the dvisior. Only the four lower bits of the DLD are implemented

and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming

the Baud Rate Generator Registers DLL, DLM and DLD provides the capability for selecting the operating data

rate. Table 5 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate.

If the pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 5. At

8X sampling rate, these data rates would double. Also, when using 8X sampling mode, please note that the bit-

time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number. When using a non-

standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s):

Required Divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16X mode EMSR[7] = 1

Required Divisor (decimal) = (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode EMSR[7] = 0

The closest divisor that is obtainable in the V2750 can be calculated using the following formula:

ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where

DLM = TRUNC(Required Divisor) >> 8

DLL = TRUNC(Required Divisor) & 0xFF

DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)

In the formulas above, please note that:

TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.

ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.

A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.

10

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

FIGURE 5. BAUD RATE GENERATOR

To Other

Channel

DLL, DLM and DLD

Registers

MCR Bit-7=0

(default)

Prescaler

Divide by 1

16X or 8X

Sampling

Rate Clock

to Transmitter

and Receiver

Crystal

Osc/

Buffer

XTAL1

XTAL2

Fractional Baud

Rate Generator

Logic

Prescaler

Divide by 4

MCR Bit-7=1

TABLE 5: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING

Required

Output Data

Rate

DIVISOR FOR

16x Clock

(Decimal)

DIVISOR

OBTAINABLE IN

V2750

DLM PROGRAM DLL PROGRAM DLD PROGRAM DATA ERROR

VALUE (HEX)

RATE (%)

400

2400

3750

625

3750

625

E

2

1

0

A6

71

38

9C

96

4E

3C

34

27

1E

1A

14

F

0

8

4

0

2

0

1

0

1

0

C

8

B

8

0

C

4

0

A

8

0

4800

312.5

156.25

150

312 8/16

156 4/16

150

0

9600

0

10000

19200

25000

28800

38400

50000

57600

75000

100000

115200

153600

200000

225000

230400

250000

300000

400000

460800

500000

750000

921600

1000000

0

78.125

60

78 2/16

60

0

52.0833

39.0625

30

52 1/16

39 1/16

30

0.04

0

26.0417

20

26 1/16

20

0.08

0

15

0

13.0208

9.7656

7.5

13

D

0.16

0

9 12/16

7 8/16

6 11/16

6 8/16

6

9

7

6.6667

6.5104

6

0.31

0.16

0

6

5

0

3.75

3 12/16

3 4/16

3

0

3.2552

3

0.16

0

3

2

0

1.6276

1.5

1 10/16

1 8/16

1

0.16

0

1

11

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

2.11 Transmitter

The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which

includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X internal

clock. A bit time is 16 (8) clock periods (see EMSR bit-7). The transmitter sends the start-bit followed by the

number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and

TSR are reported in the Line Status Register (LSR bit-5 and bit-6).

2.11.1 Transmit Holding Register (THR) - Write Only

The transmit holding register is an 8-bit register providing a data interface to the host processor. The host

writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,

parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input

register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write

operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data

location.

2.11.2 Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the

data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled

by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.

FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE

Transmit

Holding

Register

(THR)

Data

Byte

THR Interrupt (ISR bit-1)

Enabled by IER bit-1

16X or 8X

Clock

(EMSR Bit-7)

M

S

B

L

S

B

Transmit Shift Register (TSR)

TXNOFIFO1

2.11.3 Transmitter Operation in FIFO Mode

The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set

whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the

amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by

IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.

12

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE

Transmit

FIFO

Transmit

Data Byte

THR Interrupt (ISR bit-1) falls

below the programmed Trigger

Level and then when becomes

empty. FIFO is Enabled by FCR

bit-0=1

Auto CTS Flow Control (CTS# pin)

Flow Control Characters

(Xoff1/2 and Xon1/2 Reg.

Auto Software Flow Control

16X or 8X Clock

(EMSR bit-7)

Transmit Data Shift Register

(TSR)

TXFIFO1

2.12 Receiver

The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a

byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X clock (EMSR bit-7) for timing. It verifies

and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or

false start bit, an internal receiver counter starts counting at the 16X/8X clock rate. After 8 clocks (or 4 if 8X) the

start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic

0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character.

The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing.

If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte

from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status

of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character

or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a

receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus

12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.

2.12.1 Receive Holding Register (RHR) - Read-Only

The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift

Register. It provides the receive data interface to the host processor. The RHR register is part of the receive

FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When

the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the

RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data

byte are immediately updated in the LSR bits 2-4.

13

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE

16X or 8X Clock

(EMSR bit-7)

Receive Data Shift

Data Bit

Register (RSR)

Validation

Receive Data Characters

Error

Receive

Data Byte

and Errors

Receive Data

Holding Register

(RHR)

Tags in

LSR bits

4:2

RHR Interrupt (ISR bit-2)

RXFIFO1

FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE

16X or 8X Clock

(EMSR bit-7)

Receive Data Shift

Register (RSR)

Data Bit

Validation

Receive Data Characters

Example

- RX FIFO trigger level selected at 16

:

bytes

(See Note Below)

RTS# re-asserts when data falls below the flow

control trigger level to restart remote transmitter.

Enable by EFR bit-6=1, MCR bit-1.

64 bytes by 11-bit

wide

Data falls to

8

FIFO

Receive

Data FIFO

FIFO

Trigger=16

RHR Interrupt (ISR bit-2) programmed for

desired FIFO trigger level.

FIFO is Enabled by FCR bit-0=1

Data fills to

24

RTS# de-asserts when data fills above the flow

control trigger level to suspend remote transmitter.

Enable by EFR bit-6=1, MCR bit-1.

Receive

Data

Receive Data

Byte and Errors

RXFIFO1

NOTE: Table-B selected as Trigger Table for Figure 9 (Table 10).

14

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

2.13 Auto RTS (Hardware) Flow Control

Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#

output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control

features is enabled to fit specific application requirement (see Figure 10):

• Enable auto RTS flow control using EFR bit-6.

• The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).

If using the Auto RTS interrupt:

• Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the

RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.

2.14

Auto RTS Hysteresis

The V2750 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with

the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt

is generated when the receive FIFO reaches the programmed RX trigger level. The RTS# pin will not be forced

HIGH (RTS off) until the receive FIFO reaches the upper limit of the hysteresis level. The RTS# pin will return

LOW after the RX FIFO is unloaded to the lower limit of the hysteresis level. Under the above described

conditions, the V2750 will continue to accept data until the receive FIFO gets full. The Auto RTS function is

initiated when the RTS# output pin is asserted LOW (RTS On). Table 13 shows the complete details for the

Auto RTS# Hysteresis levels. Please note that this table is for programmable trigger levels only (Table D). The

hysteresis values for Tables A-C are the next higher and next lower trigger levels in the corresponding table.

2.15

Auto CTS Flow Control

Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is

monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific

application requirement (see Figure 10):

• Enable auto CTS flow control using EFR bit-7.

If using the Auto CTS interrupt:

• Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the

CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as

the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-

asserted (LOW), indicating more data may be sent.

15

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

FIGURE 10. AUTO RTS AND CTS FLOW CONTROL OPERATION

Local UART

UARTA

Remote UART

UARTB

RXA

TXB

Receiver FIFO

Trigger Reached

Transmitter

RTSA#

TXA

CTSB#

RXB

Auto RTS

Trigger Level

Auto CTS

Monitor

Receiver FIFO

Trigger Reached

Transmitter

CTSA#

RTSB#

Auto CTS

Monitor

Auto RTS

Trigger Level

Assert RTS# to Begin

Transmission

1

10

11

ON

RTSA#

OFF

7

2

ON

3

CTSB#

TXB

8

Restart

9

Data Starts

6

Suspend

4

RXA FIFO

Receive

Data

RX FIFO

12

RTS High

Threshold

RTS Low

Threshold

5

RX FIFO

Trigger Level

INTA

(RXA FIFO

Interrupt)

RTSCTS1

The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of

remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO

(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-

tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA

monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows

(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-

mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),

UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until

next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB

with RTSB# and CTSA# controlling the data flow.

16

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

2.16 Auto Xon/Xoff (Software) Flow Control

When software flow control is enabled (See Table 15), the V2750 compares one or two sequential receive data

characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the

programmed values, the V2750 will halt transmission (TX) as soon as the current character has completed

transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output

pin will be activated. Following a suspension due to a match of the Xoff character, the V2750 will monitor the

receive data stream for a match to the Xon-1,2 character. If a match is found, the V2750 will resume operation

and clear the flags (ISR bit-4).

Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to 0x00. Following reset the user can

write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff

characters (See Table 15) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are

selected, the V2750 compares two consecutive receive characters with two software flow control 8-bit values

(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control

mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.

In the event that the receive buffer is overfilling and flow control needs to be executed, the V2750 automatically

sends an Xoff message via the serial TX output to the remote modem. The V2750 sends the Xoff-1,2

characters two-character times (= time taken to send two characters at the programmed baud rate) after the

receive FIFO crosses the programmed trigger level (for all trigger tables). To clear this condition, the V2750 will

transmit the programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the

programmed trigger level (for Trigger Tables A, B, and C) or when receive FIFO is less than the trigger level

minus the hysteresis value (for Trigger Table D). This hysteresis value is the same as the Auto RTS Hysteresis

value in Table 14. Table 6 below explains this when Trigger Table-B (See Table 10) is selected.

TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL

XOFF CHARACTER(S) SENT

(CHARACTERS IN RX FIFO)

XON CHARACTER(S) SENT

(CHARACTERS IN RX FIFO)

RX TRIGGER LEVEL

INT PIN ACTIVATION

8

8*

0

8

16

24

28

16

24

28

16*

24*

28*

16

24

* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2

characters); for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.

2.17

Special Character Detect

A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced

Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal

incoming RX data.

The V2750 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will

be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal

Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is

dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of

character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also

determines the number of bits that will be used for the special character comparison.

2.18

Auto RS485 Half-duplex Control

The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR

bit-3. By default, it de-asserts RTS# (HIGH) output following the last stop bit of the last character that has been

transmitted. This helps in turning around the transceiver to receive the remote station’s response. When the

host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit FIFO. The

transmitter automatically re-asserts RTS# (LOW) output prior to sending the data. The RS485 half-duplex

direction control output can be inverted by enabling EMSR bit-3.

17

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

2.19 Infrared Mode

The V2750 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data

Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit

wide HIGH-pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the

infrared LED, hence reduces the power consumption. See Figure 11 below.

The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature

is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level

of logic zero from a reset and power up, see Figure 11.

Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.

Each time it senses a light pulse, it returns a logic 1 to the data bit stream. However, this is not true with some

infrared modules on the market which indicate a logic 0 by a light pulse. So the V2750 has a provision to invert

the input polarity to accommodate this. In this case user can enable FCTR bit-2 to invert the input signal.

FIGURE 11. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING

Character

Data Bits

1

0

TX Data

Transmit

IR Pulse

(TX Pin)

1/2 Bit Time

Bit Time

3/16 Bit Time

IrEncoder-1

Receive

IR Pulse

(RX pin)

Bit Time

1/16 Clock Delay

1

1 1

1

0

RX Data

Data Bits

Character

IRdecoder-

18

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

2.20

Sleep Mode with Auto Wake-Up

The V2750 supports low voltage system designs, hence, a sleep mode is included to reduce its power

consumption when the chip is not actively used.

All of these conditions must be satisfied for the V2750 to enter sleep mode:

■ no interrupts pending for both channels of the V2750 (ISR bit-0 = 1)

■ sleep mode of both channels are enabled (IER bit-4 = 1)

■ modem inputs are not toggling (MSR bits 0-3 = 0)

■ RX input pins are idling HIGH

The V2750 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for

no clock output as an indication that the device has entered the sleep mode.

The V2750 resumes normal operation by any of the following:

■ a receive data start bit transition (HIGH to LOW)

■ a data byte is loaded to the transmitter, THR or FIFO

■ a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#

If the V2750 is awakened by any one of the above conditions, it will return to the sleep mode automatically after

all interrupting conditions have been serviced and cleared. If the V2750 is awakened by the modem inputs, a

read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while

an interrupt is pending from channel A or B. The V2750 will stay in the sleep mode of operation until it is

disabled by setting IER bit-4 to a logic 0.

If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the

V2750 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical

Characteristics on page 40. If the input lines are floating or are toggling while the V2750 is in sleep mode, the

current can be up to 100 times more. If any of those signals are toggling or floating, then an external buffer

would be required to keep the address, data and control lines steady to achieve the low current. As an

alternative, please refer to the XR16L2751 which is pin-to-pin and software compatible with the V2750 but with

(some additional pins and) the PowerSave feature that eliminates any unnecessary external buffer.

A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the

first few receive characters may be lost. The number of characters lost during the restart also depends on your

operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep

RX A/B inputs idling HIGH or “marking” condition during sleep mode to avoid receiving a “break” condition

upon the restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type)

are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a

47k-100k ohm pull-up resistor on the RXA and RXB pins.

19

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

2.21 Internal Loopback

The V2750 UART provides an internal loopback capability for system diagnostic purposes. The internal

loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.

Figure 12 shows how the modem port signals are re-configured. Transmit data from the transmit shift register

output is internally routed to the receive shift register input allowing the system to receive the same data that it

was sending. The TX, RTS# and DTR# pins are held while the CTS#, DSR# CD# and RI# inputs are ignored.

Caution: the RX input pin must be held HIGH during loopback test else upon exiting the loopback test the

UART may detect and report a false “break” signal. Also, Auto RTS/CTS flow control is not supported during

internal loopback.

FIGURE 12. INTERNAL LOOP BACK IN CHANNEL A AND B

VCC

TXA/TXB

Transmit Shift Register

(THR/FIFO)

MCR bit-4=1

Receive Shift Register

(RHR/FIFO)

RXA/RXB

VCC

RTSA#/RTSB#

RTS#

CTS#

CTSA#/CTSB#

VCC

DTRA#/DTRB#

DTR#

DSR#

DSRA#/DSRB#

OP1#

RI#

RIA#/RIB#

VCC

OP2A#/OP2B#

OP2#

CD#

CDA#/CDB#

20

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

3.0 UART INTERNAL REGISTERS

Each of the UART channel in the V2750 has its own set of configuration registers selected by address lines A0,

A1 and A2 with CSA# or CSB# selecting the channel. The complete register set is shown on Table 7 and

Table 8.

TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS

ADDRESSES

REGISTER

READ/WRITE

COMMENTS

A2 A1 A0

16C550 COMPATIBLE REGISTERS

0

0 0

RHR - Receive Holding Register

Read-only

Write-only

LCR[7] = 0

THR - Transmit Holding Register

0

0 0

0 1

1 0

DLL - Divisor LSB

Read/Write

LCR[7] = 1, LCR ≠ 0xBF

DLM - Divisor MSB

DLD - Divisor Fractional

LCR[7] = 1, LCR ≠ 0xBF,

EFR[4] = 1

0

0 0

0 1

1 0

DREV - Device Revision Code

DVID - Device Identification Code

IER - Interrupt Enable Register

Read-only

Read/Write

DLL, DLM = 0x00,

LCR[7] = 1, LCR ≠ 0xBF

LCR[7] = 0

ISR - Interrupt Status Register

FCR - FIFO Control Register

Read-only

Write-only

LCR ≠ 0xBF

0

1

1 1

0 0

0 1

1 0

1 1

LCR - Line Control Register

Read/Write

Read-only

Read/Write

Read-only

Write-only

MCR - Modem Control Register

LSR - Line Status Register

LCR ≠ 0xBF

MSR - Modem Status Register

SPR - Scratch Pad Register

LCR ≠ 0xBF, FCTR[6] = 0

LCR ≠ 0xBF, FCTR[6] = 1

FLVL - RX/TX FIFO Level Counter Register

EMSR - Enhanced Mode Select Register

ENHANCED REGISTERS

0

0 0

TRG - RX/TX FIFO Trigger Level Register

FC - RX/TX FIFO Level Counter Register

Write-only

Read-only

0

1

0 1

1 0

0 0

0 1

1 0

1 1

FCTR - Feature Control Register

EFR - Enhanced Function Register

Xon-1 - Xon Character 1

Read/Write

LCR = 0xBF

Xon-2 - Xon Character 2

Xoff-1 - Xoff Character 1

Xoff-2 - Xoff Character 2

21

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

.

TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1

ADDRESS

A2-A0

REG

READ/

WRITE

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

COMMENT

NAME

16C550 Compatible Registers

0 0 0

0 0 1

RHR

THR

IER

RD

WR

Bit-7

0/

Bit-6

0/

Bit-5

0/

Bit-4

0/

Bit-3

Bit-2

Bit-1

Bit-0

RD/WR

Modem RXLine

Stat. Int.

Enable

TX

Empty

Int

RX

Data

Int.

LCR[7]=0

Stat.

Int.

CTS Int. RTS Int. Xoff Int.

Enable Enable Enable

Sleep

Mode

Enable

Enable Enable Enable

0 1 0

ISR

RD

FIFOs

Enabled Enabled

FIFOs

0/

INT

Source Source Source Source

Bit-3

INT

Bit-2

Bit-1

Bit-0

Source Source

Bit-5

Bit-4

LCR ≠ 0xBF

FCR

WR RXFIFO RXFIFO

Trigger Trigger

0/

DMA

Mode

Enable

TX

FIFO

Reset Reset

RX

FIFOs

FIFO Enable

TXFIFO TXFIFO

Trigger Trigger

0 1 1

1 0 0

LCR RD/WR Divisor Set TX Set Par-

Even

Parity

Enable

Stop

Bits

Word

Length Length

Bit-1 Bit-0

Word

Enable

Break

ity

MCR RD/WR

0/

Internal OP2#/INT Rsrvd RTS# DTR#

Lopback Output

Output Output

Control Control

(OP1#)

BRG

Pres-

caler

IR Mode XonAny

ENable

Enable

LCR ≠ 0xBF

1 0 1

LSR

RD

RX FIFO THR &

THR

Empty

RX

Break

RX Fram-

ing Error Parity Over-

RX

Data

Ready

Global

Error

TSR

Empty

Error

run

Error

1 1 0

1 1 1

MSR

CD#

RI#

DSR#

Input

CTS#

Input

Delta

CD#

Delta

RI#

Delta

DSR# CTS#

Delta

Input

SPR RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0 LCR ≠ 0xBF

FCTR[6]=0

1 1 1

EMSR

WR

16X

LSR

Error

Inter-

rupt.

Imd/Dly#

Auto

RS485

Output

Inversion

Rsrvd Rx/Tx Rx/Tx

FIFO FIFO

Count Count

Sam-

pling

Rate

RTS

Hyst.

RTS

Hyst.

bit-3

bit-2

LCR ≠ 0xBF

FCTR[6]=1

Mode

1 1 1

FLVL

RD

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

22

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1

ADDRESS

A2-A0

REG

READ/

WRITE

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

COMMENT

NAME

Baud Rate Generator Divisor

LCR[7]=1

0 0 0

0 0 1

0 1 0

DLL RD/WR

DLM RD/WR

DLD RD/WR

Bit-7

0

Bit-6

0

Bit-5

0

Bit-4

0

Bit-3

Bit-2

Bit-1

Bit-0

LCR ≠ 0xBF

LCR[7]=1

LCR ≠ 0xBF

EFR[4] = 1

0 0 0

0 0 1

DREV

DVID

RD

Bit-7

0

Bit-6

0

Bit-5

0

Bit-4

0

Bit-3

1

Bit-2

0

Bit-1

1

Bit-0

0

LCR[7]=1

LCR≠ 0xBF

DLL=0x00

DLM=0x00

Enhanced Registers

0 0 0

0 0 1

TRG

FC

WR

RD

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

FCTR RD/WR RX/TX SCPAD

Trig

Table

Bit-1

Trig

Table

Bit-0

Auto

RX IR

Input

Inv.

Auto

RTS

Hyst

Bit-1

Auto

RTS

Hyst

Bit-0

Mode

Swap

RS485

Direction

Control

Enable

0 1 0

EFR RD/WR

Auto

CTS

Enable Enable

Auto

RTS

Special

Char

Select

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

IER [7:4],

ISR [5:4],

FCR[5:4],

LCR=0XBF

MCR[7:5],

DLD

Bit-2

Bit-1

Bit-0

Bit-3

1 0 0

1 0 1

1 1 0

1 1 1

XON1 RD/WR

XON2 RD/WR

XOFF1 RD/WR

XOFF2 RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

4.0 INTERNAL REGISTER DESCRIPTIONS

4.1 Receive Holding Register (RHR) - Read- Only

SEE”RECEIVER” ON PAGE 13.

4.2 Transmit Holding Register (THR) - Write-Only

SEE”TRANSMITTER” ON PAGE 12.

4.3 Interrupt Enable Register (IER) - Read/Write

The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status

and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).

23

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

4.3.1 IER versus Receive FIFO Interrupt Mode Operation

When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts

(see ISR bits 2 and 3) status will reflect the following:

A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed

trigger level. It will be cleared when the FIFO drops below the programmed trigger level.

B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register

status bit and the interrupt will be cleared when the FIFO drops below the trigger level.

C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to

the receive FIFO. It is reset when the FIFO is empty.

4.3.2

IER versus Receive/Transmit FIFO Polled Mode Operation

When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16V2750 in the FIFO

polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can

be used in the polled mode by selecting respective transmit or receive control bit(s).

A. LSR BIT-0 indicates there is data in RHR or RX FIFO.

B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.

C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.

D. LSR BIT-5 indicates THR is empty.

E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.

F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.

IER[0]: RHR Interrupt Enable

The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when

the receive FIFO has reached the programmed trigger level in the FIFO mode.

• Logic 0 = Disable the receive data ready interrupt (default).

• Logic 1 = Enable the receiver data ready interrupt.

IER[1]: THR Interrupt Enable

This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-

FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is

empty when this bit is enabled, an interrupt will be generated.

• Logic 0 = Disable Transmit Ready interrupt (default).

• Logic 1 = Enable Transmit Ready interrupt.

IER[2]: Receive Line Status Interrupt Enable

If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller

about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the

character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of

the FIFO (default). Instead, LSR bits 2-4 can be programmed to generate an interrupt immediately, by setting

EMSR bit-6 to a logic 1.

• Logic 0 = Disable the receiver line status interrupt (default).

• Logic 1 = Enable the receiver line status interrupt.

IER[3]: Modem Status Interrupt Enable

• Logic 0 = Disable the modem status register interrupt (default).

• Logic 1 = Enable the modem status register interrupt.

24

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)

• Logic 0 = Disable Sleep Mode (default).

• Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.

IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)

• Logic 0 = Disable the software flow control, receive Xoff interrupt (default).

• Logic 1 = Enable the receive Xoff interrupt. See Software Flow Control section for details.

IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)

• Logic 0 = Disable the RTS# interrupt (default).

• Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition

from low to high.

IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)

• Logic 0 = Disable the CTS# interrupt (default).

• Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from

low to high.

4.4

Interrupt Status Register (ISR) - Read-Only

The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The

Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the

ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be

serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt

Source Table, Table 9, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources

associated with each of these interrupt levels.

4.4.1

Interrupt Generation:

• LSR is by any of the LSR bits 1, 2, 3 and 4.

• RXRDY is by RX trigger level.

• RXRDY Time-out is by a 4-char plus 12 bits delay timer.

• TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).

• MSR is by any of the MSR bits 0, 1, 2 and 3.

• Receive Xoff/Special character is by detection of a Xoff or Special character.

• CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.

• RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.

4.4.2

Interrupt Clearing:

• LSR interrupt is cleared by a read to the LSR register.

• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.

• RXRDY Time-out interrupt is cleared by reading RHR.

• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.

• MSR interrupt is cleared by a read to the MSR register.

• Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.

• Special character interrupt is cleared by a read to ISR or after the next character is received.

• RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.

25

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

]

TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL

PRIORITY

ISR REGISTER STATUS BITS

SOURCE OF INTERRUPT

LEVEL

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

1

2

3

4

5

6

7

-

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LSR (Receiver Line Status Register)

RXRDY (Receive Data Time-out)

RXRDY (Received Data Ready)

TXRDY (Transmit Ready)

MSR (Modem Status Register)

RXRDY (Received Xoff or Special character)

CTS#, RTS# change of state

None (default)

ISR[0]: Interrupt Status

• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt

service routine.

• Logic 1 = No interrupt pending (default condition).

ISR[3:1]: Interrupt Status

These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9).

ISR[4]: Xoff/Xon or Special Character Interrupt Status

This bit is set when EFR[4] = 1 and IER[5] = 1. ISR bit-4 indicates that the receiver detected a data match of

the Xoff character(s). If this is an Xoff interrupt, it can be cleared by a read to the ISR. If it is a special character

interrupt, it can be cleared by reading ISR or it will automatically clear after the next character received.

ISR[5]: RTS#/CTS# Interrupt Status

This bit is enabled when EFR[4] = 1. ISR bit-5 indicates that the CTS# or RTS# has been de-asserted.

ISR[7:6]: FIFO Enable Status

These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are

enabled.

4.5

FIFO Control Register (FCR) - Write-Only

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and

select the DMA mode. The DMA, and FIFO modes are defined as follows:

FCR[0]: TX and RX FIFO Enable

• Logic 0 = Disable the transmit and receive FIFO (default).

• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are

written or they will not be programmed.

FCR[1]: RX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

• Logic 0 = No receive FIFO reset (default)

• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

26

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

FCR[2]: TX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

• Logic 0 = No transmit FIFO reset (default).

• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[3]: DMA Mode Select

Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.

• Logic 0 = Normal Operation (default).

• Logic 1 = DMA Mode.

FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)

(logic 0 = default, TX trigger level = 1)

These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the

number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the

FIFO did not get filled over the trigger level on last re-load. Table 10 below shows the selections. EFR bit-4

must be set to ‘1’ before these bits can be accessed. Note that the receiver and the transmitter cannot use

different trigger tables. Whichever selection is made last applies to both the RX and TX side.

FCR[7:6]: Receive FIFO Trigger Select

(logic 0 = default, RX trigger level =1)

The FCTR Bits 5-4 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive

FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the

trigger level. Table 10 shows the complete selections. Note that the receiver and the transmitter cannot use

different trigger tables. Whichever selection is made last applies to both the RX and TX side.

27

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION

TRANSMIT

TRIGGER

LEVEL

TRIGGER FCTR FCTR

FCR

BIT-7

FCR

BIT-6

FCR

BIT-5

FCR

BIT-4

RECEIVE

TRIGGER LEVEL

COMPATIBILITY

TABLE

BIT-5

BIT-4

Table-A

0

1 (default)

16C550, 16C2550,

16C2552, 16C554,

16C580

0

1

0

1

0

1

1 (default)

4

8

14

Table-B

Table-C

Table-D

0

1

0

1

0

1

0

1

0

1

16

8

16C650A

24

30

0

1

0

1

0

1

8

16

24

28

0

1

0

1

0

1

8

16C654

16

32

56

0

1

0

1

0

1

8

16

56

60

X

Programmable Programmable 16L2752, 16C2850,

16C2852, 16C850,

16C854, 16C864

via TRG

register.

FCTR[7] = 0.

FCTR[7] = 1.

4.6

Line Control Register (LCR) - Read/Write

The Line Control Register is used to specify the asynchronous data communication format. The word or

character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this

register.

LCR[1:0]: TX and RX Word Length Select

These two bits specify the word length to be transmitted or received.

BIT-1

BIT-0

WORD LENGTH

0

1

0

1

0

1

5 (default)

6

7

8

28

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

LCR[2]: TX and RX Stop-bit Length Select

The length of stop bit is specified by this bit in conjunction with the programmed word length.

STOP BIT LENGTH

(BIT TIME(S))

WORD

LENGTH

BIT-2

0

1

5,6,7,8

5

1 (default)

1-1/2

2

6,7,8

LCR[3]: TX and RX Parity Select

Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data

integrity check. See Table 11 for parity selection summary below.

• Logic 0 = No parity.

• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the

data character received.

LCR[4]: TX and RX Parity Select

If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.

• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format (default).

• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format.

LCR[5]: TX and RX Parity Select

If the parity bit is enabled, LCR BIT-5 selects the forced parity format.

• LCR BIT-5 = logic 0, parity is not forced (default).

• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive

data.

• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive

data.

TABLE 11: PARITY SELECTION

LCR BIT-5 LCR BIT-4 LCR BIT-3

PARITY SELECTION

No parity

X

0

1

X

0

1

0

1

0

1

Odd parity

Even parity

Force parity to mark, “1”

Forced parity to space, “0”

29

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

LCR[6]: Transmit Break Enable

When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a

“space", LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.

• Logic 0 = No TX break condition (default).

• Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line

break condition.

LCR[7]: Baud Rate Divisors Enable

Baud rate generator divisor (DLL, DLM and DLD) enable.

• Logic 0 = Data registers are selected (default).

• Logic 1 = Divisor latch registers are selected.

4.7

Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write

The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.

MCR[0]: DTR# Output

The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a

general purpose output.

• Logic 0 = Force DTR# output HIGH (default).

• Logic 1 = Force DTR# output LOW.

MCR[1]: RTS# Output

The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by

EFR bit-6. The RTS# pin can also be used for Auto RS485 Half-Duplex direction control enabled by FCTR bit-

3. If the modem interface is not used, this output may be used as a general purpose output.

• Logic 0 = Force RTS# HIGH (default).

• Logic 1 = Force RTS# LOW.

MCR[2]: Reserved

OP1# is not available as an output pin on the V2750. But it is available for use during Internal Loopback Mode.

In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.

MCR[3]: OP2# Output / INT Output Enable

This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used

as a general purpose output.

• Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).

• Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.

MCR[4]: Internal Loopback Enable

• Logic 0 = Disable loopback mode (default).

• Logic 1 = Enable local loopback mode, see loopback section and Figure 12.

MCR[5]: Xon-Any Enable (requires EFR bit-4=1)

• Logic 0 = Disable Xon-Any function (default).

• Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.

The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and

the V2750 is programmed to use the Xon/Xoff flow control.

30

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit-4=1)

• Logic 0 = Enable the standard modem receive and transmit input/output interface (default).

• Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the

infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface

requirement. While in this mode, the infrared TX output will be idling LOW. SEE”INFRARED MODE” ON

PAGE 18.

MCR[7]: Clock Prescaler Select (requires EFR bit-4=1)

• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable

Baud Rate Generator without further modification, i.e., divide by one (default).

• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and

feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.

4.8

Line Status Register (LSR) - Read Only

This register provides the status of data transfers between the UART and the host.

LSR[0]: Receive Data Ready Indicator

• Logic 0 = No data in receive holding register or FIFO (default).

• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.

LSR[1]: Receiver Overrun Error Flag

• Logic 0 = No overrun error (default).

• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens

when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register

is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

LSR[2]: Receive Data Parity Error Tag

• Logic 0 = No parity error (default).

• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.

This error is associated with the character available for reading in RHR.

LSR[3]: Receive Data Framing Error Tag

• Logic 0 = No framing error (default).

• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with

the character available for reading in RHR.

LSR[4]: Receive Break Error Tag

• Logic 0 = No break condition (default).

• Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the

FIFO mode, only one break character is loaded into the FIFO.

LSR[5]: Transmit Holding Register Empty Flag

This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte

is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0

concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set

when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.

31

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

LSR[6]: THR and TSR Empty Flag

This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or

TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and

transmit shift register are both empty.

LSR[7]: Receive FIFO Data Error Flag

• Logic 0 = No FIFO error (default).

• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error

or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the

RX FIFO.

4.9

Modem Status Register (MSR) - Read Only

This register provides the current state of the modem interface input signals. Lower four bits of this register are

used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem

changes state. These bits may be used for general purpose inputs when they are not used with modem

signals.

MSR[0]: Delta CTS# Input Flag

• Logic 0 = No change on CTS# input (default).

• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[1]: Delta DSR# Input Flag

• Logic 0 = No change on DSR# input (default).

• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[2]: Delta RI# Input Flag

• Logic 0 = No change on RI# input (default).

• Logic 1 = The RI# input has changed from a LOW to HIGH, ending of the ringing signal. A modem status

interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[3]: Delta CD# Input Flag

• Logic 0 = No change on CD# input (default).

• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem

status interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[4]: CTS Input Status

CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto

CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the

modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has

finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of

the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The

CTS# input may be used as a general purpose input when the modem interface is not used.

MSR[5]: DSR Input Status

Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#

bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is

not used.

32

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

MSR[6]: RI Input Status

Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the

MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.

MSR[7]: CD Input Status

Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the

MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.

4.10 Scratch Pad Register (SPR) - Read/Write

This is a 8-bit general purpose register for the user to store temporary data. The content of this register is

preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.

4.11 Enhanced Mode Select Register (EMSR)

This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.

EMSR[1:0]: Receive/Transmit FIFO Level Count (Write-Only)

When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is

operating in.

TABLE 12: SCRATCHPAD SWAP SELECTION

FCTR[6] EMSR[1] EMSR[0]

Scratchpad is

0

1

X

0

1

X

0

1

Scratchpad

RX FIFO Level Counter Mode

TX FIFO Level Counter Mode

Alternate RX/TX FIFO Counter Mode

During Alternate RX/TX FIFO Level Counter Mode, the first value read after EMSR bits 1-0 have been

asserted will always be the RX FIFO Level Counter. The second value read will correspond with the TX FIFO

Level Counter. The next value will be the RX FIFO Level Counter again, then the TX FIFO Level Counter and

so on and so forth.

EMSR[2]: Reserved

EMSR[3]: Automatic RS485 Half-Duplex Control Output Inversion

• Logic 0 = RTS# output is LOW during TX and HIGH during RX (default, compatible with 16C2850).

• Logic 1 = RTS# output is HIGH during TX and LOW during RX.

33

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

EMSR[5:4]: Extended RTS Hysteresis

TABLE 13: AUTO RTS HYSTERESIS

RTS#

HYSTERESIS

(CHARACTERS)

EMSR

BIT-5

EMSR

BIT-4

FCTR

BIT-1

FCTR

BIT-0

0

1

0

1

0

1

0

±4

±6

±8

0

1

0

1

0

1

0

1

±8

±16

±24

±32

1

0

1

0

1

0

1

±40

±44

±48

±52

1

0

1

0

1

0

1

±12

±20

±28

±36

EMSR[6]: LSR Interrupt Mode

• Logic 0 = LSR Interrupt Delayed (for 16C2550 compatibility, default). LSR bits 2, 3, and 4 will generate an

interrupt when the character with the error is in the RHR.

• Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is

received into the FIFO.

EMSR[7]: 16X Sampling Rate Mode

Logic 0 = 8X Sampling Rate.

Logic 1 = 16X Sampling Rate (default).

4.12 FIFO Level Register (FLVL) - Read-Only

The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this is

not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.

FLVL[7:0]: FIFO Level Register

This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].

See Table 12 for details.

4.13 Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write

These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and

DLL is a 16-bit value is then added to DLD/16 to achieve the fractional baud rate divisor. DLD must be enabled

via EFR bit-4 before it can be accessed. SEE”PROGRAMMABLE BAUD RATE GENERATOR WITH

FRACTIONAL DIVISOR” ON PAGE 10.

4.14 Device Identification Register (DVID) - Read Only

This register contains the device ID (0x0A for XR16V2750). Prior to reading this register, DLL and DLM should

be set to 0x00 (DLD = 0xXX).

34

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

4.15 Device Revision Register (DREV) - Read Only

This register contains the device revision information. For example, 0x01 means revision A. Prior to reading

this register, DLL and DLM should be set to 0x00 (DLD = 0xXX).

4.16 Trigger Level Register (TRG) - Write-Only

User Programmable Transmit/Receive Trigger Level Register. If both the programmable TX and RX trigger

levels are used, the TX trigger levels must be set before the RX trigger levels.

TRG[7:0]: Trigger Level Register

These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects

between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).

4.17 RX/TX FIFO Level Count Register (FC) - Read-Only

This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count

Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is

suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1.

See Table 12.

FC[7:0]: RX/TX FIFO Level Count

Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter

FIFO (FCTR[7] = 1) can be read via this register. Reading this register is not recommended when transmitting

or receiving data.

4.18

Feature Control Register (FCTR) - Read/Write

This register controls the XR16V2750 functions that are not available in ST16C2450 or ST16C2550.

FCTR[1:0]: RTS Hysteresis

User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to

“0” to select the next trigger level for hardware flow control. See Table 13 for more details.

FCTR[2]: IrDa RX Inversion

• Logic 0 = Select RX input as encoded IrDa data (Idle state will be LOW).

• Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be HIGH).

FCTR[3]: Auto RS-485 Direction Control

• Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register

becomes empty and transmit shift register is shifting data out.

• Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its

output logic state from LOW to HIGH one bit time after the last stop bit of the last character is shifted out.

Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The

RTS# output pin will automatically return to a LOW when a data byte is loaded into the TX FIFO. However,

RTS# behavior can be inverted by setting EMSR[3] = 1.

35

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

FCTR[5:4]: Transmit/Receive Trigger Table Select

See Table 10 for more details.

REV. P1.0.0

TABLE 14: TRIGGER TABLE SELECT

FCTR

BIT-5

FCTR

BIT-4

TABLE

0

1

0

1

0

1

Table-A (TX/RX)

Table-B (TX/RX)

Table-C (TX/RX)

Table-D (TX/RX)

FCTR[6]: Scratchpad Swap

• Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.

• Logic 1 = FIFO Level Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of

characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced

Mode Select Register is selected when it is written into.

FCTR[7]: Programmable Trigger Register Select

If using both programmable TX and RX trigger levels, TX trigger levels must be set before RX trigger levels.

• Logic 0 = Registers TRG and FC selected for RX.

• Logic 1 = Registers TRG and FC selected for TX.

4.19 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive

character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes

are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that

whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before

programming a new setting.

EFR[3:0]: Software Flow Control Select

Single character and dual sequential characters software flow control is supported. Combinations of software

flow control can be selected by programming these bits.

36

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS

EFR BIT-3

EFR BIT-2

CONT-2

EFR BIT-1

CONT-1

EFR BIT-0

CONT-0

TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL

CONT-3

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

0

X

0

1

No TX and RX flow control (default and reset)

No transmit flow control

Transmit Xon1, Xoff1

Transmit Xon2, Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2

No receive flow control

Receiver compares Xon1, Xoff1

Receiver compares Xon2, Xoff2

Transmit Xon1, Xoff1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

0

1

0

1

0

1

Transmit Xon2, Xoff2

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

No transmit flow control,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

EFR[4]: Enhanced Function Bits Enable

Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, and DLD

to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values.

This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it

is recommended to leave it enabled, logic 1.

• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-

7, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5,

MCR bits 5-7, and DLD are set to a logic 0 to be compatible with ST16C550 mode (default).

• Logic 1 = Enables the above-mentioned register bits to be modified by the user.

EFR[5]: Special Character Detect Enable

• Logic 0 = Special Character Detect Disabled (default).

• Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with

data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set

to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If

flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work

normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works

normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character

interrupt, if enabled via IER bit-5.

37

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

EFR[6]: Auto RTS Flow Control Enable

RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is

selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and

RTS de-asserts HIGH at the next upper trigger level or hysteresis level. RTS# will return LOW when FIFO data

falls below the next lower trigger level. The RTS# output must be asserted (LOW) before the auto RTS can

take effect. RTS# pin will function as a general purpose output when hardware flow control is disabled.

• Logic 0 = Automatic RTS flow control is disabled (default).

• Logic 1 = Enable Automatic RTS flow control.

EFR[7]: Auto CTS Flow Control Enable

Automatic CTS Flow Control.

• Logic 0 = Automatic CTS flow control is disabled (default).

• Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH.

Data transmission resumes when CTS# returns LOW.

4.19.1 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write

These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.

For more details, see Table 6.

38

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B

REGISTERS

RESET STATE

DLM, DLL

DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up.

They do not reset when the Reset Pin is asserted.

DLD

RHR

THR

IER

Bits 7-0 = 0x00

Bits 7-0 = 0xXX

Bits 7-0 = 0x00

Bits 7-0 = 0x01

Bits 7-0 = 0x00

Bits 7-0 = 0x60

FCR

ISR

LCR

MCR

LSR

MSR

Bits 3-0 = Logic 0

Bits 7-4 = Logic levels of the inputs inverted

SPR

EMSR

FLVL

Bits 7-0 = 0xFF

Bits 7-0 = 0x80

Bits 7-0 = 0x00

RESET STATE

HIGH

EFR

XON1

XON2

XOFF1

XOFF2

FC

I/O SIGNALS

TX

OP2#

HIGH

RTS#

HIGH

DTR#

HIGH

RXRDY#

TXRDY#

INT

HIGH

LOW

Three-State Condition

39

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

ABSOLUTE MAXIMUM RATINGS

Power Supply Range

Voltage at Any Pin

4 Volts

GND-0.3V to 5.5V

o

Operating Temperature

-40 to +85 C

o

Storage Temperature

Package Dissipation

-65 to +150 C

500 mW

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)

o

Thermal Resistance (48-TQFP)

Thermal Resistance (32-QFN)

theta-ja =59 C/W, theta-jc = 16 C/W

o

theta-ja = 33 C/W, theta-jc = 22 C/W

ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS

TA=-40^OTO +85^OC, VCC IS 2.25V TO 3.6V

LIMITS

2.5V

LIMITS

SYMBOL

PARAMETER

3.3V

UNITS

CONDITIONS

MIN

MAX

MIN

MAX

V

Clock Input Low Level

Clock Input High Level

Input Low Voltage

-0.3

0.4

VCC

0.5

-0.3

0.6

V

ILCK

V

2.0

-0.3

1.8

2.4

-0.3

2.0

VCC

0.7

IHCK

V

IL

V

Input High Voltage

Output Low Voltage

5.5

IH

V

0.4

V

I

= 6 mA

= 4 mA

OL

0.4

V

Output High Voltage

2.4

V

I

= -4 mA

= -2 mA

OH

1.8

I

Input Low Leakage Current

Input High Leakage Current

Input Pin Capacitance

Power Supply Current

Sleep Current

±10

5

±10

5

uA

pF

IL

I

IH

C

IN

I

1.5

15

2.5

30

mA

uA

Ext Clk = 2MHz

See Test 1

CC

I

SLEEP

Test 1: The following inputs must remain steady at VCC or GND state to minimize Sleep current: A0-A2, D0-

D7, IOR#, IOW#, CSA#, CSB# and all modem inputs. Also, RXA and RXB inputs must idle HIGH while asleep.

Floating inputs will result in sleep currents in the mA range. For PowerSave feature that isolates address, data

and control signals, please see the XR16V2751 datasheet.

40

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

AC ELECTRICAL CHARACTERISTICS

UNLESS OTHERWISE NOTED: TA=-40^OTO +85^OC, VCC=2.25 - 3.63V, 70 PF LOAD WHERE APPLICABLE

LIMITS

SYMBOL

PARAMETER

2.5V ± 10%

3.3V ± 10%

UNIT

MIN

MAX

MIN

MAX

XTAL1

ECLK

UART Crystal Oscillator

32

50

24

64

MHz

ns

External Clock

T

External Clock Time Period

10

0

7

0

ECLK

T

Address Setup Time

ns

AS

T

Address Hold Time

0

AH

T

Chip Select Width

75

65

ns

CS

RD

DY

IOR# Strobe Width

ns

Read Cycle Delay

ns

T

Data Access Time

70

30

60

15

ns

RDV

T

Data Disable Time

0

ns

DD

T

IOW# Strobe Width

75

10

5

65

10

5

ns

WR

T

Write Cycle Delay

ns

DY

DS

DH

Data Setup Time

ns

Data Hold Time

ns

T

Delay From IOW# To Output

Delay To Set Interrupt From MODEM Input

Delay To Reset Interrupt From IOR#

Delay From Stop To Set Interrupt

Delay From IOR# To Reset Interrupt

Delay From Stop To Interrupt

Delay From Initial INT Reset To Transmit Start

Delay From IOW# To Reset Interrupt

Delay From Stop To Set RXRDY#

Delay From IOR# To Reset RXRDY#

Delay From IOW# To Set TXRDY#

Delay From Center of Start To Reset TXRDY#

Reset Pulse Width

50

1

50

1

ns

WDO

MOD

ns

T

ns

RSI

SSI

RRI

T

Bclk

ns

T

45

24

45

1

45

24

45

1

T

ns

SI

T

8

Bclk

ns

INT

T

WRI

SSR

Bclk

ns

T

45

8

45

8

RR

T

ns

WT

T

Bclk

ns

SRT

RST

40

Bclk

Baud Clock

16X or 8X of data rate

Hz

41

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

FIGURE 13. CLOCK TIMING

T_ECLK

T_ECL

T_ECH

VIH

External

Clock

VIL

FIGURE 14. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B

IOW #

Active

T_{W DO}

RTS#

DTR#

Change of state

CD#

CTS#

DSR#

Change of state

T_MOD

INT

Active

T_RSI

IOR#

Active

T_MOD

Change of state

RI#

42

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

FIGURE 15. DATA BUS READ TIMING

A0-A2

Valid Address

T_AS

T_AH

T_CS

CSA#/

CSB#

T_DY

T_RD

IOR#

T_DD

T_RDV

D0-D7

Valid Data

RDTm

FIGURE 16. DATA BUS WRITE TIMING

A0-A2

Valid Address

T_CS

Valid Address

T_CS

T_AS

T_AH

CSA#/

CSB#

T_DY

T_WR

IOW#

T_DH

T_DS

Valid Data

T_DS

Valid Data

D0-D7

16Write

43

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

FIGURE 17. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B

RX

Stop

Bit

Start

Bit

D0:D7

T_SSR

1 Byte

in RHR

INT

T_SSR

Active

Data

Active

Data

Active

Data

RXRDY#

Ready

T_RR

IOR#

(Reading data

out of RHR)

RXNFM

FIGURE 18. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B

TX

Stop

Bit

Start

Bit

D0:D7

IER[1]

enabled

ISR is read

INT*

T_WRI

T_SRT

TXRDY#

T_WT

IOW#

(Loading data

into THR)

*INT is cleared when the ISR is read or when data is loaded into the THR.

TXNonFIFO

44

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

FIGURE 19. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B

Start

Bit

RX

S

D0:D7

S

T

S

D0:D7

T

D0:D7

T_SSI

D0:D7

T

D0:D7

T

D0:D7

T

Stop

Bit

RX FIFO drops

below RX

Trigger Level

INT

T_SSR

FIFO

Empties

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

RXRDY#

First Byte is

Received in

RX FIFO

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXINTDMA#

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B

Start

Bit

Stop

Bit

RX

S

T

D0:D7

T

D0:D7

T_SSI

D0:D7

S

T

S

D0:D7

T

D0:D7

T

RX FIFO drops

below RX

Trigger Level

INT

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

T_SSR

FIFO

Empties

RXRDY#

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXFIFODMA

45

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX FIFO

Empty

TX

(Unloading)

T

S

T

S

T

S

D0:D7

T

S D0:D7

T

D0:D7

T

D0:D7

T

ISR is read

T_SI

IER[1]

enabled

ISR is read

T_SRT

INT*

TX FIFO

Empty

TX FIFO fills up

to trigger level

TX FIFO drops

below trigger level

T_WRI

Data in

TX FIFO

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.

TXDMA#

FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX

(Unloading)

S

D0:D7

T

D0:D7

S

D0:D7

S

D0:D7

S

D0:D7

T

S D0:D7

T

IER[1]

enabled

ISR Read

T_SI

T_SRT

INT*

TX FIFO fills up

to trigger level

TX FIFO drops

below trigger level

T_WRI

At least 1

empty location

in FIFO

TX FIFO

Full

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.

TXDMA

46

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)

D

1

36

25

37

24

D

1

D

48

13

1

2

B

e

A₂

C

A

Seating

Plane

A₁

α

L

Note: The control dimension is the millimeter column

INCHES MILLIMETERS

MAX

SYMBOL

MIN

MAX

1.20

0.15

A

0.039

0.002

0.047

0.006

1.00

0.05

A

1

2

0.037

0.041

0.95

1.05

B

0.007

0.004

0.346

0.272

0.011

0.008

0.362

0.280

0.17

0.09

8.80

6.90

0.27

0.20

9.20

7.10

C

D

1

e

L

a

0.020 BSC

0.50 BSC

0.018

0.030

0.45

0.75

0°

7°

0°

7°

47

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)

D2

D

D2

L

b

e

Note: The actual center pad is

metallic and the size (D2) is

device-dependent with a typical

tolerance of 0.3mm

A1

Steating Plane

A

A3

Note: The control dimension is in millimeter.

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

0.039

0.002

0.010

0.201

0.150

0.012

MIN

MAX

1.00

0.05

0.25

5.10

3.80

0.30

A

A1

A3

D

0.031

0.000

0.006

0.193

0.138

0.007

0.80

0.00

0.15

4.90

3.50

0.18

D2

b

e

0.0197 BSC

0.012 0.020

0.50 BSC

L

0.30

0.50

48

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REVISION HISTORY

DATE

REVISION

DESCRIPTION

June 2006

P1.0.0

Preliminary Datasheet.

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to

improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any

circuits described herein, conveys no license under any patent or other right, and makes no representation that

the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration

purposes and may vary depending upon a user’s specific application. While the information in this publication

has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the

failure or malfunction of the product can reasonably be expected to cause failure of the life support system or

to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless

EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has

been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately

protected under the circumstances.

Datasheet June 2006.

Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

49

XR16V2750

PRELIMINARY

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. P1.0.0

TABLE OF CONTENTS

GENERAL DESCRIPTION ................................................................................................ 1

APPLICATIONS............................................................................................................................................... 1

FEATURES .................................................................................................................................................... 1

FIGURE 1. XR16V2750 BLOCK DIAGRAM ......................................................................................................................................... 1

FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2

ORDERING INFORMATION................................................................................................................................ 2

PIN DESCRIPTIONS ........................................................................................................ 3

1.0 PRODUCT DESCRIPTION....................................................................................................................... 6

2.0 FUNCTIONAL DESCRIPTIONS............................................................................................................... 7

2.1 CPU INTERFACE................................................................................................................................................. 7

FIGURE 3. XR16V2750 DATA BUS INTERCONNECTIONS ................................................................................................................... 7

2.2 5-VOLT TOLERANT INPUTS .............................................................................................................................. 7

2.3 DEVICE RESET ................................................................................................................................................... 7

2.4 DEVICE IDENTIFICATION AND REVISION........................................................................................................ 7

2.5 CHANNEL A AND B SELECTION....................................................................................................................... 7

TABLE 1: CHANNEL A AND B SELECT ............................................................................................................................................... 8

2.6 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................... 8

2.7 DMA MODE.......................................................................................................................................................... 8

TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE ............................................................................................. 8

2.8 INTA AND INTB OUTPUTS................................................................................................................................. 9

TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER ........................................................................................................ 9

TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................... 9

2.9 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT................................................................................ 9

FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS................................................................................................................................. 9

2.10 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR.......................................... 10

FIGURE 5. BAUD RATE GENERATOR ............................................................................................................................................... 11

TABLE 5: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................... 11

2.11 TRANSMITTER................................................................................................................................................ 12

2.11.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY......................................................................................... 12

2.11.2 TRANSMITTER OPERATION IN NON-FIFO MODE.................................................................................................. 12

FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 12

2.11.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 12

FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 13

2.12 RECEIVER ....................................................................................................................................................... 13

2.12.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 13

FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................... 14

FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ......................................................................... 14

2.13 AUTO RTS (HARDWARE) FLOW CONTROL ................................................................................................ 15

2.14 AUTO RTS HYSTERESIS............................................................................................................................... 15

2.15 AUTO CTS FLOW CONTROL........................................................................................................................ 15

FIGURE 10. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 16

2.16 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 17

TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 17

2.17 SPECIAL CHARACTER DETECT.................................................................................................................. 17

2.18 AUTO RS485 HALF-DUPLEX CONTROL ..................................................................................................... 17

2.19 INFRARED MODE ........................................................................................................................................... 18

FIGURE 11. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING .......................................................................... 18

2.20 SLEEP MODE WITH AUTO WAKE-UP.......................................................................................................... 19

2.21 INTERNAL LOOPBACK................................................................................................................................. 20

FIGURE 12. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 20

3.0 UART INTERNAL REGISTERS ............................................................................................................. 21

TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS ....................................................................................... 21

TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ......................................... 22

4.0 INTERNAL REGISTER DESCRIPTIONS............................................................................................... 23

4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 23

4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 23

4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE................................................................................. 23

4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 24

4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 24

I

PRELIMINARY

XR16V2750

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 25

4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 25

4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 25

TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 26

4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ 26

TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 28

4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 28

TABLE 11: PARITY SELECTION ........................................................................................................................................................ 29

4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE . 30

4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 31

4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 32

4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 33

4.11 ENHANCED MODE SELECT REGISTER (EMSR)......................................................................................... 33

TABLE 12: SCRATCHPAD SWAP SELECTION .................................................................................................................................... 33

TABLE 13: AUTO RTS HYSTERESIS ................................................................................................................................................ 34

4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY ............................................................................................ 34

4.13 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD) - READ/WRITE ....................................... 34

4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY....................................................................... 34

4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY................................................................................. 35

4.16 TRIGGER LEVEL REGISTER (TRG) - WRITE-ONLY.................................................................................... 35

4.17 RX/TX FIFO LEVEL COUNT REGISTER (FC) - READ-ONLY ....................................................................... 35

4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE .......................................................................... 35

TABLE 14: TRIGGER TABLE SELECT ............................................................................................................................................... 36

4.19 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 36

TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 37

4.19.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE.............................. 38

TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B ............................................................................................ 39

ABSOLUTE MAXIMUM RATINGS ................................................................................. 40

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 40

ELECTRICAL CHARACTERISTICS............................................................................... 40

DC ELECTRICAL CHARACTERISTICS............................................................................................................. 40

TA=-40o to +85oC, Vcc is 2.25V to 3.6V ............................................................................................................... 40

AC ELECTRICAL CHARACTERISTICS............................................................................................................. 41

Unless otherwise noted: TA=-40o to +85oC, Vcc=2.25 - 3.63V, 70 pF load where applicable................................ 41

FIGURE 13. CLOCK TIMING............................................................................................................................................................. 42

FIGURE 14. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 42

FIGURE 16. DATA BUS WRITE TIMING ............................................................................................................................................ 43

FIGURE 15. DATA BUS READ TIMING.............................................................................................................................................. 43

FIGURE 17. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 44

FIGURE 18. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 44

FIGURE 19. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 45

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 45

FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ........................... 46

FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 46

PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm) .................................................................................. 47

PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm).............................................. 48

REVISION HISTORY ..................................................................................................................................... 49

TABLE OF CONTENTS ..................................................................................................... I

II


型号：	XR16V2750
厂家：	EXAR CORPORATION
描述：	HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 具有64字节FIFO高性能DUART 先进先出芯片
文件：	总51页 (文件大小：1074K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XR16V2750 [EXAR]

相关型号：

XR16V2750IL-F

XR16V2750IL32

XR16V2750IM

XR16V2750IM-F

XR16V2750_07

XR16V2750_0709

XR16V2751

XR16V2751IM

XR16V2751_07

XR16V2751_0709

XR16V2752

XR16V2752IJ