SP708TEN-L_技术文档

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

June 2010

Rev. 2.0.0

GENERAL DESCRIPTION

APPLICATIONS

The SP706R/S/T and SP708R/S/T series is a

family of microprocessor (µP) supervisory

circuits that integrate myriad components

involved in discrete solutions which monitor

power-supply and battery in µP and digital

systems.

• Processors & DSPs Based Systems

• Industrial & Medical Instruments

FEATURES

• Precision Low Voltage Monitor

− SP706R/SP708R: +2.63V

− SP706S/SP708S: +2.93V

− SP706T/SP708T: +3.08V

The SP706R/S/T and SP708R/S/T series will

significantly improve system reliability and

operational efficiency when compared to

solutions obtained with discrete components.

The features of the SP706R/S/T and

SP708R/S/T series include a watchdog timer, a

µP reset, a Power Fail Comparator, and a

manual-reset input.

• 200ms RESET Pulse Width

− SP706R/S/T: Active Low

− SP708R/S/T: Active High and Active Low

• Independent Watchdog Timer

− 1.6s Timeout (SP706R/S/T)

− Enable/Disable Function

The SP706R/S/T and SP708R/S/T series is

ideal for 3.0V or 3.3V applications in

automotive systems, computers, controllers,

and intelligent instruments. The SP706R/S/T

and SP708R/S/T series is an ideal solution for

systems in which critical monitoring of the

power supply to the µP and related digital

components is demanded.

• 40µA Maximum Supply Current

• Debounced TTL/CMOS Manual Reset

Input

• RESET Asserted Down to V_CC=1V

• V_CCGlitch Immunity

• Voltage Monitor for Power Failure or

Low Battery Warning

• 8-Pin NSOIC and MSOP Packages

• Pin Compatible with Industry

Standards 706R/S/T and 708R/S/T

Part Number

RESET Threshold

RESET Active

Manual RESET

Watchdog

PFI Accuracy

Yes

No

SP706R

SP706S

SP706T

SP708R

SP708S

SP708T

Low

Yes

4%

2.63V

2.93V

3.08V

2.63V

2.93V

3.08V

Low

Low and High

No

Exar Corporation

www.exar.com

48720 Kato Road, Fremont CA 94538, USA

Tel. +1 510 668-7000 – Fax. +1 510 668-7001

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

ESD Rating (HBM - Human Body Model) ....................2kV

ABSOLUTE MAXIMUM RATINGS

Continuous Power Dissipation

These are stress ratings only and functional operation of

the device at these ratings or any other above those

indicated in the operation sections of the specifications

below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may affect

reliability.

SO (derate 5.88mW/°C above +70°C)...............471mW

Mini SO (derate 4.10mW/°C above +70°C)........330mW

Storage Temperature ..............................-65°C to 160°C

Lead Temperature (Soldering, 10 sec)....................300°C

V_CC..........................................................-0.3V to 6.0V

All Other Inputs (Note 1)...................-0.3V to (V_CC+0.3V)

Input Current

VCC.................................................................20mA

GND ................................................................20mA

Output Current (All outputs)...............................20mA

ELECTRICAL SPECIFICATIONS

Unless otherwise indicated, V_CC= 2.7V to 5.5V (SP70xR), V_CC= 3.15V to 5.5V (SP70xS), V_CC= 3.0V to 5.5V (SP70xT), T_A=

T_MINto T_MAX, typical at 25°C.

Parameter

Min.

Typ.

Max.

Units

Conditions

Operating Voltage Range V_CC

Supply Current I_SUPPLY

5.5

40

V

1.0

25

µA

MR=V_CCor floating, WDI floating

SP706R. SP708R

SP706S. SP708S

SP706T. SP708T

Note 2

2.63

2.93

3.08

20

2.70

3.00

3.15

2.55

2.85

3.00

Reset Threshold

V

Reset Threshold Hysteresis

mV

ms

Reset Pulse Width t_RS

200

280

Note 2

140

RESET Output Voltage

0.8xV_CC

V_CC-1.5

V_RST(MAX)<V_CC<3.6V, I_SOURCE=500µA

V_OH

0.3

0.4

V

V_RST(MAX)<V_CC<3.6V, I_SINK=1.2mA

V_OL

4.5V<V_CC<5.5V, I_SOURCE=800µA

4.5V<V_CC<5.5V, I_SINK=3.2mA

V_OH

V_OL

RESET Output Voltage

V_CC-0.6

V_CC-1.5

V_RST(MAX)<V_CC<3.6V, I_SOURCE=215µA

V_OH

0.3

V_RST(MAX)<V_CC<3.6V, I_SOURCE=1.2mA

V_OL

4.5V<V_CC<5.5V, I_SOURCE=800µA

4.5V<V_CC<5.5V, I_SOURCE=3.2mA

V_CC<3.6V

V_OH

0.4

V_OL

Watchdog Timeout Period t_WD

1.60

0.02

2.25

s

1.00

50

WDI Pulse Width t_WP(note 1)

ns

V_IL=0.4V, V_IH=0.8xV_CC

WDI Input Threshold

0.6

0.8

1

V_RST(MAX)<V_CC<3.6V

V_CC=5V

V_IL

0.7xV_CC

V

µA

V

V_IH

V_IL

3.5

-1

V_CC=5V

V_IH

WDI Input Current

WDI=0V or WDI=V_CC

WDO Output Voltage

0.8xV_CC

V_CC-1.5

V_RST(MAX)<V_CC<3.6V, I_SOURCE=500µA

V_IL

V_IH

V_IL

V_IH

0.3

V_RST(MAX)<V_CC<3.6V, I_SINK=1.2mA

4.5V<V_CC<5.5V, I_SOURCE=800µA

4.5V<V_CC<5.5V, I_SINK=3.2mA

MR = 0V, V_RST(MAX)<V_CC<3.6V

MR = 0V, 4.5V<V_CC<5.5V

0.4

250

600

70

25

MR Pull-up Current

µA

250

100

2/16

Rev. 2.0.0

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

Parameter

MR Pulse Width t_MR

Min.

Typ.

Max.

Units

Conditions

V_RST(MAX)<V_CC<3.6V

4.5V<V_CC<5.5V

500

150

ns

MR Input Threshold

0.6

0.8

V_RST(MAX)<V_CC<3.6V

V_IL

V_IH

V_IL

V_IH

0.7xV_CC

2.0

V

V_RST(MAX)<V_CC<3.6V

4.5V<V_CC<5.5V

V_RST(MAX)<V_CC<3.6V

4.5V<V_CC<5.5V

750

250

MR to Reset Out Delay t_MD

ns

V_CC=3.0V - SP70xR, PFI falling

V_CC=3.3V - SP70xS/T, PFI falling

PFI Input Threshold

1.25

0.01

1.30

V

1.20

PFI Input Current

25.00

nA

-25.00

PFO Output Voltage

0.8xV_CC

V_CC-1.5

V_RST(MAX)<V_CC<3.6V, I_SOURCE=500µA

V_RST(MAX)<V_CC<3.6V, I_SINK=1.2mA

4.5V<V_CC<5.5V, I_SOURCE=800µA

4.5V<V_CC<5.5V, I_SINK=3.2mA

V_IL

V_IH

V_IL

V_IH

0.3

0.4

V

Note 1:WDI minimum rise /fall time is 1µs.

BLOCK DIAGRAM

Fig. 1: SP706R/S/T Block Diagram

3/16

Rev. 2.0.0

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

Fig. 2: SP708R/S/T Block Diagram

PIN ASSIGNMENT

Fig. 3: Pin Assignment

4/16

Rev. 2.0.0

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

PIN DESCRIPTION

Pin Number

Name

Description

SP706R/S/T

SP708R/S/T

SOIC MSOP

SOIC

MSOP

Manual Reset

This input triggers a reset pulse when pulled below 0.8V. This active

LOW input has an internal 70µA pull-up current. It can be driven

from a TTL or CMOS logic line or shorted to ground with a switch.

1

3

MR

3

2

3

Voltage Input

Ground reference for all signals

2

3

4

5

V_CC

GND

4

5

Power-Fail Input

4

5

When this voltage monitor input is less than 1.25V, PFO goes LOW.

Connect PFI to ground or V_CCwhen not in use.

Power-Fail Output

4

5

6

7

PFI

6

7

PFO

This output is LOW until PFI is less then 1.25V

Watchdog Input

If this input remains HIGH or LOW for 1.6s, the internal watchdog

timer times out and WDO goes LOW. Floating WDI or connecting WDI

to a high-impedance tri-state buffer disables the watchdog feature.

The internal watchdog timer clears whenever RESET is asserted, WDI

is tri-stated, or whenever WDI sees a rising or falling edge.

No Connect

Active-LOW RESET Output

This output pulses LOW for 200ms when triggered and stays LOW

whenever V^CCis below the reset threshold. It remains LOW for 200ms

after V^ccrises above the reset threshold or MR goes from LOW to

HIGH. A watchdog timeout will not trigger RESET unless WDO is

connected to MR.

6

-

WDI

N.C.

8

-

6

7

8

1

7

RESET

1

Watchdog Output

This output pulls LOW when the internal watchdog timer finishes its

1.6s count and does not go HIGH again until the watchdog is cleared.

WDO also goes LOW during low-line conditions. Whenever V_CCis

below the reset threshold, WDO stays LOW. However, unlike RESET,

WDO does not have a minimum pulse width. As soon as V_CCis above

the reset threshold, WDO goes HIGH with no delay.

8

-

WDO

2

-

Active-HIGH RESET Output

This output is the complement of RESET. Whenever RESET is HIGH,

RESET is LOW and vice-versa. Note that the SP708R/S/T has a reset

output only.

8

2

RESET

ORDERING INFORMATION

Temperature

Part Number

Packing

Quantity

Marking

Package

Note 1

Lead Free

Note 2

Range

SP706RC

YYWWL

X

Bulk

2.5K/Tape & Reel

Bulk

SP706RCN-L

8-pin NSOIC

8-pin MSOP

8-pin NSOIC

8-pin MSOP

8-pin NSOIC

8-pin MSOP

0°C≤T_A≤+70°C

-40°C≤T_A≤+85°C

0°C≤T_A≤+70°C

SP706RCN-L/TR

SP706RCU-L

Lead Free

706R

CXXX

YWW

2.5K/Tape & Reel

Bulk

SP706RCU-L/TR

SP706REN-L

SP706RE

YYWWL

X

2.5K/Tape & Reel

Bulk

SP706REN-L/TR

SP706REU-L

706R

EXXX

YWW

2.5K/Tape & Reel

Bulk

SP706REU-L/TR

SP706SCN-L

SP706SC

YYWWL

X

2.5K/Tape & Reel

Bulk

SP706SCN-L/TR

SP706SCU-L

706S

CXXX

YWW

2.5K/Tape & Reel

SP706SCU-L/TR

5/16

Rev. 2.0.0

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

Temperature

Range

Packing

Quantity

Part Number

Marking

Package

Note 1

Lead Free

Note 2

SP706SE

YYWWL

X

Bulk

2.5K/Tape & Reel

Bulk

SP706SEN-L

8-pin NSOIC

8-pin MSOP

8-pin NSOIC

8-pin MSOP

8-pin NSOIC

8-pin MSOP

-40°C≤T_A≤+85°C

0°C≤T_A≤+70°C

-40°C≤T_A≤+85°C

SP706SEN-L/TR

SP706SEU-L

Lead Free

706S

EXXX

YWW

2.5K/Tape & Reel

Bulk

SP706SEU-L/TR

SP706TCN-L

SP706TC

YYWWL

X

2.5K/Tape & Reel

Bulk

SP706TCN-L/TR

SP706TCU-L

706T

CXXX

YWW

2.5K/Tape & Reel

Bulk

SP706TCU-L/TR

SP706TEN-L

SP706TE

YYWWL

X

2.5K/Tape & Reel

Bulk

SP706TEN-L/TR

SP706TEU-L

706T

EXXX

YWW

2.5K/Tape & Reel

SP706TEU-L/TR

SP708RE

YYWWL

X

Bulk

2.5K/Tape & Reel

Bulk

SP708REN-L

8-pin NSOIC

8-pin MSOP

8-pin NSOIC

-40°C≤T_A≤+85°C

0°C≤T_A≤+70°C

-40°C≤T_A≤+85°C

0°C≤T_A≤+70°C

-40°C≤T_A≤+85°C

Lead Free

SP708REN-L/TR

SP708SCN-L

SP708SC

YYWWL

X

2.5K/Tape & Reel

Bulk

SP708SCN-L/TR

SP708SCU-L

708S

UXXX

YWW

2.5K/Tape & Reel

Bulk

SP708SCU-L/TR

SP708SEN-L

SP708SE

YYWWL

X

2.5K/Tape & Reel

Bulk

SP708SEN-L/TR

SP708TCN-L

SP708TC

YYWWL

X

2.5K/Tape & Reel

Bulk

SP708TCN-L/TR

SP708TEN-L

SP706TE

YYWWL

X

2.5K/Tape & Reel

SP708TEN-L/TR

“YY” = Year – “WW” = Work Week – “X” = Lot Number

6/16

Rev. 2.0.0

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

TYPICAL PERFORMANCE CHARACTERISTICS

All data taken at V_CC= 2.7V to 5.5V (SP70xR), V_CC= 3.15V to 5.5V (SP70xS), V_CC= 3.0V to 5.5V (SP70xT), T_A= 25°C,

unless otherwise indicated.

Fig. 5: Power-Fail Comparator

De-Assertion Response Time Circuit

Fig. 4: Power-Fail Comparator

De-Assertion Response Time

Fig. 7: Power-Fail Comparator

Assertion Response Time Circuit

Fig. 6: Power-Fail Comparator

Assertion Response Time

Fig. 9: SP706 RESET Output Voltage

Fig. 8: SP706 RESET Output Voltage

vs. Supply Voltage Circuit

vs. Supply Voltage

7/16

Rev. 2.0.0

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

Fig. 10: SP706 RESET Response Time

Fig. 11: SP706 RESET Response Time Circuit

Fig. 12: SP708 RESET and RESET Assertion

Fig. 13: SP708 RESET and RESET De-Assertion

Fig. 14: SP708 RESET and RESET Assertion and De-Assertion Circuit

8/16

Rev. 2.0.0

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

Fig. 15: SP708 RESET Output Voltage

vs. Supply Voltage

Fig. 16: SP708 RESET Response Time

Fig. 17: SP708 RESET Output Voltage vs. Supply Voltage

and SP813L RESET Response Time Circuit

9/16

Rev. 2.0.0

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

brownout condition occurs in the middle of a

previously initiated reset pulse, the pulse

continues for at least another 140ms. On

power down, once V_CCfalls below the reset

FEATURES

The SP706R/S/T and SP708R/S/T series

provides four key functions:

threshold,

RESET

stays

LOW

and

is

1. A reset output during power-up, power-

down and brownout conditions.

guaranteed to be 0.4V or less until V_CCdrops

below 1V.

2. An independent watchdog output that goes

LOW if the watchdog input has not been

toggled within 1.6 seconds.

The active-HIGH RESET output is simply the

complement of the RESET output and is

guaranteed to be valid with V^CCdown to 1.1V.

Some µPs, such as Intel's 80C51, require an

active-HIGH reset pulse.

3. A 1.25V threshold detector for power-fail

warning, low battery detection, or monitoring

a power supply other than +3.3V/+3.0V.

4. An active-LOW manual-reset that allows

RESET to be triggered by a pushbutton switch.

WATCHDOG TIMER

The SP706R/S/T-SP708R/S/T watchdog circuit

monitors the µP's activity. If the µP does not

toggle the watchdog input (WDI) within 1.6

seconds and WDI is not tri-stated, WDO goes

LOW. As long as RESET is asserted or the WDI

input is tri-stated, the watchdog timer will stay

cleared and will not count. As soon as RESET

is released and WDI is driven HIGH or LOW,

the timer will start counting. Pulses as short as

50ns can be detected.

The SP706R/S/T devices are the same as the

SP708R/S/T devices except for the active-

HIGH RESET substitution of the watchdog

timer.

THEORY OF OPERATION

The SP706R/S/T-SP708R/S/T series is

a

microprocessor (µP) supervisory circuit that

monitors the power supplied to digital circuits

such as microprocessors, microcontrollers, or

memory. The series is an ideal solution for

portable, battery-powered equipment that

Typically, WDO will be connected to the non-

maskable interrupt input (NMI) of a µP. When

V_CCdrops below the reset threshold, WDO will

go LOW whether or not the watchdog timer

had timed out. Normally this would trigger an

NMI but RESET goes LOW simultaneously and

thus overrides the NMI.

requires

power

supply

monitoring.

Implementing this series will reduce the

number of components and overall complexity.

The watchdog functions of this product family

will continuously oversee the operational

status of a system. The operational features

and benefits of the SP706R/S/T-SP708R/S/T

series are described in more detail below.

If WDI is left unconnected, WDO can be used

as a low-line output. Since floating WDI

disables the internal timer, WDO goes LOW

only when V_CCfalls below the reset threshold,

thus functioning as a low-line output.

RESET OUTPUT

A microprocessor's reset input starts the µP in

a known state. The SP706R/S/T-SP708R/S/T

series asserts reset during power-up and

prevents code execution errors during power

down or brownout conditions.

On power-up, once V_CCreaches 1V, RESET is a

guaranteed logic LOW of 0.4V or less. As V_CC

rises, RESET stays LOW. When V_CCrises above

the reset threshold, an internal timer releases

RESET after 200ms. RESET pulses LOW

whenever V_CCdips below the reset threshold,

such as in a brownout condition. When a

Fig. 18: Watchdog Timing Waveforms

Rev. 2.0.0

10/16

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

MANUAL RESET

The manual-reset input (MR) allows RESET to

be triggered by a pushbutton switch. The

switch is effectively debounced by the 140ms

minimum RESET pulse width. MR is TTL/CMOS

logic compatible, so it can be driven by an

external logic line. MR can be used to force a

watchdog timeout to generate a RESET pulse

in

the

SP706R/S/T-SP708R/S/T.

Simply

connect WDO to MR.

Ensuring a Valid Reset Output Down to

V_CC=0V

When V_CCfalls below 1V, the RESET output no

longer sinks current, it becomes an open

circuit. High-impedance CMOS logic inputs can

drift to undetermined voltages if left undriven.

If a pull-down resistor is added to the RESET

pin, any stray charge or leakage currents will

be shunted to ground, holding RESET LOW.

The resistor value is not critical. It should be

about 100KΩ, large enough not to load RESET

and small enough to pull RESET to ground.

Fig. 19: Timing Diagrams with WDI tri-stated.

P

OWER-FAIL COMPARATOR

The power-fail comparator can be used for

various purposes because its output and non

inverting input are not internally connected.

The inverting input is internally connected to a

1.25V reference.

To build an early-warning circuit for power

failure, connect the PFI pin to a voltage divider

as shown in Figure 20. Choose the voltage

divider ratio so that the voltage at PFI falls

below 1.25V just before the +5V regulator

drops out. Use PFO to interrupt the µP so it

can prepare for an orderly power-down.

M

ONITORING

VOLTAGES OTHER THAN THE

U

NREGULATED DC INPUT

Monitor voltages other than the unregulated

DC by connecting a voltage divider to PFI and

adjusting the ratio appropriately. If required,

add hysteresis by connecting a resistor (with a

value approximately 10 times the sum of the

two resistors in the potential divider network)

between PFI and PFO. A capacitor between PFI

and GND will reduce the power-fail circuit's

sensitivity to high-frequency noise on the line

being monitored. RESET can be used to

monitor voltages other than the +3.3V/+3.0V

V_CCline. Connect PFO to MR to initiate a

RESET pulse when PFI drops below 1.25V.

Figure 21 shows the SP706R/S/T-SP708R/S/T

series configured to assert RESET when the

+3.3V/3.0V supply falls below the RESET

threshold, or when the +12V supply falls

below approximately 11V.

MONITORING A NEGATIVE VOLTAGE SUPPLY

The power-fail comparator can also monitor a

negative supply rail, shown in Figure 22. When

the negative rail is good (a negative voltage of

large magnitude), PFO is LOW. By adding the

Fig. 20: Typical Operating Circuit

11/16

Rev. 2.0.0

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

resistors and transistor as shown, a HIGH PFO

triggers RESET. As long as PFO remains HIGH,

the SP706R/S/T-SP708R/S/T series will keep

RESET asserted (where RESET = LOW and

RESET = HIGH). Note that this circuit's

accuracy depends on the PFI threshold

tolerance, the V_CCline, and the resistors.

I

NTERFACING TO µPS WITH BIDIRECTIONAL

RESET PINS

µPs with bidirectional RESET pins, such as the

Motorola 68HC11 series, can contend with the

SP705/706/707/708 RESET output. If, for

example, the RESET output is driven HIGH and

the µP wants to pull it LOW, indeterminate

logic levels may result. To correct this,

connect a 4.7KΩ resistor between the RESET

output and the µP reset I/O, as shown if

Figure 23. Buffer the RESET output to other

system components.

Fig. 21: Monitoring +3.3V/+3.0V and +12V Power

Supplies

Fig. 23: Interfacing to Microprocessors

with Bidirectional RESET I/O (SP706)

N

EGATIVE-GOING V_CCTRANSIENT

While issuing resets to the μP during power-

up, power-down, and brownout conditions,

these supervisors are relatively immune to

short duration negative-going VCC transients

(glitches). It is usually undesirable to reset the

μP when V_CCexperiences only small glitches.

Figure 24 shows maximum transient duration

vs. reset-comparator overdrive, for which

reset pulses are not generated. The data was

generated using negative-going V_CCpulses,

starting at 3.3V and ending below the reset

threshold by the magnitude indicated (reset

comparator overdrive). The graph shows the

maximum pulse width a negative-going V_CC

transient may typically have without causing a

reset pulse to be issued. As the amplitude of

the transient increases (i.e. goes farther below

Fig. 22: Monitoring a Negative Voltage Supply

12/16

Rev. 2.0.0

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

the reset threshold), the maximum allowable

pulse width decreases. Typically, a V_CC

transient that goes 100mV below the reset

threshold and lasts for 40μs or less will not

cause a reset pulse to be issued. A 100nF

bypass capacitor mounted close to the VCC pin

provides additional transient immunity.

Fig. 25: Supply Current vs. Temperature

Fig. 24: Maximum Transient Duration without Causing a

Reset Pulse vs. Reset Comparator Overdrive

APPLICATIONS

The SP706P/R/S/T-SP708R/S/T series offers

unmatched performance and the lowest power

consumption for these industry standard

devices. Refer to Figures 25 and 26 for supply

current performance characteristics rated

against temperature and supply voltages.

Fig. 26: Supply Current vs. Supply Voltage

13/16

Rev. 2.0.0

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

PACKAGE SPECIFICATION

8-PIN NSOIC

14/16

Rev. 2.0.0

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

8-PIN MSOP

15/16

Rev. 2.0.0

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

REVISION HISTORY

Revision

Date

Description

06/04/2010

Reformat of datasheet

2.0.0

FOR FURTHER ASSISTANCE

Email:

customersupport@exar.com

Exar Technical Documentation:

http://www.exar.com/TechDoc/default.aspx?

E

XAR

CORPORATION

H

EADQUARTERS AND

SALES OFFICES

48720 Kato Road

Fremont, CA 94538 – USA

Tel.: +1 (510) 668-7000

Fax: +1 (510) 668-7030

www.exar.com

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve

design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein,

conveys no license under any patent or other right, and makes no representation that the circuits are free of patent

infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a

user’s specific application. While the information in this publication has been carefully checked; no responsibility, however,

is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or

malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its

safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in

writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all

such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

16/16

Rev. 2.0.0


型号：	SP708TEN-L
厂家：	EXAR CORPORATION
描述：	Power Supply Support Circuit, Fixed, 1 Channel, +3.08VV, PDSO8, LEAD FREE, PLASTIC, SOIC-8 输入元件光电二极管
文件：	总16页 (文件大小：844K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP708TEN-L [EXAR]

相关型号：

SP708TEN-L/TR

SP708TEP

SP708TEP-L

SP708TEU

SP708TEU

SP708TEU-L

SP708TEU-L

SP708TEU-L/TR

SP708TEU/TR

SP7101

SP7102

SP7103