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MP7543JN [EXAR]

5 V CMOS Serial Input 12-Bit Digital-to-Analog Converter; 5 V CMOS串行输入12位数字 - 模拟转换器
MP7543JN
型号： MP7543JN
厂家： EXAR CORPORATION    EXAR CORPORATION
描述：

5 V CMOS Serial Input 12-Bit Digital-to-Analog Converter
5 V CMOS串行输入12位数字 - 模拟转换器

转换器
文件： 总12页 (文件大小：131K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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MP7543  
5 V CMOS  
Serial Input 12-Bit  
Digital-to-Analog Converter  
FEATURES  
BENEFITS  
• 12-Bit DAC with Serial Digital Input Interface  
• Nonlinearity +1/2 LSB from Tmin to Tmax  
• Compatible with Serial Addressing Systems  
• Lowest Sensitivity to Amplifier V  
• Low Output Capacitance  
• Full 4-Quadrant Multiplication  
• Latch-Up Free  
OS  
• Asynchronous CLEAR Input  
• Serial Load On Positive or Negative Strobes  
• +5 V Supply Operation  
• 3 V Version: MP75L43  
• 4-Bit Parallel Version: MP7542  
GENERAL DESCRIPTION  
The MP7543 is a precision, 12-bit CMOS 4-quadrant multi-  
plying Digital-to-Analog Converter designed for serial interface  
applications.  
under control of the Load inputs.  
A CLEAR input is provided for the asynchronous resetting of  
register B to all 0’s.  
The MP7543 is manufactured using an advanced thin film  
monolithic CMOS fabrication process. A unique decoding tech-  
nique is utilized yielding excellent accuracy and stability. 12-bit  
linearity is achieved without laser trimming.  
TheMP7543consistsoftwo12-bitregisters, controllogicand  
a 12-bit multiplying D/A converter. The input register (register A)  
is a 12-bit serial-in parallel-out shift register. Serial data at the  
SR1 pin is clocked into Register A on the leading or trailing edge  
(user selected) of the strobe input, with the MSB loaded first.  
Register B is a 12-bit parallel-in parallel-out register that follows  
register A. The contents of register A are loaded into register B  
The MP7543 reduces the additional linearity errors due to  
output amplifier offset to only 330 µV per millivolt of offset - half  
the value of a standard R-2R CMOS DAC design approach.  
SIMPLIFIED BLOCK DIAGRAM  
R
FB  
I
I
OUT1  
12-Bit D/A Converter  
V
REF  
OUT2  
AGND  
CLR  
DAC Register B  
Load  
LD1  
LD2  
Register A  
12-Bit Shift Register  
STB1  
SRI  
STB4  
STB3  
STB2  
V
DD  
DGND  
Rev. 2.00  
1
MP7543  
ORDERING INFORMATION  
Package  
Type  
Temperature  
INL  
(LSB)  
DNL  
(LSB)  
Gain Error  
(LSB)  
Part No.  
Range  
–40 to +85°C  
–40 to +85°C  
–40 to +85°C  
–40 to +85°C  
–40 to +85°C  
–40 to +85°C  
–40 to +85°C  
–40 to +85°C  
–55 to +125°C  
–55 to +125°C  
Plastic Dip  
Plastic Dip  
SOIC  
MP7543JN  
MP7543KN  
MP7543JS  
MP7543KS  
MP7543JP  
MP7543KP  
MP7543AD  
MP7543BD  
MP7543SD*  
MP7543TD*  
+1  
+1/2  
+1  
+2  
+1  
+2  
+1  
+2  
+1  
+2  
+1  
+2  
+1  
+14.5  
+14.5  
+14.5  
+14.5  
+14.5  
+14.5  
+14.5  
+14.5  
+14.5  
+14.5  
SOIC  
+1/2  
+1  
PLCC  
PLCC  
+1/2  
+1  
Ceramic Dip  
Ceramic Dip  
Ceramic Dip  
Ceramic Dip  
+1/2  
+1  
+1/2  
*Contact factory for non-compliant military processing  
PIN CONFIGURATIONS  
See Packaging Section for  
Package Dimensions  
I
R
FB  
OUT1  
N/C  
I
V
REF  
OUT2  
3
2
1
20  
19  
1
1
2
3
4
5
6
7
8
16  
15  
14  
16  
I
I
R
V
V
OUT1  
FB  
4
18  
17  
AGND  
V
2
3
4
5
15  
14  
13  
12  
DD  
OUT2  
REF  
DD  
AGND  
STB1  
LD1  
5
STB1  
See  
Pin Out  
at Left  
CLR  
N/C  
13 CLR  
12  
DGND  
6
7
8
16  
N/C  
LD1  
N/C  
11  
10  
9
N/C  
SRI  
STB4  
STB3  
LD2  
6
7
8
11  
10  
9
15 DGND  
14 STB4  
STB2  
9
10  
11  
12  
13  
SRI  
N/C  
STB3  
STB2  
LD2  
16 Pin CDIP, PDIP (0.300”)  
D16, N16  
16 Pin SOIC (Jedec, 0.300”)  
S16  
20 Pin PLCC  
P20  
Rev. 2.00  
2
MP7543  
PIN OUT DEFINITIONS  
PDIP, CDIP and SOIC  
PLCC  
PIN NO.  
NAME  
DESCRIPTION  
PIN NO.  
NAME  
N/C  
DESCRIPTION  
No Connection.  
1
I
I
DAC current output pin. Normally  
terminated at op amp virtual ground.  
1
2
OUT1  
I
DAC current output pin. Normally  
terminated at op amp virtual ground.  
OUT1  
2
DAC current output pin. Normally  
terminated at AGND.  
OUT2  
3
I
DAC current output pin. Normally  
terminated at AGND.  
OUT2  
3
4
5
AGND  
STB1  
LD1  
Analog Ground.  
Register A Strobe 1 input, See Table 1.  
4
5
6
7
AGND  
STB1  
N/C  
Analog Ground.  
DAC Register B Load 1 input. When  
LD1 and LD2 go low the contents of  
Register A are loaded into DAC  
Register B.  
Register A Strobe 1 input, See Table 1.  
No Connection.  
LD1  
DAC Register B Load 1 input. When  
LD1 and LD2 go low the contents of  
Register A are loaded into DAC  
Register B.  
6
7
8
9
N/C  
No Connection.  
SRI  
Serial Data Input to Register A.  
Register A Strobe 2 input, See Table 1.  
STB2  
LD2  
8
N/C  
No Connection.  
DAC Register B Load 2 input. When  
LD1 and LD2 go low the contents of  
Register A are loaded into DAC  
Register B.  
9
SR1  
STB2  
N/C  
Serial Data Input to Register A.  
Register A Strobe 2 input, See Table 1.  
No Connection.  
10  
11  
12  
10  
11  
12  
13  
STB3  
STB4  
DGND  
CLR  
Register A Strobe 3 input, See Table 1.  
Register A Strobe 4 input, See Table 1.  
Digital Ground.  
LD2  
DAC Register B Load 2 input. When  
LD1 and LD2 go low the contents of  
Register A are loaded into DAC  
Register B.  
Register B CLEAR input (active  
LOW), can be used to asynchronously  
reset Register B to 0000 0000 0000.  
13  
14  
15  
16  
17  
STB3  
STB4  
DGND  
N/C  
Register A Strobe 3 input, See Table 1.  
Register A Strobe 4 input, See Table 1.  
Digital Ground.  
14  
15  
V
V
+5 V Supply Input.  
DD  
No Connection.  
Reference input. Can be positive or  
negative DC voltage or AC signal.  
REF  
CLR  
Register B CLEAR input (active  
LOW), can be used to asynchronously  
reset Register B to 0000 0000 0000.  
16  
R
DAC Feedback Resistor.  
FB  
18  
19  
V
V
+5 V Supply Input.  
DD  
Reference input. Can be positive or  
negative DC voltage or AC signal.  
REF  
20  
R
DAC Feedback Resistor.  
FB  
Rev. 2.00  
3
MP7543  
ELECTRICAL CHARACTERISTICS  
(V = + 5 V, V  
= +10 V unless otherwise noted)  
DD  
REF  
25°C  
Typ  
Tmin to Tmax  
Min Max  
Parameter  
Symbol  
Min  
Max  
Units  
Test Conditions/Comments  
1
STATIC PERFORMANCE  
Resolution (All Grades)  
N
12  
12  
Bits  
Integral Non-Linearity  
(Relative Accuracy)  
J, A, S  
INL  
LSB  
Best Fit Straight Line Spec.  
(Max INL – Min INL) / 2  
+1  
+1  
K, B, T  
+1/2  
+1/2  
Differential Non-Linearity  
DNL  
GE  
LSB  
LSB  
Monotonicity:  
11 Bits Guaranteed  
12 Bits Guaranteed  
J, A, S  
K, B, T  
+2  
+1  
+2  
+1  
Gain Error  
Using Internal R  
FB  
J, A, K, B, S, T  
+12.3  
+50  
+14.5  
2
Gain Temperature Coefficient  
TC  
+2 ppm/°C  
∆Gain/∆Temperature  
|∆Gain/∆V | ∆V = + 5%  
GE  
Power Supply Rejection Ratio  
PSRR  
+100 ppm/%  
DD  
DD  
Output Leakage Current  
I
nA  
+10  
+200  
OUT  
J, K, A, B  
S, T  
+10  
+10  
DYNAMIC PERFORMANCE  
2
Current Output Settling Time  
t
S
2
2
µs  
R =100Ω, C =13pF  
L L  
Full Scale Output Settles to  
1/2 LSB of Final Value  
2
AC Feedthrough at I  
F
T
2.5  
2.5 mV p-p  
V
REF  
= 10kHz, 20 Vp-p, sinewave  
OUT1  
REFERENCE INPUT  
Input Resistance  
R
V
V
IL  
LKG  
5
10  
20  
5
20 kΩ  
IN  
3
DIGITAL INPUTS  
Logical “1” Voltage  
Logical “0” Voltage  
Input Leakage Current  
3.0  
3.0  
V
IH  
0.8  
+1  
0.8  
V
I
+1 µA  
2
ANALOG OUTPUTS  
Output Capacitance  
C
C
C
C
260  
100  
50  
260 pF  
100 pF  
50 pF  
DAC Inputs all 1’s  
DAC Inputs all 0’s  
DAC Inputs all 1’s  
DAC Inputs all 0’s  
OUT1  
OUT1  
OUT2  
OUT2  
210  
210 pF  
POWER SUPPLY  
Supply Voltage  
Supply Current  
V
I
4.75  
5.25  
2.5  
4.75  
5.25  
V
V
= +5 V +5% for specified  
DD  
DD  
performance  
All digital inputs = 0 V or all = 5 V  
2.5 mA  
DD  
Rev. 2.00  
4
MP7543  
ELECTRICAL CHARACTERISTICS (CONT’D)  
25°C  
Typ  
Tmin to Tmax  
Min Max  
Parameter  
Symbol  
Min  
Max  
Units  
Test Conditions/Comments  
SWITCHING  
CHARACTERISTICS  
2, 4  
Serial Input to Strobe Set-up Time  
Serial Input to Strobe Set-up Time  
Serial Input to Strobe Set-up Time  
Serial Input to Strobe Set-up Time  
Serial Input to Strobe Hold Time  
Serial Input to Strobe Hold Time  
Serial Input to Strobe Hold Time  
Serial Input to Strobe Hold Time  
SRI Data Pulse Width  
STB1 Pulse Width  
STB4 Pulse Width  
STB3 Pulse Width  
STB2 Pulse Width  
t
50  
0
0
100  
0
0
40  
60  
160  
160  
120  
160  
160  
200  
200  
160  
300  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
STB1 used as a strobe  
STB4 used as a strobe  
STB3 used as a strobe  
STB2 used as a strobe  
STB1 used as a strobe  
STB4 used as a strobe  
STB3 used as a strobe  
STB2 used as a strobe  
DS1  
t
t
t
t
t
t
t
DS4  
DS3  
DS2  
DH1  
DH4  
DH3  
DH2  
20  
30  
80  
80  
60  
80  
80  
100  
100  
80  
150  
0
t
SRI  
t
t
t
t
STB1  
STB4  
STB3  
STB2  
Load Pulse Width  
t
LD1, 2  
Minimum time between strobing  
Reg. A and loading Reg. B  
CLR pulse width  
t
ASB  
t
200  
400  
ns  
CLR  
NOTES:  
1
Full Scale Range (FSR) is 10V for unipolar mode.  
Guaranteed but not production tested.  
Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.  
See timing diagram.  
2
3
4
Specificationsare subject to change without notice  
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3  
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V  
Digital Input Voltage to GND (2) . GND –0.5 to VDD +0.5 V  
IOUT1, IOUT2 to GND . . . . . . . . . . . GND –0.5 to VDD +0.5 V  
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C  
Lead Temperature (Soldering, 10 seconds) . . . . . . +300°C  
V
V
REF to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V  
RFB to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V  
Package Power Dissipation Rating to 75°C  
CDIP, PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . . 700mW  
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V  
(Functionality Guaranteed +0.5 V)  
Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 10mW/°C  
NOTES:  
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a  
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating  
conditions for extended periods may affect device reliability.  
2
3
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps  
(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short  
transients outside the supplies of less than 100mA for less than 100µs.  
GND refers to AGND and DGND.  
Rev. 2.00  
5
MP7543  
TIMING DIAGRAM  
t
SRI  
Bit 1  
MSB  
Bit 12  
LSB  
SR1  
Bit 2  
Bit 11  
11  
t
, t  
, t  
t
, t  
, t  
DS1 DS2 DS4  
DH1 DH2 DH4  
1
2
12  
Strobe Input  
(STB1, STB2, STB4  
(Note)  
t
t
t
STB1  
STB2  
STB4  
LOADING REGISTER A  
t
ASB  
t
t
LD1  
LD2  
LD1 AND LD2  
Note:  
Strobe Waveform is Inverted if  
STB3 is Used to Strobe Serial Data Bits  
into Register A  
Loading Register B  
with Contents of Register A  
MP7543 Logic Inputs  
Register A Control Inputs  
Register B Control Inputs  
MP7543 Operation  
Notes  
STB4 STB3 STB2 STB1  
CLR  
LD2  
LD1  
0
0
0
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
Data appearing at SRI strobed into Register A  
Data appearing at SRI strobed into Register A  
Data appearing at SRI strobed into Register A  
Data appearing at SRI strobed into Register A  
2, 3  
2, 3  
2, 3  
2, 3  
0
0
0
0
1
X
0
0
1
X
X
X
X
X
1
X
X
X
1
No Operation (Register A)  
3
X
X
X
0
1
1
1
X
1
X
0
X
X
1
0
Clear Register B to code 0000 0000 0000 (Asynchronous)  
No Operation (Register B)  
1, 3  
3
Load Register B with the contents of Register A  
3
NOTES  
1. CLR = 0 Asynchronously resets Register B to 0000 0000 0000, but has no effect on Register A.  
2. Serial data is loaded into Register A MSB first, on edges shown  
3. 0 = Logic LOW, 1 = Logic HIGH, X = Don’t Care.  
is positive edge,  
is negative edge.  
Table 1. Truth Table  
Rev. 2.00  
6
MP7543  
APPLICATION NOTES  
Refer to Section 8 for Applications Information  
(8)  
ADDRESS BUS (16)  
ADDRESS BUS (16)  
A0-15  
ADDRESS (16)  
ADDRESS (16)  
A0-15  
8085  
ALE  
6800  
R/W  
E1  
E1  
8212  
φ2  
DECODER  
DECODER  
8205  
8205  
E3  
E2  
E3  
E2  
+5 V  
WR  
D0  
D7  
DATA BUS (8)  
DATA (8)  
DATA (8)  
(8) AD0-7  
DATA  
SOD  
SR1 LD2 STB2  
STB3  
SR1 LD2 STB1  
STB3  
+5 V  
+5 V  
MP7543  
MP7543  
STB1  
STB4  
STB2  
STB4  
LD1  
LD1  
CLR  
CLR  
FROM SYSTEM RESET  
FROM SYSTEM RESET  
Figure 1. MP7543 8085 Interface  
Figure 2. MP7543 MC6800 Interface  
Digital Input  
V
IN  
R
FB  
I
V
REF  
OUT1  
MP7543  
I
OUT2  
–
+
V
OUT  
Figure 3. Digitally Programmable  
Gain Amplifier  
Graph 1. Relative Accuracy vs. Digital Code  
Rev. 2.00  
7
MP7543  
16 LEAD PLASTIC DUAL-IN-LINE  
(300 MIL PDIP)  
N16  
S
9
8
16  
1
E
1
Q
B
E
1
D
A
1
A
L
Seating  
Plane  
B
e
1
C
α
INCHES  
MILLIMETERS  
SYMBOL  
MIN  
MAX  
MIN  
MAX  
A
––  
0.015  
0.014  
0.038  
0.008  
0.745  
0.295  
0.220  
0.200  
––  
––  
0.38  
5.08  
––  
A
B
1
0.023  
0.065  
0.015  
0.785  
0.325  
0.310  
0.356  
0.965  
0.203  
18.92  
7.49  
0.584  
1.65  
0.381  
19.94  
8.26  
7.87  
B (1)  
1
C
D
E
E
e
L
5.59  
1
0.100 BSC  
2.54 BSC  
0.115  
0.150  
2.92  
3.81  
α
0°  
0.055  
0.020  
15°  
0.070  
0.080  
0°  
1.40  
0.51  
15°  
1.78  
2.03  
Q
S
1
Note: (1) The minimum limit for dimensions B1 may be 0.023”  
(0.58 mm) for all four corner leads only.  
Rev. 2.00  
8
MP7543  
16 LEAD CERAMIC DUAL-IN-LINE  
(300 MIL CDIP)  
D16  
S1  
S
See  
Note 1  
16  
9
8
1
E
1
E
D
Q
Base  
Plane  
A
Seating  
Plane  
L
e
c
L
1
b
b
1
α
NOTES  
INCHES  
MILLIMETERS  
1. Index area; a notch or a lead one identification mark  
is located adjacent to lead one and is within the  
shaded area shown.  
SYMBOL  
MIN  
MAX  
MIN  
MAX  
NOTES  
A
––  
0.014  
0.038  
0.008  
––  
0.200  
0.023  
0.065  
0.015  
0.840  
0.310  
0.320  
––  
0.356  
0.965  
0.203  
––  
5.08  
0.584  
1.65  
––  
––  
2
2. The minimum limit for dimension b may be 0.023  
1
b
(0.58 mm) for all four corner leads only.  
3. Dimension Q shall be measured from the seating  
plane to the base plane.  
b1  
c
0.381  
21.34  
7.87  
––  
4
4. This dimension allows for off-center lid, meniscus and  
glass overrun.  
D
E
5. The basic lead spacing is 0.100 inch (2.54 mm) be-  
tween centerlines.  
0.220  
0.290  
5.59  
4
E1  
e
7.37  
8.13  
7
6. Applies to all four corners.  
7. This is measured to outside of lead, not center.  
0.100 BSC  
2.54 BSC  
5
L
0.125  
0.200  
––  
3.18  
3.81  
0.381  
––  
5.08  
––  
––  
––  
3
L1  
Q
S
0.150  
0.015  
––  
0.060  
0.080  
––  
1.52  
2.03  
––  
6
S1  
0.005  
0.13  
6
α
0°  
15°  
0°  
15°  
––  
Rev. 2.00  
9
MP7543  
16 LEAD SMALL OUTLINE  
(300 MIL JEDEC SOIC)  
S16  
D
16  
9
E
H
8
h x 45°  
C
A
Seating  
Plane  
α
e
B
A
1
L
INCHES  
MILLIMETERS  
SYMBOL  
MIN  
MAX  
MIN  
MAX  
A
0.097  
0.104  
0.0115  
0.019  
2.46  
0.127  
0.356  
0.231  
10.21  
7.42  
2.64  
0.292  
0.482  
0.318  
10.46  
7.59  
A
B
0.0050  
0.014  
1
C
D
E
e
0.0091 0.0125  
0.402  
0.292  
0.412  
0.299  
0.050 BSC  
1.27 BSC  
H
h
0.400  
0.410  
0.016  
0.035  
10.16  
0.254  
0.406  
10.41  
0.406  
0.889  
0.010  
0.016  
L
α
0°  
8°  
0°  
8°  
Rev. 2.00  
10  
MP7543  
20 LEAD PLASTIC LEADED CHIP CARRIER  
(PLCC)  
P20  
D
D
Seating  
Plane  
1
A
2
1
B
D
D
1
D
2
e
1
C
D
3
A
1
A
INCHES  
MILLIMETERS  
SYMBOL  
MIN  
MAX  
MIN  
MAX  
A
0.165  
0.100  
0.148  
0.013  
0.008  
0.385  
0.350  
0.290  
0.180  
0.110  
0.156  
0.021  
0.012  
0.395  
0.354  
0.330  
4.19  
2.54  
4.57  
2.79  
A
1
A
2
B
3.76  
3.96  
0.330  
0.203  
9.78  
0.533  
0.305  
10.03  
8.99  
C
D
D (1)  
8.89  
1
D
D
7.37  
8.38  
2
3
0.200 Ref  
0.050 BSC  
5.08 Ref.  
1.27 BSC  
e
1
Note: (1) Dimension D does not include mold protrusion.  
1
Allowed mold protrusion is 0.254 mm/0.010 in.  
Rev. 2.00  
11  
MP7543  
NOTICE  
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-  
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-  
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are  
free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary  
depending upon a user’s specific application. While the information in this publication has been carefully checked;  
no responsibility, however, is assumed for inaccuracies.  
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or  
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly  
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation  
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the  
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-  
stances.  
Copyright EXAR Corporation  
Datasheet April 1995  
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.  
Rev. 2.00  
12  

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