MR4A16BCYS35 [EVERSPIN]
1M x 16 MRAM;型号: | MR4A16BCYS35 |
厂家: | Everspin Technologies |
描述: | 1M x 16 MRAM 静态存储器 光电二极管 内存集成电路 |
文件: | 总16页 (文件大小:909K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MR4A16B
1M x 16 MRAM
FEATURES
• +3.3 Volt power supply
• Fast 35 ns read/write cycle
• SRAM compatible timing
• Unlimited read & write endurance
• Data always non-volatile for >20 years at temperature
• RoHS-compliant small footprint BGA and TSOP2 package
• All products meet MSL-3 moisture sensitivity level
BENEFITS
• One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems
for simpler, more efficient designs
• Improves reliability by replacing battery-backed SRAM
INTRODUCTION
The MR4A16B is a 16,777,216-bit magnetoresistive random access memory
(MRAM) device organized as 1,048,576 words of 16 bits. The MR4A16B offers
SRAM compatible 35 ns read/write timing with unlimited endurance. Data
is always non-volatile for greater than 20 years. Data is automatically pro-
RoHS
tected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. To
simplify fault tolerant design, the MR4A16B includes internal single bit error correction code with 7 ECC
parity bits for every 64 data bits. The MR4A16B is the ideal memory solution for applications that must
permanently store and retrieve critical data and programs quickly.
The MR4A16B is available in a small footprint 48-pin ball grid array (BGA) package and a 54-pin thin small
outline package (TSOP Type 2). These packages are compatible with similar low-power SRAM products and
other nonvolatile RAM products.
The MR4A16B provides highly reliable data storage over a wide range of temperatures. The product is
offered with commercial temperature (0 to +70 °C), and industrial temperature (-40 to +85 °C) operating
temperature options.
CONTENTS
1. DEVICE PIN ASSIGNMENT.........................................................................
2. ELECTRICAL SPECIFICATIONS.................................................................
3. TIMING SPECIFICATIONS..........................................................................
4. ORDERING INFORMATION.......................................................................
5. MECHANICAL DRAWING..........................................................................
6. REVISION HISTORY......................................................................................
How to Reach Us...................................................................................... ..........
3
4
7
12
13
15
16
Copyright © 2018 Everspin Technologies, Inc.
1
MR4A16B Rev. 11.7 3/2018
MR4A16B
1. DEVICE PIN ASSIGNMENT
Figure 1.1 Block Diagram
OUTPUT
ENABLE
BUFFER
UPPER BYTE OUTPUT ENABLE
LOWER BYTE OUTPUT ENABLE
G
10
UPPER
BYTE
OUTPUT
BUFFER
A[19:0] ADDRESS
8
8
ROW
DECODER
10
BUFFER
COLUMN
DECODER
20
8
8
SENSE
AMPS
CHIP
ENABLE
BUFFER
E
LOWER
BYTE
OUTPUT
BUFFER
16
1M x 16
BIT
MEMORY
ARRAY
UPPER
BYTE
WRITE
DRIVER
8
WRITE
ENABLE
BUFFER
DQU[15:8]
W
8
8
FINAL
WRITE
DRIVERS
16
LOWER
BYTE
8
DQL[7:0]
WRITE
DRIVER
UB
LB
UB
LB
UPPER BYTE WRITE ENABLE
LOWER BYTE WRITE ENABLE
BYTE
ENABLE
BUFFER
Table 1.1 Pin Functions
Signal Name
Function
A
Address Input
Chip Enable
Write Enable
Output Enable
E
W
G
UB
Upper Byte Enable
Lower Byte Enable
Data I/O
LB
DQ
VDD
VSS
Power Supply
Ground
DC
NC
Do Not Connect
No Connection
Copyright © 2018 Everspin Technologies, Inc.
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MR4A16B Rev. 11.7 3/2018
DEVICE PIN ASSIGNMENT
MR4A16B
Figure 1.1 Pin Diagrams for Available Packages (Top View)
1
2
3
4
5
6
54
53
52
51
1
2
3
4
NC
Aꢀꢁ
NC
Aꢀꢈ
LB
G
A0
A1
A2
NC
A
B
C
D
E
Aꢂ
Aꢀ
Aꢃ
Aꢄ
Aꢉ
Aꢀꢇ
Aꢀꢆ
Aꢀꢅ
G
UB
LB
DQꢀꢅ
DQꢀꢉ
DQꢀꢄ
DQꢀꢃ
DQU8
DQU9
DQL0
DQL2
UB
A3
A5
A4
A6
E
50
49
48
5
6
7
DQU10
DQU11
DQU12
DQU13
NC
DQL1
DQL3
47
46
E
8
9
DQꢂ
DQꢀ
DQꢃ
DQꢄ
VSS
VDD
A7
A17
DC
45
44
43
42
41
10
11
12
13
14
VDD
A16
A15
A13
A10
DQL4
DQL5
VSS
VDD
V
V
SS
V
SS
DD
F
DQU14
DQU15
DQL6
DQL7
A14
A12
A9
DQꢉ
DQꢅ
DQꢆ
DQꢇ
W
DQꢀꢀ
DQꢀꢂ
DQꢁ
DQꢈ
DC
40
39
15
16
38
37
36
35
34
33
32
17
18
19
20
21
22
23
G
H
W
A
18
A8
A11
A19
Aꢅ
Aꢀꢉ
Aꢆ
Aꢇ
Aꢈ
Aꢀꢄ
Aꢀꢃ
Aꢀꢀ
Aꢀꢂ
NC
NC
NC
Aꢁ
31
30
24
25
NC
NC
NC
29
28
26
27
48-Pin BGA
54-Pin TSOP2
Table 1.2 Operating Modes
E1
H
L
G1 W1 LB1 UB1
Mode
Not selected
VDD Current
DQL[7:0]2 DQU[15:8]2
X
H
X
L
X
H
X
H
H
H
L
X
X
H
L
X
X
H
H
L
ISB1, ISB2
Hi-Z
Hi-Z
Hi-Z
DOut
Hi-Z
DOut
Din
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DOut
DOut
Hi-Z
Din
Output disabled
Output disabled
Lower Byte Read
Upper Byte Read
Word Read
IDDR
L
IDDR
L
IDDR
L
L
H
L
IDDR
L
L
L
IDDR
L
X
X
X
L
H
L
Lower Byte Write
Upper Byte Write
Word Write
IDDW
IDDW
IDDW
L
L
H
L
Hi-Z
Din
L
L
L
Din
1
2
H = high, L = low, X = don’t care
Hi-Z = high impedance
Copyright © 2018 Everspin Technologies, Inc.
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MR4A16B Rev. 11.7 3/2018
MR4A16B
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or
electric fields; however, it is advised that normal precautions be taken to avoid application of any
voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken
to avoid application of any magnetic field greater than the maximum field intensity specified
in the maximum ratings.
Table 2.1 Absolute Maximum Ratings 1
Symbol
VDD
Parameter
Conditions
Value
Unit
V
Supply voltage2
Voltage on an pin 2
Output current per pin
-0.5 to 4.0
-0.5 to VDD + 0.5
VIN
V
IOUT
20
mA
PD
Package power dissipation 3
Temperature under bias
Storage Temperature
0.600
W
Commercial
Industrial
-10 to 85
-45 to 95
-55 to 150
°C
°C
°C
TBIAS
Tstg
Lead temperature during solder (3
minute max)
TLead
260
°C
Hmax_write
Hmax_read
Maximum magnetic field
Maximum magnetic field
During Write
8000
A/m
During Read or Standby
1
2
3
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation
should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic
fields could affect device reliability.
All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more than
0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited to less than
20mA.
Power dissipation capability depends on package characteristics and use environment.
Copyright © 2018 Everspin Technologies, Inc.
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MR4A16B Rev. 11.7 3/2018
Electrical Specifications
MR4A16B
Table 2.2 Operating Conditions
Symbol
Parameter
Temp Range
Min
3.0 1
Typical
Max
3.6
3.01
Unit
V
VDD
Power supply voltage
Write inhibit voltage
Input high voltage
Input low voltage
3.3
VWI
VIH
VIL
2.5
2.7
V
VDD + 0.3 2
2.2
-0.5 3
-
-
-
V
0.8
70
85
V
Commercial
Industrial
0
°C
TA
Temperature under bias
-40
-
°C
1
2
3
There is a 2 ms startup time once VDD exceeds VDD,(min). See Power Up and Power Down Sequencing below.
VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
Power Up and Power Down Sequencing
The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min),
there is a startup time of 2 ms before read or write operations can start. This time allows memory power
supplies to stabilize.
The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain
high for the startup time. In most systems, this means that these signals should be pulled up with a resis-
tor so that a signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W
should hold the signals high with a power-on reset signal for longer than the startup time.
During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be
observed when power returns above VDD(min).
Figure 2.1 Power Up and Power Down Diagram
VDD
V
WI
BROWNOUT or POWER LOSS
2 ms
2 ms
STARTUP
RECOVER
NORMAL
OPERATION
NORMAL
OPERATION
READ/WRITE
INHIBITED
READ/WRITE
INHIBITED
VIH
VIH
E
W
Copyright © 2018 Everspin Technologies, Inc.
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MR4A16B Rev. 11.7 3/2018
Electrical Specifications
MR4A16B
Table 2.3 DC Characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Ilkg(I)
Input leakage current
All
-
1
1
μA
Ilkg(O)
Output leakage current
All
-
-
μA
V
IOL = +4 mA
0.4
VOL
Output low voltage
IOL = +100 μA
VSS + 0.2
V
IOH = -4 mA
2.4
-
-
V
V
VOH
Output high voltage
IOH = -100 μA
VDD - 0.2
Table 2.4 Power Supply Characteristics
Symbol Parameter
Typical
Max
Unit
AC active supply current - read modes1
(IOUT= 0 mA, VDD= max)
IDDR
60
68
mA
mA
AC active supply current - write modes1
(VDD= max)
IDDW
152
9
180
AC standby current
ISB1
(VDD= max, E = VIH)
14
9
mA
mA
no other restrictions on other inputs
CMOS standby current
ISB2
(E ≥ VDD - 0.2 V and VIn ≤VSS + 0.2 V or ≥ VDD - 0.2 V)
(VDD = max, f = 0 MHz)
5
1
All active current measurements are measured with one address transition per cycle and at minimum cycle time.
Copyright © 2018 Everspin Technologies, Inc.
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MR4A16B Rev. 11.7 3/2018
MR4A16B
3. TIMING SPECIFICATIONS
Table 3.1 Capacitance 1
Symbol Parameter
Typical
Max
Unit
pF
CIn
Address input capacitance
Control input capacitance
Input/Output capacitance
-
-
-
6
6
8
CIn
pF
CI/O
pF
1 f = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.
Table 3.2 AC Measurement Conditions
Parameter
Value
1.5
Unit
V
Logic input timing measurement reference level
Logic output timing measurement reference level
Logic input pulse levels
1.5
V
0 or 3.0
2
V
Input rise/fall time
ns
Output load for low and high impedance parameters
Output load for all other timing parameters
See Figure 3.1
See Figure 3.2
Figure 3.1 Output Load Test Low and High
ZD= 50 Ω
Output
RL = 50 Ω
VL = 1.5 V
Figure 3.2 Output Load Test All Others
3.3 V
590 Ω
Output
5 pF
435 Ω
Copyright © 2018 Everspin Technologies, Inc.
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MR4A16B Rev. 11.7 3/2018
Timing Specifications
MR4A16B
Table 3.3 Read Cycle Timing 1
Read Mode
Symbol
tAVAV
Parameter
Min
35
-
Max
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
Address access time
Enable access time 2
tAVQV
tELQV
tGLQV
tBLQV
tAXQX
tELQX
tGLQX
tBLQX
35
35
15
15
-
-
Output enable access time
-
Byte enable access time
-
Output hold from address change
Enable low to output active 3
Output enable low to output active 3
Byte enable low to output active 3
Enable high to output Hi-Z 3
Output enable high to output Hi-Z 3
Byte high to output Hi-Z 3
3
3
-
0
-
0
-
tEHQZ
tGHQZ
tBHQZ
0
15
10
10
0
0
1
W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be
minimized or eliminated during read or write cycles.
Addresses valid before or at the same time E goes low.
2
3
This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage.
Figure 3.3A Read Cycle 1
tAVAV
A (ADDRESS)
tAXQX
Previous Data Valid
Data Valid
Q (DATA OUT)
tAVQV
Note: Device is continuously selected (E≤VIL, G≤VIL).
Figure 3.3B Read Cycle 2
tAVAV
A (ADDRESS)
E (CHIP ENABLE)
tAVQV
tELQV
tEHQZ
tELQX
G (OUTPUT ENABLE)
LB, UB (BYTE ENABLE)
tGHQZ
tGLQV
tGLQX
tBHQZ
tBLQV
tBLQX
Data Valid
Q (DATA OUT)
Copyright © 2018 Everspin Technologies, Inc.
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MR4A16B Rev. 11.7 3/2018
Timing Specifications
MR4A16B
Table 3.4 Write Cycle Timing 1 (W Controlled) 1
Min
Symbol
Parameter
Write cycle time 2
Max
Unit
tAVAV
35
0
-
ns
tAVWL
tAVWH
tAVWH
Address set-up time
-
-
-
ns
ns
ns
20
20
Address valid to end of write (G high)
Address valid to end of write (G low)
tWLWH
tWLEH
tWLWH
tWLEH
tDVWH
15
15
-
-
ns
ns
Write pulse width (G high)
Write pulse width (G low)
Data valid to end of write
Data hold time
10
0
-
-
ns
ns
ns
ns
ns
tWHDX
tWLQZ
tWHQX
tWHAX
Write low to data Hi-Z 3
Write high to output active 3
Write recovery time
0
15
-
3
12
-
1
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must
remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being
asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given
voltage or temperate, tWLQZ(max) < tWHQX(min).
2
3
Figure 3.4 Write Cycle Timing 1 (W Controlled)
t
AVAV
A (ADDRESS)
t
t
AVWH
WHAX
E (CHIP ENABLE)
t
t
WLEH
WLWH
W (WRITE ENABLE)
t
AVWL
UB, LB (BYTE ENABLED)
D (DATA IN)
t
t
WHDX
DVWH
DATA VALID
t
WLQZ
Hi -Z
Hi -Z
Q (DATA OUT)
t
WHQX
Copyright © 2018 Everspin Technologies, Inc.
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MR4A16B Rev. 11.7 3/2018
Timing Specifications
MR4A16B
Table 3.5 Write Cycle Timing 2 (E Controlled) 1
Symbol
Parameter
Min
Max
Unit
ns
Write cycle time 2
35
-
-
-
-
tAVAV
tAVEL
tAVEH
tAVEH
Address set-up time
0
ns
Address valid to end of write (G high)
Address valid to end of write (G low)
20
20
ns
ns
tELEH
tELWH
tELEH
tELWH
Enable to end of write (G high)
Enable to end of write (G low) 3
15
15
-
-
ns
ns
tDVEH
tEHDX
tEHAX
Data valid to end of write
Data hold time
10
0
-
-
-
ns
ns
ns
Write recovery time
12
1
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W, E or UB/ LB has been brought high, the signal must
remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being
asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the
same time or before W goes high, the output will remain in a high-impedance state.
2
3
Figure 3.5 Write Cycle Timing 2 (E Controlled)
tAVAV
A (ADDRESS)
tEHAX
tAVEH
tELEH
E (CHIP ENABLE)
tAVEL
tELWH
W (WRITE ENABLE)
UB, LB (BYTE ENABLE)
D (DATA IN)
tEHDX
tDVEH
Data Valid
Hi-Z
Q (DATA OUT)
Copyright © 2018 Everspin Technologies, Inc.
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MR4A16B Rev. 11.7 3/2018
Timing Specifications
MR4A16B
Table 3.6 Write Cycle Timing 3 (LB/UB Controlled) 1
Min
Symbol
Parameter
Max
Unit
Write cycle time 2
35
0
-
ns
tAVAV
tAVBL
tAVBH
tAVBH
Address set-up time
-
-
-
ns
ns
ns
Address valid to end of write (G high)
Address valid to end of write (G low)
20
20
tBLEH
tBLWH
tBLEH
tBLWH
tDVBH
Write pulse width (G high)
Write pulse width (G low)
15
15
-
-
ns
ns
Data valid to end of write
Data hold time
10
0
-
-
-
ns
ns
ns
tBHDX
tBHAX
Write recovery time
12
1
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W
goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must remain
in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals must have no more than 2
ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent
cycle is the same as the minimum cycle time allowed for the device.
2
All write cycle timings are referenced from the last valid address to the first transition address.
Figure 3.6 Write Cycle Timing 3 (LB/UB Controlled)
t
AVAV
A (ADDRESS)
t
t
AVEH
BHAX
E (CHIP ENABLE)
W (WRITE ENABLE)
t
t
t
AVBL
BLEH
BLWH
UB, LB (BYTE ENABLED)
D (DATA IN)
t
t
BHDX
DVBH
Data Valid
Hi -Z
Hi -Z
Q (DATA OUT)
Copyright © 2018 Everspin Technologies, Inc.
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MR4A16B Rev. 11.7 3/2018
MR4A16B
4. ORDERING INFORMATION
Figure 4.1 Part Numbering System
MR
4
A
16
B
C
MA 35
R
Carrier
Speed
Blank = Tray, R = Tape & Reel
35 ns
Package
MA = FBGA, YS = TSOP
Temperature Range Blank= Commercial (0 to +70 °C),
C= Industrial (-40 to +85°C )
Revision
Data Width
Type
16 = 16-bit
A = Asynchronous
Density
4 =16Mb
Magnetoresistive RAM
Table 4.1 Available Parts
Shipping Con-
tainer
Grade
Temp Range
Package
Order Part Number
Trays
MR4A16BMA35
MR4A16BMA35R
MR4A16BYS35
48-BGA
Tape & Reel
Trays
Commercial
Industrial
0 to +70 °C
54-TSOP2
48-BGA
Tape & Reel
Tray
MR4A16BYS35R
MR4A16BCMA35
MR4A16BCMA35R
MR4A16BCYS35
MR4A16BCYS35R
Tape & Reel
Tray
-40 to +85°C
54-TSOP2
Tape & Reel
Copyright © 2018 Everspin Technologies, Inc.
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MR4A16B Rev. 11.7 3/2018
MR4A16B
5. MECHANICAL DRAWING
Figure 5.1 48-FBGA
BOTTOM VIEW
TOP VIEW
(DATUM B)
PIN A1
INDEX
PIN A1
INDEX
6
5 4 3 2 1
A
B
C
D
E
F
G
H
(DATUM A)
SEATING PLANE
SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION.
THE PRE-REFLOW DIAMETER IS
ø 0.35mm
Ref
A
Min
1.19
0.22
0.31
Nominal
Max
1.35
0.32
1.27
Print Version Not To Scale
A1
b
0.27
0.36
0.41
1. Dimensions in Millimeters.
10.00 BSC
10.00 BSC
5.25 BSC
3.75 BSC
0.375 BSC
0.375 BSC
0.75 BSC
D
E
2. The ‘e’represents the basic solder ball grid pitch.
3. ‘b’is measurable at the maximum solder ball diameter
in a plane parallel to datum C.
D1
E1
DE
SE
e
4. Dimension ‘ddd’is measured parallel to primary datum
C.
5. Primary datum C (seating plane) is defined by the
crowns
of the solder balls.
6. Package dimensions refer to JEDEC MO-205 Rev. G.
Ref
aaa
bbb
ddd
eee
fff
Tolerance of, from and position
0.10
0.10
0.10
0.15
0.08
Copyright © 2018 Everspin Technologies, Inc.
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MR4A16B Rev. 11.7 3/2018
MR4A16B
5. MECHANICAL DRAWING
Figure 5.2 54-TSOP2
A2
A1
A
D
54
28
θ2
θ3
c
1
27
⊕0.20(0.008) M
e
b
R1
R2
0.71 REF.
0.21(0.008)R
C
0.665(0.026)R
GAGE
0.25 mm
SEATING PLANE
0.10
C
Ref
A
Min
Nominal
Max
1.20
A1
A2
b
c
D
E
E1
e
0.05
0.95
0.10
1.00
0.35
0.15
1.05
0.45
Print Version Not To Scale
0.30
1. Dimensions in Millimeters.
0.12
0.21
2. Package dimensions refer to JEDEC MS-024
22.10
11.56
10.03
22.22
11.76
10.16
0.80 BSC
0.50
22.35
11.95
10.29
0.40
0.60
L
0.80 REF
-
L1
R1
R2
θ
0.12
0.12
0°
-
0.25
8°
-
-
0.40
-
-
θ1
θ2
θ3
15° REF
15° REF
Copyright © 2018 Everspin Technologies, Inc.
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MR4A16B Rev. 11.7 3/2018
MR4A16B
6. REVISION HISTORY
Rev Date
Description of Change
1
2
3
4
5
May 29, 2009
Establish Speed and Power Specifications
July 27, 2009
Nov 26, 2009
Mar 10, 2010
Apr 7, 2010
Increase BGA Package to 11 mm x 11 mm
Changed ball definition of H6 to A19 and G2 to NC in Figure 1.2.
Changed speed marking and timing specs to 35 ns part. Changed BGA package to 10 mm x 10mm
Added 54-TSOP package options.
Added AEC-Q100 Grade 1 product option. Max. magnetic field during write (Hmax_write ) increased
to 8000 A/m. Revised IDDW typical from110 to 152mA, max from TBD to 180mA; IDDR max from
TBD to 68mA; ISB1 typical from 11 to 9ma; ISB2 from typical 7 to 5mA.
6
Oct 7, 2011
Added note to BGA package option products are MSL-6 only, MSL-3 qualification underway.
Fixed typo on BGA drawing: Top View incorrectly labeled Bottom View.
7
8
9
Oct 28, 2011
Figure 2.1 Power Up and Power Down Timing redrawn. Added 54-TSOP illustrations. Re-
formatted all parametric tables. Reformatted Table 4.1 Ordering Part Numbers.
August 6, 2012
August 27, 2013
Corrected the AEC Q-100 Grade A ordering option to be available in 54-TSOP2, not 48-
BGA.
Jaunary 29,
2014
9.1
10
11
Corrected minor typo in Ordering PN table.
April 25, 2014
AEC-Q100 removed until qualified product is available.
48-BGA package options moisture sensitivity level upgraded to MSL-5.
Revised Everspin contact information.
September 17,
2014
11.1 May 19, 2015
11.2 June 11, 2015
11.3 July 29, 2015
11.4 March 11, 2016
Corrected Japan Sales Office telephone number.
Minor correction to the ‘ddd’tolerance value for the BGA Package (Note 4.)
The BGA package moisture sensitivity level rating is changed to MSL-6 in Table 4.1.
The BGA package moisture sensitivity level rating is changed to MSL-5 in Table 4.1.
All products meet MSL-3 moisture sensitivity level
November 22,
2016
11.5
11.6 May 09, 2017
11.7 March 23, 2018
Updated the Contact Us table
Copyright © 2018 Everspin Technologies, Inc.
15
MR4A16B Rev. 11.7 3/2018
7. HOW TO CONTACT US
Everspin Technologies, Inc.
How to Reach Us:
Home Page:
Information in this document is provided solely to enable system and software
implementers to use Everspin Technologies products. There are no express or
implied licenses granted hereunder to design or fabricate any integrated cir-
cuit or circuits based on the information in this document. Everspin Technolo-
gies reserves the right to make changes without further notice to any products
herein. Everspin makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Everspin
Technologies assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including
without limitation consequential or incidental damages. “Typical”parameters,
which may be provided in Everspin Technologies data sheets and/or speci-
fications can and do vary in different applications and actual performance
may vary over time. All operating parameters including “Typicals”must be
validated for each customer application by customer’s technical experts. Ever-
spin Technologies does not convey any license under its patent rights nor the
rights of others. Everspin Technologies products are not designed, intended,
or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for
any other application in which the failure of the Everspin Technologies product
could create a situation where personal injury or death may occur. Should
Buyer purchase or use Everspin Technologies products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Everspin Tech-
nologies and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such
claim alleges that Everspin Technologies was negligent regarding the design
or manufacture of the part. Everspin™ and the Everspin logo are trademarks of
Everspin Technologies, Inc. All other product or service names are the property
of their respective owners.
www.everspin.com
World Wide Information Request
WW Headquarters - Chandler, AZ
5670 W. Chandler Blvd., Suite 100
Chandler, Arizona 85226
Tel: +1-877-480-MRAM (6726)
Local Tel: +1-480-347-1111
Fax: +1-480-347-1175
support@everspin.com
orders@everspin.com
sales@everspin.com
Europe, Middle East and Africa
Everspin Europe Support
support.europe@everspin.com
Japan
Everspin Japan Support
support.japan@everspin.com
Asia Pacific
Everspin Asia Support
support.asia@everspin.com
Copyright © 2018 Everspin Technologies, Inc.
Filename:
EST00352_MR4A16B_Datasheet_Rev11.7032318
Copyright © 2018 Everspin Technologies, Inc.
16
MR4A16B Rev. 11.7 3/2018
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