MR256A08BYS35R [EVERSPIN]
32K x 8 MRAM;
| 型号： | MR256A08BYS35R |
| 厂家： | 
Everspin Technologies |
| 描述： | 32K x 8 MRAM 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总24页 (文件大小：1150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MR256A08B
32K x 8 MRAM
FEATURES
• 3.3 Volt power supply
• Fast 35 ns read/write cycle
• SRAM compatible timing
• Native non-volatility
48-ball FBGA
44-pin TSOP2
• Unlimited read & write endurance
• Data always non-volatile for >20 years at temperature
• Commercial and industrial temperatures
• All products meet MSL-3 moisture sensitivity level
• RoHS-Compliant TSOP2 and BGA packages
BENEFITS
• One memory replaces FLASH, SRAM, EEPROM and MRAM
in system for simpler, more efficient design
• Improves reliability by replacing battery-backed SRAM
INTRODUCTION
The MR256A08B is a 262,144-bit magnetoresistive random access
memory (MRAM) device organized as 32,768 words of 8 bits. The
MR256A08B offers SRAM compatible 35ns read/write timing with un-
limited endurance.
RoHS
Data is always non-volatile for greater than 20-years. Data is automatically protected on
power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification.
The MR256A08B is the ideal memory solution for applications that must permanently store
and retrieve critical data and programs quickly.
The MR256A08B is available in a small footprint 400-mil, 44-lead plastic small-outline TSOP
type-2 package, or an 8 mm x 8 mm, 48-pin ball grid array (BGA) package. (The 32-SOIC
package options is obsolete and no longer available for new orders.) All package footprints
are compatible with similar low-power SRAM products and other non-volatile RAM products.
The MR256A08B provides highly reliable data storage over a wide range of temperatures.
The product is offered with commercial temperature (0 to +70 °C) and industrial temperature
(-40 to +85 °C) range options.
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
TABLE OF CONTENTS
FEATURES .............................................................................................................................................1
BENEFITS...............................................................................................................................................1
INTRODUCTION ...................................................................................................................................1
BLOCK DIAGRAM AND PIN ASSIGNMENTS.......................................................................................4
Figure 1 – MR256A08B Block Diagram.................................................................................................................. 4
Table 1 – MR256A08B Pin Functions...................................................................................................................... 4
1 ...................................................................... 5
Figure 2 – Pin Diagrams for Available Packages (Top View)
Table 2 – Operating Modes....................................................................................................................................... 5
ELECTRICAL SPECIFICATIONS ............................................................................................................6
Absolute Maximum Ratings ...........................................................................................................6
Table 3 – Absolute Maximum Ratings................................................................................................................... 6
OPERATING CONDITIONS ...................................................................................................................7
Table 4 – Operating Conditions............................................................................................................................... 7
Power Up and Power Down Sequencing .......................................................................................8
Figure 3 – Power Up and Power Down Sequencing Timing Diagram....................................................... 8
DC CHARACTERISTICS.........................................................................................................................9
Table 5 – DC Characteristics...................................................................................................................................... 9
Table 6 – Power Supply Characteristics..............................................................................................................10
TIMING SPECIFICATIONS ................................................................................................................. 11
Table 7 – Capacitance ...............................................................................................................................................11
Table 8 – AC Measurement Conditions ..............................................................................................................11
Figure 4 – Output Load Test Low and High.......................................................................................................11
Figure 5 – Output Load Test All Others...............................................................................................................11
Read Mode .................................................................................................................................... 12
Table 9 – Read Cycle Timing ...................................................................................................................................12
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
TABLE OF CONTENTS (CONT’D)
Figure 6 – Read Cycle 1.............................................................................................................................................12
Figure 7 – Read Cycle 2.............................................................................................................................................13
Write Mode.................................................................................................................................... 14
Table 10 – Write Cycle Timing 1 (W Controlled)..............................................................................................14
Figure 8 – Write Cycle Timing 1 (W Controlled) ..............................................................................................15
Table 11 – Write Cycle Timing 2 (E Controlled)................................................................................................16
Figure 9 – Write Cycle Timing 2 (E Controlled) ................................................................................................17
ORDERING INFORMATION ............................................................................................................... 18
Table 12 – Ordering Part Number System for Parallel I/O MRAM..............................................................18
1..........................................................................................19
Table 13 – MR256A08B Ordering Part Numbers
PACKAGE OUTLINE DRAWINGS....................................................................................................... 20
Figure 10 – 44-TSOP2 Package Outline...............................................................................................................20
Figure 11 – 48-BGA Package Outline...................................................................................................................21
1 ..............................................................................................................22
Figure 12 – 32-SOIC Package Outline
REVISION HISTORY ........................................................................................................................... 23
HOW TO CONTACT US....................................................................................................................... 24
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
BLOCK DIAGRAM AND PIN ASSIGNMENTS
Figure 1 – MR256A08B Block Diagram
OUTPUT
ENABLE
BUFFER
ꢀ
OUTPUT ENABLE
ꢈ
ꢃꢄ1ꢅꢆ0ꢇ
1ꢁ
ADDRESS
BUFFER
ROW
8
COLUMN
DECODER
DECODER
CHIP
ENABLE
BUFFER
E
8
8
OUTPUT
BUFFER
8
SENSE
AMPS
32K x 8
BIT
MEMORY
ARRAY
WRITE
ENABLE
BUFFER
ꢂ
FINAL
WRITE
DRIVERS
8
8
WRITE
DRIVER
8
ꢉꢊꢄꢈꢆ0ꢇ
WRITE ENABLE
Table 1 – MR256A08B Pin Functions
Signal
Name
Function
A
Address Input
Chip Enable
Write Enable
E
W
G
Output Enable
Data I/O
DQ
V
Power Supply
DD
V
Ground
SS
DC
NC
Do Not Connect
No Connection - Pin 2, 40, 41,43 (TSOP2); Ball C2, C5, D3, F2, F5, G1, G2, G6, H1, H6 (BGA); Pin 9,
24, 31(SOIC) Reserved For Future Expansion
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
1
Figure 2 – Pin Diagrams for Available Packages ꢀTop Viewꢁ
DC
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
DC
NC
A
DC
NC
2
NC
1
2
3
4
5
6
3
DC
NC
NC
3
W
4
A
A
DC
G
A
A
A
DC
A
B
C
D
E
5
4
A13
A8
6
A14
A13
G
A
A
E
A
A
A
NC
DQ
DC
E
DC
DQ
A6
5
7
8
A5
6
A9
A
NC
DQ
NC
DQ
9
A4
7
A11
G
10
11
12
13
14
15
16
17
18
19
20
21
22
VSS
A
VDD
A3
8
NC
DC
VSS
A
VDD
VSS
V
SS
V
DD
NC
9
NC
DQ
NC
NC
A
DQ
VDD
A14
A13
VDD
A
VSS
A2
10
11
12
13
14
15
16
A10
E
DC
VSS
W
A1
F
DQ3
NC
DQ
NC
NC
NC
W
A
A
A
A
A
A
DC
DC
A0
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
A
G
H
DQ0
DQ1
DQ2
A
A
A
NC
DC
DC
V
SS
1
44 Pin TSOP2
32 Pin SOIC
48 Pin FBGA
Note:
1. The 32-SOIC package is obsolete and shown for legacy reference only. This package option is no longer
available for new orders.
Table 2 – Operating Modes
1
1
1
2
E
G
W
Mode
V Current
DQ[7:0]
DD
I
, I
H
X
X
Not selected
Output disabled
Byte Read
Hi-Z
Hi-Z
SB1 SB2
I
L
L
L
H
L
H
H
L
DDR
I
D
DDR
Out
I
X
Byte Write
D
DDW
in
Notes:
1. H = high, L = low, X = don’t care
2. Hi-Z = high impedance
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or
electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage
greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken to avoid
application of any magnetic field more intense than the maximum field intensity specified in the maximum
1
ratings.
Table 3 – Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
2
V
Supply voltage
-0.5 to 4.0
V
DD
2
V
Voltage on an pin
-0.5 to V + 0.5
V
mA
W
IN
DD
I
Output current per pin
20
OUT
3
P
Package power dissipation
Temperature under bias
0.600
D
MR256A08B (Commercial)
MR256A08BC (Industrial)
-10 to 85
-45 to 95
°C
T
BIAS
T
Storage Temperature
-55 to 150
260
°C
°C
stg
T
Lead temperature during solder (3 minute max)
Maximum magnetic field during write
Lead
H
2000
A/m
max_write
Maximum magnetic field during read or standby
H
8000
A/m
max_read
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional oper-
ation should be restricted to recommended operating conditions. Exposure to excessive voltages
or magnetic fields could affect device reliability.
2. All voltages are referenced to V .
SS
3. Power dissipation capability depends on package characteristics and use environment.
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
OPERATING CONDITIONS
Table 4 – Operating Conditions
Parameter
Symbol
Min
Typical
Max
Unit
1
Power supply voltage
V
3.0
3.3
3.6
V
DD
1
Write inhibit voltage
Input high voltage
Input low voltage
V
2.5
2.2
2.7
3.0
V
V
V
WI
2
V
-
-
V
+ 0.3
IH
DD
3
V
-0.5
0.8
IL
Temperature under bias
MR256A08B (Commercial)
MR256A08BC (Industrial)
T
0
70
85
°C
A
-40
Notes:
1. There is a 2 ms startup time once V exceeds V (min). See “Power Up and Power Down Sequencing Timing Diagram”.
DD
DD,
2. V (max) = V + 0.3 V ; V (max) = V + 2.0 V (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
DC
IH
DD
3. VIH(min) = -0D.5D V ; V (min) = -2.0 V (pulse wiAdCth ≤ 10 ns) for I ≤ 20.0 mA.
IL
DC
IL
AC
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
Power Up and Power Down Sequencing
The MRAM is protected from write operations whenever V is less than V . As soon as V exceeds V (min),
DD
WI
there is a startup time of 2 ms before read or write operations can start. This time allowsDmD emory poDwDer sup-
plies to stabilize.
The E and W control signals should track V on power up to V - 0.2 V or V (whichever is lower) and remain
DD
IH
high for the startup time. In most systems,DtDhis means that these signals should be pulled up with a resistor
so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should
hold the signals high with a power-on reset signal for longer than the startup time.
During power loss or brownout where V goes below V , writes are protected and a startup time must be
DD
WI
observed when power returns above V (min).
DD
Figure 3 – Power Up and Power Down Sequencing Timing Diagram
VDD
V
WI
BROWNOUT or POWER LOSS
2 ms
2 ms
STARTUP
RECOVER
NORMAL
OPERATION
NORMAL
OPERATION
READ/WRITE
INHIBITED
READ/WRITE
INHIBITED
VIH
VIH
E
W
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
DC CHARACTERISTICS
Table 5 – DC Characteristics
Parameter
Symbol
Min
Typical
Max
Unit
I
Input leakage current
-
-
1
μA
lkg(I)
I
Output leakage current
Output low voltage
-
-
1
μA
lkg(O)
(I = + 4 mA)
-
-
0.4
V
V
OL
OL
(I = + 100 μA)
V + 0.2
OL
SS
Output high voltage
(I = - 4 mA)
2.4
-
-
V
V
OL
OH
(I = - 100 μA)
V - 0.2
DD
OL
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
Table 6 – Power Supply Characteristics
Parameter
Symbol
Typical
Max
Unit
1
AC active supply current - read modes
(I = 0 mA, V = max)
25
30
mA
I
DDR
OUT
DD
1
AC active supply current - write modes
(V = max)
DD
MR256A08B (Commercial)
MR256A08BC (Industrial)
55
55
65
75
mA
I
DDW
AC standby current
(V = max, E = V )
DD
IH
no other restrictions on other inputs
MR256A08B (Commercial)
MR256A08BC (Industrial)
6
6
7
8
I
SB1
mA
mA
CMOS standby current
(E ≥ V - 0.2 V and V ≤V + 0.2 V or ≥ V - 0.2 V)
DD
In
SS
DD
(V = max, f = 0 MHz)
DD
MR256A08B (Commercial)
MR256A08BC (Industrial)
5
5
6
7
I
SB2
Notes:
1. All active current measurements are measured with one address transition per cycle and at minimum cycle time.
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
TIMING SPECIFICATIONS
Table 7 – Capacitance
1
Parameter
Symbol
Typical
Max
Unit
pF
C
Address input capacitance
Control input capacitance
-
-
6
6
In
C
pF
In
C
Input/Output capacitance
-
8
pF
I/O
Notes:
1. f = 1.0 MHz, dV = 3.0 V, T = 25 °C, periodically sampled rather than 100% tested.
A
Table 8 – AC Measurement Conditions
Parameter
Value
1.5
Unit
V
Logic input timing measurement reference level
Logic output timing measurement reference level
Logic input pulse levels
1.5
V
0 or 3.0
2
V
Input rise/fall time
ns
Output load for low and high impedance parameters
Output load for all other timing parameters
See Figure 4
See Figure 5
Figure 4 – Output Load Test Low and High
ZD= 50 Ω
Output
RL = 50 Ω
VL = 1.5 V
Figure 5 – Output Load Test All Others
3.3 V
590 Ω
Output
5 pF
435 Ω
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
Read Mode
Table 9 – Read Cycle Timing
1
Parameter
Symbol
Min
Max
-
Unit
ns
t
Read cycle time
AVAV
35
-
t
Address access time
AVQV
35
35
15
-
ns
2
t
Enable access time
ELQV
-
ns
t
Output enable access time
Output hold from address change
GLQV
-
ns
t
AXQX
3
3
0
0
0
ns
3
t
Enable low to output active
ELQX
-
ns
3
t
Output enable low to output active
GLQX
-
ns
3
t
Enable high to output Hi-Z
EHQZ
15
10
ns
3
t
Output enable high to output Hi-Z
GHQZ
ns
Notes:
1. W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be
minimized or eliminated during read or write cycles.
2. Addresses valid before or at the same time E goes low.
3. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage.
Figure 6 – Read Cycle 1
tAVAV
A (ADDRESS)
tAXQX
Previous Data Valid
Data Valid
Q (DATA OUT)
tAVQV
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
Figure 7 – Read Cycle 2
tAVAV
A (ADDRESS)
tAVQV
tELQV
E (CHIP ENABLE)
tEHQZ
tELQX
G (OUTPUT ENABLE)
Q (DATA OUT)
tGHQZ
tGLQV
tGLQX
Data Valid
13
Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
Write Mode
Table 10 – Write Cycle Timing 1 ꢀW Controlledꢁ
1
Parameter
Symbol
Min
35
0
Max
Unit
ns
2
t
Write cycle time
AVAV
-
-
t
Address set-up time
AVWL
ns
t
Address valid to end of write (G high)
AVWH
18
20
-
-
ns
ns
t
AVWH
Address valid to end of write (G low)
Write pulse width (G high)
t
t
WLWH
15
15
-
-
ns
ns
WLEH
t
t
WLWH
Write pulse width (G low)
WLEH
t
Data valid to end of write
Data hold time
DVWH
10
0
-
-
ns
ns
ns
ns
ns
t
WHDX
3
t
Write low to data Hi-Z
WLQZ
0
12
-
3
t
Write high to output active
WHQX
3
t
Write recovery time
Notes:
WHAX
12
-
1. All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or
after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must re-
main in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being
asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
2. All write cycle timings are referenced from the last valid address to the first transition address.
3. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any
given voltage or temperature, t
(max) < t
(min)
WLQZ
WHQX
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
Figure 8 – Write Cycle Timing 1 ꢀW Controlledꢁ
tAVAV
A (ADDRESS)
E (CHIP ENABLE)
tWHAX
tAVWH
tWLEH
tWLWH
W (WRITE ENABLE)
tAVWL
tDVWH
tWHDX
D (DATA IN)
Data Valid
tWLQZ
Hi-Z
Hi-Z
Q (DATA OUT)
tWHQX
15
Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
Table 11 – Write Cycle Timing 2 ꢀE Controlledꢁ
1
Parameter
Symbol
Min
35
0
Max
Unit
ns
2
t
Write cycle time
AVAV
-
-
t
Address set-up time
AVEL
ns
t
Address valid to end of write (G high)
Address valid to end of write (G low)
AVEH
18
20
-
-
ns
ns
t
AVEH
t
ELEH
Enable to end of write (G high)
15
15
-
-
ns
ns
t
ELWH
t
ELEH
3
Enable to end of write (G low)
t
ELWH
t
Data valid to end of write
Data hold time
DVEH
10
0
-
-
-
ns
ns
ns
t
EHDX
t
Write recovery time
Notes:
EHAX
12
1. All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain
in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being as-
serted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
2. All write cycle timings are referenced from the last valid address to the first transition address.
3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the
same time or before W goes high, the output will remain in a high-impedance state.
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
Figure 9 – Write Cycle Timing 2 ꢀE Controlledꢁ
tAVAV
A (ADDRESS)
E (CHIP ENABLE)
tEHAX
tAVEH
tELEH
tELWH
tAVEL
W (WRITE ENABLE)
tEHDX
tDVEH
D (DATA IN)
Data Valid
Hi-Z
Q (DATA OUT)
17
Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
ORDERING INFORMATION
Table 12 – Ordering Part Number System for Parallel I/O MRAM
Memory Density Type I/O Width
MR 256 08
Rev.
B
Temp Package Speed Packing Grade
MA 35
Example Ordering Part Number
A
C
R
MRAM
256 Kb
1 Mb
MR
256
0
4 Mb
2
16 Mb
Async 3.3v
4
A
D
Async 3.3v Vdd and 1.8v Vddq
DL
Async 3.3v Vdd and 1.8v Vddq with 2.7v min. Vdd
8-bit
08
16-bit
Rev A
Rev B
16
A
B
Commercial
Industrial
Extended
0 to 70°C
-40 to 85°C
-40 to 105°C
Blank
C
V
AEC Q-100 Grade 1 -40 to 125°C
44-TSOP-2
M
YS
48-FBGA
16-SOIC
MA
SC
32-SOIC
35 ns
SO
35
45 ns
45
Tray
Blank
R
ES
Blank
Blank
Tape and Reel
Engineering Samples
Customer Samples
Mass Producꢀon
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Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
1
Table 13 – MR256A08B Ordering Part Numbers
Temp Grade
Temp
Package
Shipping
Tray
Ordering Part Number
MR256A08BYS35
44-TSOP2
Tape and Reel
Tray
MR256A08BYS35R
MR256A08BMA35
Commercial
48-BGA
0 to +70 °C
Tape and Reel
Tray
MR256A08BMA35R
MR256A08BSO35 Obsolete
MR256A08BSO35R Obsolete
MR256A08BCYS35
1
32-SOIC
Tape and Reel
Tray
44-TSOP2
48-BGA
Tape and Reel
Tray
MR256A08BCYS35R
MR256A08BCMA35
Industrial
-40 to +85 °C
Tape and Reel
Tray
MR256A08BCMA35R
MR256A08BCSO35 Obsolete
MR256A08BCSO35R Obsolete
1
32-SOIC
Tape and Reel
1
The 32-SOIC package option is obsolete and no longer available. See PCN02895 here.
19
Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
PACKAGE OUTLINE DRAWINGS
Figure 10 – 44-TSOP2 Package Outline
Not To Scale
1. Dimensions and tolerances per ASME Y14.5M - 1994.
2. Dimensions in Millimeters.
3. Dimensions do not include mold protrusion.
4. Dimension does not include DAM bar protrusions.
5. DAM Bar protrusion shall not cause the lead width to
exceed 0.58.
44
20
Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
Figure 11 – 48-BGA Package Outline
TOP VIEW
0.41
0.31
0.32
0.22
SIDE VIEW
BOTTOM VIEW
Not To Scale
1. Dimensions in Millimeters.
2. Dimensions and tolerances per ASME Y14.5M - 1994.
3. Maximum solder ball diameter measured parallel to DATUM A
4. DATUM A, the seating plane is determined by the spherical crowns
of the solder balls.
5.
surface of package.
21
Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
1
Figure 12 – 32-SOIC Package Outline
PIN 1 ID
32
17
J
Reference JEDEC MO-119
K
1
16
A
I
G
D
C
H
E
F
B
Unit
A
B
C
D
E
F
G
H
I
J
K
mm - Min 20.574 1.00
- Max 20.878 1.50
0.355 0.66
0.508 0.81
0.101 2.286 Radius 0.533 0.152 7.416 10.287
0.254 2.540 0.101 1.041 0.304 7.594 10.642
inch - Min 0.810 0.04
- Max 0.822 0.06
0.14
0.02
0.026 0.004 0.09
0.032 0.010 0.10
Radius 0.021 0.006 0.292 0.405
0.0040 0.041 0.012 0.299 0.419
Note:
1. The 32-SOIC package is obsolete and shown for legacy reference only. This package option is no longer
available for new orders.
22
Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
REVISION HISTORY
Revision Date
Description of Change
Initial Advance Information Release
0
1
Sept 12, 2008
Mar 25, 2009
Add Industrial and Automotive Temperature Options
Removed Automotive temperature options. Included SOIC package.
Revised formatting
2
3
August 16, 2011
Changed TSOP-II to TSOP2. Changed logo to new EST Logo. Revisions to
Available Parts, Table 4.1: Added Industrial Temp Grade option in SOIC
package. Deleted Tape & Reel pack option for all SOIC packaged parts.
October 28, 2011
Dec 9, 2011
Figure 2.1 cosmetic update. Figure 5.2 BGA package outline drawing
revised for package ball size. Revisions to ISB1, ISB2 and IDDW for Indus-
trial Grade options in Table 2.4.
4
5
6
July 9, 2013
MR256A08BCSO35 removed Preliminary status. Now MP.
Added Tape and Reel shipping option for SOIC packaged products. Re-
formatted to current standards.
October 11, 2013
6.1
6.2
May 19, 2015
June 11, 2015
Revised Everspin contact information.
Corrected Japan Sales Office telephone number.
6.3
6.4
6.5
July 20, 2015
32-SOIC package options Not Recommended for New Designs.
32-SOIC package options are obsolete and no longer available.
Updated the Contact Us table
October 17, 2015
March 23, 2018
23
Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
MR256A08B
HOW TO CONTACT US
How to Reach Us:
Home Page:
Everspin Technologies, Inc.
Information in this document is provided solely to enable system and
software implementers to use Everspin Technologies products. There
are no express or implied licenses granted hereunder to design or
fabricate any integrated circuit or circuits based on the information
in this document. Everspin Technologies reserves the right to make
changes without further notice to any products herein. Everspin makes
no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose, nor does Everspin Technologies as-
sume any liability arising out of the application or use of any product or
circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical”parameters,
which may be provided in Everspin Technologies data sheets and/
or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters including
“Typicals”must be validated for each customer application by cus-
tomer’s technical experts. Everspin Technologies does not convey any
license under its patent rights nor the rights of others. Everspin Tech-
nologies products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other
application in which the failure of the Everspin Technologies product
could create a situation where personal injury or death may occur.
Should Buyer purchase or use Everspin Technologies products for any
such unintended or unauthorized application, Buyer shall indemnify
and hold Everspin Technologies and its officers, employees, subsidiar-
ies, affiliates, and distributors harmless against all claims, costs, dam-
ages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Ever-
spin Technologies was negligent regarding the design or manufacture
of the part. Everspin™ and the Everspin logo are trademarks of Everspin
Technologies, Inc. All other product or service names are the property
of their respective owners.
www.everspin.com
World Wide Information Request
WW Headquarters - Chandler, AZ
5670 W. Chandler Blvd., Suite 100
Chandler, Arizona 85226
Tel: +1-877-480-MRAM (6726)
Local Tel: +1-480-347-1111
Fax: +1-480-347-1175
support@everspin.com
orders@everspin.com
sales@everspin.com
Europe, Middle East and Africa
Everspin Europe Support
support.europe@everspin.com
Japan
Everspin Japan Support
support.japan@everspin.com
Asia Pacific
Everspin Asia Support
support.asia@everspin.com
Copyright © Everspin Technologies, Inc. 2018
Filename:
EST00355_MR256A08B_Datasheet_Rev6.5032318
24
Copyright © 2018 Everspin Technologies
MR256A08B Rev. 6.5 3/2018
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