MR0D08B [EVERSPIN]
Dual Supply 128K x 8 MRAM;型号: | MR0D08B |
厂家: | Everspin Technologies |
描述: | Dual Supply 128K x 8 MRAM |
文件: | 总16页 (文件大小:776K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MR0D08B
Dual Supply 128K x 8 MRAM
FEATURES
• +3.3 Volt power supply
• I/O Voltage range supports wide +1.65 to +3.6 Volt interfaces
• Fast 45 ns read/write cycle
• SRAM compatible timing
• Unlimited read & write endurance
• Data always non-volatile for >20-years at temperature
• RoHS-compliant small footprint BGA package
BENEFITS
• One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems
for simpler, more efficient designs
RoHS
• Improves reliability by replacing battery-backed SRAM
INTRODUCTION
The MR0D08B is a dual power supply 1,048,576-bit magnetoresistive random access memory (MRAM) de-
vice organized as 131,072 words of 8 bits. It supports I/O voltages from +1.65 to +3.6 volts. The MR0D08B
offers SRAM compatible 45ns read/write timing with unlimited endurance. Data is always non-volatile for
greater than 20-years. Data is automatically protected on power loss by low-voltage inhibit circuitry to pre-
vent writes with voltage out of specification. The MR0D08B is the ideal memory solution for applications
that must permanently store and retrieve critical data and programs quickly.
The MR0D08B is available in small footprint 8 mm x 8 mm, 48-pin ball grid array (BGA) package with 0.75
mm ball centers.
The MR0D08B provides highly reliable data storage over a wide range of temperatures. The product is of-
fered with commercial temperature (0 to +70 °C).
CONTENTS
1. DEVICE PIN ASSIGNMENT......................................................................... 2
2. ELECTRICAL SPECIFICATIONS................................................................. 4
3. TIMING SPECIFICATIONS.......................................................................... 8
4. ORDERING INFORMATION....................................................................... 13
5. MECHANICAL DRAWING.......................................................................... 14
6. REVISION HISTORY...................................................................................... 15
How to Reach Us.......................................................................................... 15
Copyright © Everspin Technologies 20158
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MR0D08B Rev. 3.3, 3/2018
MR0D08B
1. DEVICE PIN ASSIGNMENT
Figure 1.1 Block Diagram
OUTPUT
ENABLE
ꢀ
OUTPUT ENABLE
BUFFER
ꢁ
ꢃꢄ1ꢅꢆ0ꢇ ADDRESS
10
ROW
DECODER
BUFFER
COLUMN
DECODER
1ꢁ
CHIP
ENABLE
BUFFER
E
8
8
OUTPUT
BUFFER
8
SENSE
AMPS
128Kx 8
BIT
MEMORY
ARRAY
WRITE
ENABLE
BUFFER
ꢂ
FINAL
WRITE
DRIVERS
8
8
WRITE
DRIVER
8
ꢈꢉꢄꢁꢆ0ꢇ
WRITE ENABLE
Table 1.1 Pin Functions
Signal Name
Function
A
Address Input
Chip Enable
Write Enable
Output Enable
Data I/O
E
W
G
DQ
VDD
Power Supply
VDDQ
VSS
I/O Power Supply
Ground
DC
NC
Do Not Connect
No Connection, Ball D3, H1, H6, G2 Reserved for Future Expansion
Copyright © Everspin Technologies 2018
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MR0D08B Rev. 3.3, 3/2018
DEVICE PIN ASSIGNMENT
MR0D08B
Figure 1.2 Pin Diagrams for Available Packages (Top View)
1
2
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢅ
ꢅ
ꢉꢇꢇ
ꢅ
ꢆ
C
ꢇ
E
ꢇC
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢌC
ꢇꢈ
ꢇC
ꢉꢇꢇ
ꢇꢈ
ꢇꢈ
E
ꢇC
ꢇꢈ
ꢌC
ꢇꢈ
ꢉꢊꢊ
ꢉꢇꢇꢈ
ꢌC
ꢇC
ꢇꢈ
ꢉꢇꢇꢈ
ꢉꢊꢊ
ꢋ
ꢇꢈꢀ
ꢌC
ꢌC
ꢌC
ꢅ
ꢇꢈ
ꢌC
ꢌC
ꢌC
ꢍ
ꢅ
ꢄ
ꢎ
ꢅ
ꢅ
ꢅ
ꢅ
ꢌC
48 Pin FBGA
Table 1.2 Operating Modes
E1
H
L
G1
X
W1
X
Mode
Not selected
Output disabled
Byte Read
VDD Current
DQ[7:0]2
Hi-Z
ISB1, ISB2
H
L
H
IDDR
Hi-Z
L
H
IDDR
DOut
L
X
L
Byte Write
IDDW
Din
1
2
H = high, L = low, X = don’t care
Hi-Z = high impedance
Copyright © Everspin Technologies 2018
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MR0D08B Rev. 3.3, 3/2018
MR0D08B
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or
electric fields; however, it is advised that normal precautions be taken to avoid application of any
voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken
to avoid application of any magnetic field more intense than the maximum field intensity specified
in the maximum ratings.
Table 2.1 Absolute Maximum Ratings1
Parameter
Core Supply voltage2
I/O Power Supply voltage2
Symbol
Value
-0.5 to 4.0
-0.5 to 4.0
-0.5 to +4.0 or
VDDQ + 0.5
whichever is less
20
Unit
V
VDD
VDDQ
VIN
V
Voltage on any pin2
V
IOUT
PD
Output current per pin
Package power dissipation 3
mA
W
0.600
TBIAS
Temperature under bias
-10 to 85
-55 to 150
260
°C
Tstg
Storage Temperature
°C
TLead
Lead temperature during solder (3 minute max)
Maximum magnetic field during write
Maximum magnetic field during read or standby
°C
Hmax_write
Hmax_read
2000
A/m
A/m
8000
1
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera-
tion should be restricted to recommended operating conditions. Exposure to excessive voltages or
magnetic fields could affect device reliability.
2
3
All voltages are referenced to VSS.
Power dissipation capability depends on package characteristics and use environment.
Copyright © Everspin Technologies 2018
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MR0D08B Rev. 3.3, 3/2018
Electrical Specifications
MR0D08B
Table 2.2 Operating Conditions
Parameter
Symbol
VDD
Min
3.0 1
1.65 1
2.5
Typical
Max
3.6
Unit
V
Core Power supply voltage
I/O Power supply voltage
3.3
VDDQ
VWIDD
VWIDDQ
VIH
-
3.6
3.01
1.651
V
Write inhibit voltage
2.7
V
Write inhibit voltage
1.2
1.4
V
Input high voltage (VDDQ=1.65-2.2V)
Input high voltage (VDDQ=2.2-2.7V)
Input high voltage (VDDQ=2.7-3.6V)
Input low voltage (VDDQ=1.65-2.2V)
Input low voltage (VDDQ=2.2-2.7V)
Input low voltage (VDDQ=2.7-3.6V)
Temperature under bias
1.4
-
-
-
-
-
-
VDDQ + 0.22
VDDQ + 0.22
VDDQ + 0.22
0.4
V
VIH
1.8
V
VIH
2.2
V
VIL
-0.2 3
-0.2 3
-0.2 3
0
V
VIL
0.6
V
VIL
0.8
V
TA
70
°C
1
VDDQ≤VDD. Write inhibit occurs when either VDD or VDDQ drops below its write inhibit voltage. There is a 2 ms startup time once
VDD exceeds VDD(min). See Power Up and Power Down Sequencing.
VIH(max) = VDDQ + 0.2 V DC ; VIH(max) = VDDQ + 0.5 V AC (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
VIL(min) = -0.2 V DC ; VIL(min) = -2.0 V AC (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
2
3
Copyright © Everspin Technologies 2018
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MR0D08B Rev. 3.3, 3/2018
Electrical Specifications
MR0D08B
Power Up and Power Down Sequencing
The MRAM is protected from write operations whenever VDD is less than VWIDD or VDDQ is less than VWIDDQ. As
soon as VDD exceeds VDD(min) and VDDQ exceeds VDDQ(min), there is a startup time of 2 ms before read or write
operations can start. This time allows memory power supplies to stabilize.
The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain
high for the startup time. In most systems, this means that these signals should be pulled up with a resis-
tor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W
should hold the signals high with a power-on reset signal for longer than the startup time.
During power loss or brownout where either VDD goes below VWIDD or VDDQ goes below VWIDDQ, writes are pro-
tected and a startup time must be observed when power returns above VDD(min) and / or VDDQ
.
Figure 2.1 Power Up and Power Down Diagram
VDD / VDDQ
V
WIDD
V
WIDDQ
2 ms
2 ms
BROWNOUT or POWER LOSS
STARTUP
RECOVER
NORMAL
OPERATION
NORMAL
OPERATION
READ/WRITE
INHIBITED
READ/WRITE
INHIBITED
VIH
VIH
E
W
Copyright © Everspin Technologies 2018
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MR0D08B Rev. 3.3, 3/2018
Electrical Specifications
MRD08B
Table 2.3 DC Characteristics
Parameter
Symbol
Min Typical Max
Unit
Ilkg(I)
Input leakage current
-
-
-
-
-
-
-
-
-
-
1
1
μA
Ilkg(O)
Output leakage current
μA
V
VOL
VOL
VOL
VOH
VOH
VOH
Output low voltage (VDDQ=1.65-2.2V@ 0.1mA)
Output low voltage (VDDQ=2.2-2.7V@ 0.1mA)
Output low voltage (VDDQ=2.7-3.6V@ 2.1 mA)
Output high voltage (VDDQ=1.65-2.2V@ - 0.1 mA)
Output high voltage (VDDQ=2.2-2.7V@ -0.1 mA)
Output high voltage (VDDQ=2.7-3.6V@ -1.0 mA)
-
0.2
0.4
0.4
-
-
V
-
V
1.4
2
V
-
V
2.4
-
V
Table 2.4 Power Supply Characteristics
Parameter
Symbol
Typical
Max
Unit
AC active supply current - read modes1
(IOUT= 0 mA, VDD= max)
IDDR
25
30
mA
mA
AC active supply current - write modes1
(VDD= max)
IDDW
55
65
2
AC active operating current
(VDDQ = VIH= 3.6V, VIL= 0V)
IDDQ
0.50
mA
mA
mA
input transitions <2ns, no output load
AC standby current
(VDD= max, E = VIH)
ISB1
6
5
8
7
no other restrictions on other inputs
CMOS standby current
(E ≥ VDD - 0.2 V and VIn ≤VSS + 0.2 V or ≥ VDDQ - 0.2 V)
(VDD = max, f = 0 MHz)
ISB2
1
All active current measurements are measured with one address transition per cycle and at minimum cycle time.
Copyright © Everspin Technologies 2018
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MR0D08B Rev. 3.3, 3/2018
MR0D08B
3. TIMING SPECIFICATIONS
Table 3.1 Capacitance1
Symbol
Parameter
Typical
Max
Unit
pF
Address input capacitance
Control input capacitance
CIn
CIn
-
-
-
6
6
8
pF
Input/Output capacitance
CI/O
pF
1
f = 1.0 MHz, VDDQ=VDDQ(typ), TA = 25 °C, periodically sampled rather than 100% tested.
Table 3.2 AC Measurement Conditions
Parameter
VDDQ=1.8
0.8
VDDQ=2.5
VDDQ=3.3
0.8
Unit
Logic input timing measurement reference level
Logic output timing measurement reference level
Logic input pulse levels
0.8
0.8
V
V
V
0.8
0.8
0 or 1.8
0 or 2.5
0 or 3.3
Output load voltage (VL) for low & high impedance
parameters (Figure 3.1)
0.8
1.2
1.75
V
Output load resistor (R1) for all other timing
Output load resistor (R2) for all other timing
13,500
10,800
16,600
15,400
1,103
1,554
Ω
Ω
Figure 3.1 Output Load Test Low and High
ZD= 50 Ω
Output
RL = 50 Ω
VL
Figure 3.2 Output Load Test All Others
VDDQ
R1
Output
30 pF
R2
Copyright © Everspin Technologies 2018
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MR0D08B Rev. 3.3, 3/2018
Timing Specifications
MR0D08B
Read Mode
Table 3.3 Read Cycle Timing1
Parameter
Symbol
Min
Max
Unit
ns
tAVAV
Read cycle time
45
-
-
tAVQV
tELQV
Address access time
Enable access time2
45
45
20
-
ns
-
ns
tGLQV
tAXQX
tELQX
Output enable access time
Output hold from address change
Enable low to output active3
Output enable low to output active3
Enable high to output Hi-Z3
-
ns
3
3
0
0
0
ns
-
ns
tGLQX
-
ns
tEHQZ
tGHQZ
15
15
ns
Output enable high to output Hi-Z3
ns
1
W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be
minimized or eliminated during read or write cycles.
Addresses valid before or at the same time E goes low.
2
3
This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage.
Figure 3.3A Read Cycle 1
tAVAV
A (ADDRESS)
tAXQX
Previous Data Valid
Data Valid
Q (DATA OUT)
tAVQV
NOTE: Device is continuously selected (E ≤ VIL, G ≤ VIL)
Figure 3.3B Read Cycle 2
tAVAV
A (ADDRESS)
tAVQV
tELQV
E (CHIP ENABLE)
tEHQZ
tELQX
G (OUTPUT ENABLE)
Q (DATA OUT)
tGHQZ
tGLQV
tGLQX
Data Valid
Copyright © Everspin Technologies 2018
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MR0D08B Rev. 3.3, 3/2018
Timing Specifications
MR0D08B
Table 3.4 Write Cycle Timing 1 (W Controlled)1
Parameter
Write cycle time2
Symbol
Min
45
0
Max
Unit
ns
tAVAV
-
-
-
-
tAVWL
Address set-up time
ns
tAVWH
Address valid to end of write (G high)
Address valid to end of write (G low)
25
25
ns
tAVWH
ns
tWLWH
tWLEH
tWLWH
tWLEH
tDVWH
Write pulse width (G high)
Write pulse width (G low)
20
20
-
-
ns
ns
Data valid to end of write
Data hold time
Write low to data Hi-Z3
Write high to output active3
15
0
-
-
ns
ns
ns
ns
ns
tWHDX
tWLQZ
tWHQX
tWHAX
0
15
-
3
Write recovery time
12
-
1
All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given
voltage or temperature, tWLQZ(max) < tWHQX(min)
2
3
Figure 3.4 Write Cycle Timing 1 (W Controlled)
tAVAV
A (ADDRESS)
tWHAX
tAVWH
E (CHIP ENABLE)
tWLEH
tWLWH
W (WRITE ENABLE)
tAVWL
tDVWH
tWHDX
D (DATA IN)
Data Valid
tWLQZ
Hi-Z
Hi-Z
Q (DATA OUT)
tWHQX
MR0D08B Rev. 3.3, 3/2018
Copyright © Everspin Technologies 2018
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Timing Specifications
MR0D08B
Table 3.5 Write Cycle Timing 2 (E Controlled)1
Parameter
Symbol
Min
45
0
Max
Unit
ns
Write cycle time2
-
-
-
-
tAVAV
tAVEL
tAVEH
Address set-up time
ns
Address valid to end of write (G high)
Address valid to end of write (G low)
25
25
ns
tAVEH
ns
tELEH
tELWH
tELEH
tELWH
tDVEH
Enable to end of write (G high)
Enable to end of write (G low)3
20
20
-
-
ns
ns
Data valid to end of write
Data hold time
15
0
-
-
-
ns
ns
ns
tEHDX
tEHAX
Write recovery time
12
1
All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the
same time or before W goes high, the output will remain in a high-impedance state.
2
3
Figure 3.5 Write Cycle Timing 2 (E Controlled)
tAVAV
A (ADDRESS)
tEHAX
tAVEH
tELEH
E (CHIP ENABLE)
tAVEL
tELWH
W (WRITE ENABLE)
D (DATA IN)
tEHDX
tDVEH
Data Valid
Copyright © Everspin Technologies 2018
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MR0D08B Rev. 3.3, 3/2018
Timing Specifications
MR0D08B
Table 3.6 Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled)1
Parameter
Symbol
Min
Max
Unit
Write cycle time2
45
-
ns
tAVAV
tAVWL
tAVWH
tAVWH
Address set-up time
0
-
ns
Address valid to end of write (G high)
Address valid to end of write (G low)
25
25
-
-
ns
ns
tWLWH
tWLEH
tDVWH
Write pulse width
20
-
ns
Data valid to end of write
Data hold time
15
0
-
-
ns
ns
tWHDX
tEHAX
tWHAX
tWHEL
Enable recovery time
-2
6
-
-
-
ns
ns
ns
Write recovery time3
Write to enable recovery time3
12
1
All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the
same time or before W goes high, the output will remain in a high-impedance state.
2
3
Table 3.6 Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled)
tAVAV
A (ADDRESS)
t
tAVWH
tEHAX
E (CHIP ENABLE)
t WLEH
tWLWH
tWHEL
tWHDX
W (WRITE ENABLE)
t AVWL
t DVWH
D (DATA IN)
Copyright © Everspin Technologies 2018
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MR0D08B Rev. 3.3, 3/2018
MR0D08B
4. ORDERING INFORMATION
Figure 4.1 Part Numbering System
MR
0
D
08
B
MA 45
R
Carrier
Speed
(Blank= Tray,R=Tape & Reel)
(45 = 45 ns)
Package
Temperature Range
Revision
Data Width
Type
(MA = FBGA)
(Blank= 0 to +70 °C)
(B = Revision)
(08 = 8-Bit)
(D = Dual Supply)
(0 = 1Mb)
Density
Part Type
(MR = Magnetoresistive
RAM)
Table 4.1 Available Parts
Description
Part Number
Temperature
MR0D08BMA45
Dual Supply 128x8 MRAM 48-BGA
Commercial
Dual Supply 128x8 MRAM 48-BGA
Tape & Reel
MR0D08BMA45R
Commercial
Copyright © Everspin Technologies 2018
13
MR0D08B Rev. 3.3, 3/2018
Mechanical Drawings
MR0D08B
Figure 5.1 FBGA
TOP VIEW
0.41
0.31
0.32
0.22
SIDE VIEW
BOTTOM VIEW
Print Version Not To Scale
1. Dimensions in Millimeters.
2. Dimensions and tolerances per ASME Y14.5M - 1994.
3. Maximum solder ball diameter measured parallel to DATUM A
4. DATUM A, the seating plane is determined by the spherical
crowns of the solder balls.
5. Parallelism measurement shall exclude any effect of mark on
top surface of package.
Copyright © Everspin Technologies 2018
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MR0D08B Rev. 3.3, 3/2018
MR0D08B
6. REVISION HISTORY
Revision
Date
Description of Change
0
Aug 24, 2009 Initial Product Concept
Added Write Cycle Timing 3. In table 2.4, ISB1 max changes from 7 to 8 mA and
Oct 22, 2009 ISB2 from 6 to 7 mA. Added Tape & Reel Option in table 4.1. Changed to Pro-
duction Level
1
2
Apr 7, 2010
Dec 9, 2011
Added IDDQ specification in table 2.4.
3
Corrected Figure 5.1 FBGA drawing ball dimensions.
3.1
3.2
May 19, 2015 Revised contact information on Contact US page.
June 11, 2015 Correction to Japan Sales Office telephone number.
March 22,
3.3
Updated the Contact Us table
2018
Copyright © Everspin Technologies 2018
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MR0D08B Rev. 3.3, 3/2018
HOW TO CONTACT US
Home Page:
Everspin Technologies, Inc.
www.everspin.com
Information in this document is provided solely to enable system and
software implementers to use Everspin Technologies products. There are
no express or implied licenses granted hereunder to design or fabricate any
integrated circuit or circuits based on the information in this document.
Everspin Technologies reserves the right to make changes without further
notice to any products herein. Everspin makes no warranty, representa-
tion or guarantee regarding the suitability of its products for any particular
purpose, nor does Everspin Technologies assume any liability arising out of
the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or inci-
dental damages. “Typical”parameters, which may be provided in Everspin
Technologies data sheets and/or specifications can and do vary in differ-
ent applications and actual performance may vary over time. All operating
parameters including “Typicals”must be validated for each customer ap-
plication by customer’s technical experts. Everspin Technologies does not
convey any license under its patent rights nor the rights of others. Everspin
Technologies products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other ap-
plication in which the failure of the Everspin Technologies product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Everspin Technologies products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Everspin Tech-
nologies and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even
if such claim alleges that Everspin Technologies was negligent regarding
the design or manufacture of the part. Everspin™ and the Everspin logo are
trademarks of Everspin Technologies, Inc.
World Wide Information Request
WW Headquarters - Chandler, AZ
5670 W. Chandler Blvd., Suite 100
Chandler, Arizona 85224
Tel: +1-877-480-MRAM (6726)
Local Tel: +1-480-347-1111
Fax: +1-480-347-1175
support@everspin.com
Europe, Middle East and Africa
Everspin Europe Support
support.europe@everspin.com
Japan
Everspin Japan Support
support.japan@everspin.com
Asia Pacific
Everspin Asia Support
support.asia@everspin.com
Filename:
All other product or service names are the property of their respective owners.
MR0D08B_Datasheet_EST370_Rev3.3 032218
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MR0D08B Rev. 3.3, 3/2018
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