MR0A16ACMA35R [EVERSPIN]
64K x 16 MRAM Memory;型号: | MR0A16ACMA35R |
厂家: | Everspin Technologies |
描述: | 64K x 16 MRAM Memory 静态存储器 内存集成电路 |
文件: | 总22页 (文件大小:930K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MR0A16A
64K x 16 MRAM Memory
FEATURES
• 3.3 Volt power supply
• Fast 35ns read/write cycle
• SRAM compatible timing
• Unlimited read & write endurance
• Commercial, Industrial, and Extended Temperatures
• Data non-volatile for >20 years at temperature
• RoHS-compliant TSOP2 and BGA packages available
• All products meet MSL-3 moisture sensitivity level
• Automotive AEC-Q100 Grade 1 option available
44-pin TSOP2
BENEFITS
• One memory replaces FLASH, SRAM, EEPROM and BBSRAM
in system for simpler, more efficient designs
48-ball BGA
• Improves reliability by replacing battery-backed SRAM
• Automatic data protection on power loss
RoHS
INTRODUCTION
The MR0A16A is a 1,048,576-bit magnetoresistive random access memory (MRAM) device organized as
65,536 words of 16 bits. The MR0A16A offers SRAM compatible 35 ns read/write timing with unlimited en-
durance. Data is always non-volatile for greater than 20 years. Data is automatically protected on power loss
by low-voltage inhibit circuitry to prevent writes with voltage out of specification.
MR0A16A is the ideal memory solution for applications that must permanently store and retrieve critical
data and programs quickly.
The MR0A16B is available in a small footprint 48-pin ball grid array (BGA) package and a 44-pin thin small
outline package (TSOP Type 2). These packages are compatible with similar low-power SRAM products and
other nonvolatile RAM products.
The MR0A16A provides highly reliable data storage over a wide range of temperatures. The product is avail-
able with commercial temperature (0 to +70 °C), industrial temperature (-40 to +85 °C), extended tempera-
ture (-40 to +105 °C), and Automotive AEC-Q100 Grade 1 (-40 to +125°) temperature range options.
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
TABLE OF CONTENTS
FEATURES .............................................................................................................................................1
BENEFITS...............................................................................................................................................1
INTRODUCTION ...................................................................................................................................1
BLOCK DIAGRAM AND PIN ASSIGNMENTS.......................................................................................4
Figure 1 – Block Diagram........................................................................................................................................... 4
Table 1 – Pin Functions............................................................................................................................................... 4
Figure 2 – MR0A16A Package Pinouts .................................................................................................................. 5
OPERATING MODES.............................................................................................................................5
Table 2 – Operating Modes....................................................................................................................................... 5
ABSOLUTE MAXIMUM RATINGS.........................................................................................................6
Table 3 – Absolute Maximum Ratings................................................................................................................... 6
OPERATING CONDITIONS ...................................................................................................................7
Table 4 – Operating Conditions............................................................................................................................... 7
Power Up and Power Down Sequencing .......................................................................................8
Figure 3 – Power Up and Power Down Timing ................................................................................................. 8
DC CHARACTERISTICS.........................................................................................................................9
Table 5 – DC Characteristics...................................................................................................................................... 9
Table 6 – Power Supply Characteristics................................................................................................................ 9
TIMING SPECIFICATIONS ................................................................................................................. 10
Table 7 – Capacitance ...............................................................................................................................................10
Table 8 – AC Measurement Conditions ..............................................................................................................10
Figure 4 – Output Load Test Low and High.......................................................................................................10
Figure 5 – Output Load Test All Others...............................................................................................................10
Table 9 – Read Cycle Timing ...................................................................................................................................11
Figure 6 – Read Cycle 1.............................................................................................................................................12
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
TABLE OF CONTENTS - continued
Figure 7 – Read Cycle 2.............................................................................................................................................12
Table 10 – Write Cycle Timing 1 (W Controlled) ..............................................................................................13
Figure 8 – Write Cycle Timing 1 (W Controlled)...............................................................................................14
Table 11 – Write Cycle Timing 2 (E Controlled)................................................................................................15
Figure 9 – Write Cycle Timing 2 (E Controlled)................................................................................................15
Table 12 – Write Cycle Timing 3 (LB/UB Controlled).....................................................................................16
Figure 10 – Write Cycle Timing 3 (UB/LB Controlled)...................................................................................16
ORDERING INFORMATION ............................................................................................................... 17
Table 13 – Part Numbering System......................................................................................................................17
Table 14 – MR0A16A Ordering Part Numbers..................................................................................................18
PACKAGE OUTLINE DRAWINGS....................................................................................................... 19
Figure 11 – 44-pin TSOP2.........................................................................................................................................19
Figure 12 – 48-ball FBGA..........................................................................................................................................20
REVISION HISTORY ........................................................................................................................... 21
HOW TO CONTACT US....................................................................................................................... 22
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
BLOCK DIAGRAM AND PIN ASSIGNMENTS
Figure 1 – Block Diagram
OUTPUT
ENABLE
BUFFER
UPPER BYTE OUTPUT ENABLE
LOWER BYTE OUTPUT ENABLE
G
8
UPPER
BYTE
OUTPUT
BUFFER
A[15:0] ADDRESS
8
ROW
DECODER
8
BUFFER
COLUMN
DECODER
16
8
8
SENSE
AMPS
CHIP
ENABLE
BUFFER
E
LOWER
BYTE
OUTPUT
BUFFER
8
16
64K x 16
BIT
MEMORY
ARRAY
UPPER
BYTE
WRITE
8
8
WRITE
ENABLE
BUFFER
DQU[15:8]
DQL[7:0]
W
8
8
DRIVER
FINAL
WRITE
DRIVERS
16
LOWER
BYTE
WRITE
DRIVER
UB
LB
UB
UPPER BYTE WRITE ENABLE
LOWER BYTE WRITE ENABLE
BYTE
ENABLE
BUFFER
LB
Table 1 – Pin Functions
Function
Signal Name
Address Input
Chip Enable
Write Enable
Output Enable
A
E
W
G
Upper Byte Enable
Lower Byte Enable
Data I/O
UB
LB
DQ
Power Supply
VDD
VSS
Ground
Do Not Connect
No Connection
DC
NC
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
Figure 2 – MR0A16A Package Pinouts
1
2
3
4
5
6
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
A
A
A
A
A
LB
G
A0
A1
A2
NC
A
B
C
D
E
3
4
G
UB
A
A
E
5
DQU8
DQU9
DQL0
DQL2
UB
A3
A5
A4
A6
E
6
LB
7
DQU15
DQU14
DQU13
DQU12
DQL0
DQL1
DQL2
DQL3
8
DQU10
DQU11
DQU12
DQU13
DQL1
DQL3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VSS
VDD
VSS
A15
NC
VDD
VSS
VSS
V
DD
DQU11
DQU10
DQU9
DQU8
DC
DQL4
DQL5
DQL6
DQL7
VDD
A14
A13
A11
A9
DQL4
DQL5
VSS
F
DQU14
DQU15
NC
DQL6
DQL7
A12
A10
A8
W
A
A
A
A
A
V
DD
G
H
VSS
NC
A7
W
A
A
A
VDD
DC
44-Pin TSOP Type 2
48-Pin BGA
OPERATING MODES
Table 2 – Operating Modes
Mode
VDD Current
ISB1, ISB2
IDDR
DQL[7:0] 2
Hi-Z
Hi-Z
Hi-Z
DOut
Hi-Z
DOut
Din
DQU[15:8] 2
Hi-Z
E 1
H
G 1
X
W 1
X
LB 1
X
UB 1
X
Not selected
L
L
L
L
L
L
L
H
X
L
H
X
H
H
H
L
X
H
L
X
H
H
L
Output disabled
Output disabled
Lower Byte Read
Upper Byte Read
Word Read
Hi-Z
IDDR
Hi-Z
IDDR
Hi-Z
L
H
L
IDDR
DOut
DOut
Hi-Z
L
L
IDDR
X
X
X
L
H
L
Lower Byte Write
Upper Byte Write
Word Write
IDDW
L
H
L
IDDW
Hi-Z
Din
Din
L
L
L
IDDW
Din
Notes:
1. H = high, L = low, X = don’t care
2. Hi-Z = high impedance
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
ABSOLUTE MAXIMUM RATINGS
This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however,
normal precautions should be taken to avoid application of any voltage greater than maximum rated voltages to these high-
impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any
magnetic field more intense than the maximum field intensity specified in the maximum ratings.
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to
recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 1
Table 3 – Absolute Maximum Ratings
Symbol Parameter
Temp Range
Package
Value
Unit
VDD
VIN
Supply voltage 2
-
-
-0.5 to 4.0
V
Voltage on any pin 2
Output current per pin
Package power dissipation 3
-
-
-
-0.5 to VDD + 0.5
V
mA
W
-
IOUT
PD
-
20
Note 3
0.600
Commercial
Industrial
-
-
-
-
-10 to 85
-45 to 95
-45 to 110
-45 to 130
TBIAS
Temperature under bias
°C
Extended
AEC Q-100 Grade 1
Tstg
Storage Temperature
-
-
-
-55 to 150
260
°C
°C
Lead temperature during solder (3
minute max)
TLead
-
Commercial
TSOP2, BGA
BGA
2,000
2,000
10,000
2,000
8,000
8,000
10,000
8,000
Maximum magnetic field during
write
Industrial, Ex-
tended
Hmax_write
A/m
A/m
TSOP2
AEC-Q100 Grade 1
Commercial
TSOP2
TSOP2, BGA
BGA
Maximum magnetic field during
read or standby
Industrial, Ex-
tended
Hmax_read
TSOP2
AEC-Q100 Grade 1
TSOP2
Notes appear on the next page.
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
Notes: for MR0A16A Absolute Maximum Ratings:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted
to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability.
2. All voltages are referenced to VSS.
3. Power dissipation capability depends on package characteristics and use environment.
OPERATING CONDITIONS
Table 4 – Operating Conditions
Symbol
Parameter
Temp Range
Min
Typical
Max
Unit
VDD
Power supply voltage 1
All
3.0
3.3
3.6
V
VWI
VIH
VIL
Write inhibit voltage
Input high voltage
Input low voltage
All
All
All
2.5
2.2
2.7
3.0 1
VDD + 0.3 2
0.8
V
V
V
-
-
-0.5 3
Commercial
Industrial
0
70
85
-40
-40
-40
TA
Ambient Temperature under bias
°C
Extended
105
125
4
AEC Q-100 Grade 1
Notes:
1. There is a 2 ms startup time once VDD exceeds VDD,(min). See Power Up and Power Down Sequencing below.
2. VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
3. VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
4. AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2 years out of 20 years life.)
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
Power Up and Power Down Sequencing
The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds
VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory
power supplies to stabilize.
The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and
remain high for the startup time. In most systems, this means that these signals should be pulled up with a
resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and
W should hold the signals high with a power-on reset signal for longer than the startup time.
During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be
observed when power returns above VDD(min)
.
Figure 3 – Power Up and Power Down Timing
VDD
V
WI
BROWNOUT or POWER LOSS
2 ms
2 ms
STARTUP
RECOVER
NORMAL
OPERATION
NORMAL
OPERATION
READ/WRITE
INHIBITED
READ/WRITE
INHIBITED
VIH
VIH
E
W
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
DC CHARACTERISTICS
Table 5 – DC Characteristics
Symbol
Parameter
Condition
Min
Max
Unit
Ilkg(I)
Input leakage current
All
-
1
μA
Ilkg(O)
Output leakage current
Output low voltage
All
-
-
1
μA
V
IOL = +4 mA
IOL = +100 μA
IOH = -4 mA
0.4
VSS + 0.2
-
VOL
2.4
VOH
Output high voltage
V
IOH = -100 μA
VDD - 0.2
Table 6 – Power Supply Characteristics
Symbol
Parameter
Condition
Temp Range Typical
Max
Unit
AC active supply current
- read modes 1
IDDR
IOUT= 0 mA, VDD= max
All
55
80
mA
Commercial
Industrial
Extended
105
105
105
105
155
165
165
165
AC active supply current
- write modes1
IDDW
VDD= max
mA
AEC-Q100
Grade 1
VDD= max, E = VIH
ISB1
AC standby current
All
18
9
28
12
mA
mA
No other restrictions on other
inputs
E ≥ VDD - 0.2 V and VIn ≤ VSS
0.2 V or ≥ VDD - 0.2 V
+
ISB2
CMOS standby current
VDD = max, f = 0 MHz
Notes:
1. All active current measurements are measured with one address transition per cycle and at minimum cycle time.
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
TIMING SPECIFICATIONS
Table 7 – Capacitance
Symbol Parameter 1
Typical
Max
Unit
CIn
Address input capacitance
-
6
pF
CIn
Control input capacitance
Input/Output capacitance
-
-
6
8
pF
pF
CI/O
Notes:
1. f = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.
Table 8 – AC Measurement Conditions
Parameter
Value
Unit
Logic input timing measurement reference level
Logic output timing measurement reference level
Logic input pulse levels
1.5
V
1.5
0 or 3.0
2
V
V
Input rise/fall time
ns
Output load for low and high impedance parameters
Output load for all other timing parameters
See Figure 4
See Figure 5
Figure 4 – Output Load Test Low and High
ZD= 50 Ω
Output
RL = 50 Ω
VL = 1.5 V
Figure 5 – Output Load Test All Others
3.3 V
590 Ω
Output
5 pF
435 Ω
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
Table 9 – Read Cycle Timing
Symbol
tAVAV
Parameter 1
Min
Max
-
Unit
ns
Read cycle time
35
-
tAVQV
tELQV
Address access time
Enable access time 2
35
35
15
15
-
ns
-
ns
tGLQV
tBLQV
tAXQX
tELQX
Output enable access time
-
ns
Byte enable access time
-
ns
Output hold from address change
Enable low to output active 3
Output enable low to output active 3
Byte enable low to output active 3
Enable high to output Hi-Z 3
Output enable high to output Hi-Z3
Byte high to output Hi-Z3
3
3
0
0
0
0
0
ns
-
ns
tGLQX
tBLQX
tEHQZ
tGHQZ
tBHQZ
-
ns
-
ns
15
10
10
ns
ns
ns
Notes:
1. W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be
minimized or eliminated during read or write cycles.
2. Addresses valid before or at the same time E goes low.
3. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage.
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
Figure 6 – Read Cycle 1
tAVAV
A (ADDRESS)
Q (DATA OUT)
tAXQX
Previous Data Valid
Data Valid
tAVQV
Note: Device is continuously selected (E≤VIL, G≤VIL).
Figure 7 – Read Cycle 2
tAVAV
A (ADDRESS)
E (CHIP ENABLE)
tAVQV
tELQV
tEHQZ
tELQX
G (OUTPUT ENABLE)
LB, UB (BYTE ENABLE)
tGHQZ
tGLQV
tGLQX
tBHQZ
tBLQV
tBLQX
Data Valid
Q (DATA OUT)
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
Table 10 – Write Cycle Timing 1 (W Controlled)
Symbol
tAVAV
Parameter 1
Min
35
Max
Unit
ns
Write cycle time 2
-
-
-
-
tAVWL
Address set-up time
0
ns
tAVWH
tAVWH
Address valid to end of write (G high)
Address valid to end of write (G low)
18
ns
20
ns
tWLWH
tWLEH
Write pulse width (G high)
Write pulse width (G low)
15
15
-
-
ns
ns
tWLWH
tWLEH
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
Data valid to end of write
Data hold time
10
0
-
-
ns
ns
ns
ns
ns
Write low to data Hi-Z 3
Write high to output active 3
Write recovery time
0
12
-
3
12
-
Notes:
1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
2. All write cycle timings are referenced from the last valid address to the first transition address.
3. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given
voltage or temperate, tWLQZ(max) < tWHQX(min)
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
Figure 8 – Write Cycle Timing 1 (W Controlled)
tAVAV
A (ADDRESS)
tAVWH
tWHAX
E (CHIP ENABLE)
tWLEH
tWLWH
W (WRITE ENABLE)
tAVWL
UB, LB (BYTE ENABLED)
D (DATA IN)
tDVWH
tWHDX
DATA VALID
tWLQZ
Hi -Z
Hi -Z
Q (DATA OUT)
tWHQX
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
Table 11 – Write Cycle Timing 2 (E Controlled)
Symbol
Parameter 1
Min
Max
Unit
tAVAV
Write cycle time 2
35
-
ns
tAVEL
tAVEH
tAVEH
Address set-up time
0
-
-
-
ns
ns
ns
Address valid to end of write (G high)
Address valid to end of write (G low)
18
20
tELEH
tELWH
tELEH
tELWH
Enable to end of write (G high)
Enable to end of write (G low) 3
15
15
-
-
ns
ns
tDVEH
tEHDX
tEHAX
Data valid to end of write
Data hold time
10
0
-
-
-
ns
ns
ns
Write recovery time
12
Notes:
1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
2. All write cycle timings are referenced from the last valid address to the first transition address.
3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the
same time or before W goes high, the output will remain in a high-impedance state.
Figure 9 – Write Cycle Timing 2 (E Controlled)
tAVAV
A (ADDRESS)
tEHAX
tAVEH
tELEH
E (CHIP ENABLE)
tAVEL
tELWH
W (WRITE ENABLE)
UB, LB (BYTE ENABLE)
D (DATA IN)
tEHDX
tDVEH
Data Valid
Hi-Z
Q (DATA OUT)
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
Table 12 – Write Cycle Timing 3 (LB/UB Controlled)
Symbol
Parameter 1
Min
Max
Unit
tAVAV
Write cycle time 2
35
-
ns
tAVBL
Address set-up time
0
-
-
-
ns
ns
ns
Address valid to end of write (G high)
Address valid to end of write (G low)
18
20
tAVBH
tBLEH
tBLWH
tBLEH
tBLWH
Write pulse width (G high)
Write pulse width (G low)
15
15
-
-
ns
ns
tDVBH
tBHDX
tBHAX
Data valid to end of write
Data hold time
10
0
-
-
-
ns
ns
ns
Write recovery time
12
Notes:
1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
Wgoes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must
remain in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals must have no
more than 2 ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in
a subsequent cycle is the same as the minimum cycle time allowed for the device.
2. All write cycle timings are referenced from the last valid address to the first transition address.
Figure 10 – Write Cycle Timing 3 (UB/LB Controlled)
tAVAV
A (ADDRESS)
tAVEH
tBHAX
E (CHIP ENABLE)
W (WRITE ENABLE)
tAVBL
tBLEH
tBLWH
UB, LB (BYTE ENABLED)
D (DATA IN)
tDVBH
Data Valid
tBHDX
Hi -Z
Hi -Z
Q (DATA OUT)
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
ORDERING INFORMATION
Table 13 – Part Numbering System
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
Table 14 – MR0A16A Ordering Part Numbers
Temp Grade
Temp
Package
Shipping
Tray
Ordering Part Number
MR0A16AYS35
44-TSOP2
Tape and Reel
Tray
MR0A16AYS35R
MR0A16AMA35
MR0A16AMA35R
MR0A16ACYS35
MR0A16ACYS35R
MR0A16ACMA35
MR0A16ACMA35R
MR0A16AVYS35
MR0A16AVYS35R
MR0A16AVMA35
MR0A16AVMA35R
MR0A16AMYS35
MR0A16AMYS35R
Commercial
0 to +70 °C
48-BGA
Tape and Reel
Tray
44-TSOP2
Tape and Reel
Tray
Industrial
-40 to +85 °C
48-BGA
44-TSOP2
48-BGA
Tape and Reel
Tray
Tape and Reel
Tray
Extended
-40 to +105 °C
-40 to 125 °C
Tape and Reel
Tray
AEC-Q100 Grade 1
44-TSOP2
Tape and Reel
18
Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
PACKAGE OUTLINE DRAWINGS
Figure 11 – 44-pin TSOP2
Notes:
1. Dimensions and tolerances per ASME
Y14.5M - 1994.
2. Dimensions in Millimeters.
3. Dimensions do not include mold protru-
sion.
4. Dimension does not include DAM bar
protrusions.
5. DAM Bar protrusion shall not cause the
lead width to exceed 0.58.
19
Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
Figure 12 – 48-ball BGA Package Outline
20
Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
REVISION HISTORY
Description of Change
Date
Revision
0
1
2
Jun 18, 2007
Sept 21, 2007
Nov 12, 2007
Initial Advanced Information Release
Table 6, Applied Values to TBD’s in IDD Specifications
Table 2, Changed IDDA to IDDR or IDDW
Reformat Datasheet for EverSpin, Add BGA Packaging Information, Add Tape & Reel Part
Numbers, Add Power Sequencing Info, Correct IOH spec of VOH to -100 uA, Correct ac Test
Conditions.
3
Sep 12, 2008
4
5
Feb 28, 2011
Dec 9, 2011
Add TSOPII Lead Cross-Section, Add Production Note. Converted to new document format.
Figure 2.1 cosmetic update. Figure 5.2 BGA package outline drawing revised for ball size.
Updated logo and contact information.
Revised Table 1 and Figure 1 to be correct for x16 device. Revised magnetic immunity
ratings for TSOP2 Industrial Grade. Revised figure 3. Complete document reformat and
restructure.
6
7
8
August 6, 2012
October 14,
2013
Added AEC-Q100 Grade 1 product option.
February 19,
2015
Revised package outline for BGA. Ball size to 0.25 / 0.35 mm.
8.1
8.2
8.3
May 19, 2015
June 11, 2015
Revised contact information on Contact Us page.
Correction to Japan Sales Office telephone number.
March 23, 2018 Revised contact information on Contact Us page.
21
Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
MR0A16A
HOW TO CONTACT US
Everspin Technologies, Inc.
How to Reach Us:
Home Page:
Information in this document is provided solely to enable system and
software implementers to use Everspin Technologies products. There are
no express or implied licenses granted hereunder to design or fabricate any
integrated circuit or circuits based on the information in this document.
Everspin Technologies reserves the right to make changes without further
notice to any products herein. Everspin makes no warranty, representa-
tion or guarantee regarding the suitability of its products for any particular
purpose, nor does Everspin Technologies assume any liability arising out of
the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or inci-
dental damages. “Typical”parameters, which may be provided in Everspin
Technologies data sheets and/or specifications can and do vary in differ-
ent applications and actual performance may vary over time. All operating
parameters including “Typicals”must be validated for each customer ap-
plication by customer’s technical experts. Everspin Technologies does not
convey any license under its patent rights nor the rights of others. Everspin
Technologies products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other ap-
plication in which the failure of the Everspin Technologies product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Everspin Technologies products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Everspin Tech-
nologies and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even
if such claim alleges that Everspin Technologies was negligent regarding
the design or manufacture of the part. Everspin™ and the Everspin logo are
trademarks of Everspin Technologies, Inc.
www.everspin.com
World Wide Information Request
WW Headquarters - Chandler, AZ
5670 W. Chandler Blvd., Suite 100
Chandler, Arizona 85226
Tel: +1-877-480-MRAM (6726)
Local Tel: +1-480-347-1111
Fax: +1-480-347-1175
support@everspin.com
orders@everspin.com
sales@everspin.com
Europe, Middle East and Africa
Everspin Europe Support
support.europe@everspin.com
Japan
Everspin Japan Support
support.japan@everspin.com
Asia Pacific
Everspin Asia Support
support.asia@everspin.com
All other product or service names are the property of their respective owners.
Copyright © Everspin Technologies, Inc. 2018
Filename:
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Copyright © 2018 Everspin Technologies
MR0A16A Rev. 8.3 3/2018
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