EM669325BG-7.5G [ETRON]
4M x 32 Low Power SDRAM (LPSDRAM); 4M ×32低功耗SDRAM （ LPSDRAM ）
| 型号： | EM669325BG-7.5G |
| 厂家： | 
ETRON TECHNOLOGY, INC. |
| 描述： | 4M x 32 Low Power SDRAM (LPSDRAM) |
| 文件： | 总51页 (文件大小：598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Et r on Tech
EM669325
4M x 32 Low Power SDRAM (LPSDRAM)
Preliminary (Rev 0.6 Sep./2003)
Features
4096 refresh cycles/64ms
Single 3.0V, or 3.3V power supply
Interface: LVTTL
•
•
•
•
Clock rate: 133/125/100 MHz
Fully synchronous operation
Internal pipelined architecture
Four internal banks (1M x 32bit x 4bank)
Programmable Mode
•
•
•
•
•
Package : 90 ball-FBGA, 11x13mm, Lead Free
Ordering Information
- CAS# Latency: 1, 2 & 3
Part Number
Frequency
Package
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential & Interleave
- Burst-Read-Single-Write
Burst stop function
Individual byte controlled by DQM0-3
Auto Refresh and Self Refresh
EM669325BG-7.5G(*)
EM669325BG-8G(*)
EM669325BG-1H/LG(*)
133MHz
125MHz
100MHz
11x13 BGA
11x13 BGA
11x13 BGA
•
•
•
(*) : G indicates Lead free package
Pin Assignment : Top View
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DQ26
DQ28
VSSQ
VSSQ
VDDQ
VSS
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
VSS
VSSQ
DQ25
DQ30
NC
VDD
VDDQ
DQ22
DQ17
NC
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
DQ21
DQ19
VDDQ
VDD1Q
VSSQ
VDD
A3
A2
G
H
J
A1
A4
A6
A10
A7
A8
NC
NC
BA1
A11
CLK
DQM1
VDDQ
VSSQ
VSSQ
DQ11
DQ13
CKE
NC
A9
BA0
CS#
RAS#
DQM0
VSSQ
VDDQ
VDDQ
DQ4
K
L
NC
CAS#
VDD
DQ6
DQ1
VDDQ
VDD
WE#
DQ7
DQ8
VSS
DQ9
DQ14
VSSQ
VSS
M
DQ10
DQ12
VDDQ
DQ15
DQ5
DQ3
N
P
VSSQ
DQ0
DQ2
R
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
Et r on Tech
EM669325
4M x 32 LPSDRAM
Overview
The EM669325 SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is
internally configured as a quad 1M x 32 DRAM with a synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the 1M x 32 bit banks is organized as 4096 rows by 256
columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which is then followed by a Read or Write command.
The EM669325 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy
to use.
By having a programmable mode register, the system can choose the most suitable modes to maximize
its performance. These devices are well suited for applications requiring high memory bandwidth.
Block Diagram
Column
Decoder
4096
X 256 X 32
CELL ARRAY
(BANK #0)
Sense
Amplifier
CO N T R OL
S IG N A L
GE N ER A T OR
CL K
CKE
CLO CK
BUFFER
Sense
Amplifier
CS #
4096X 256
CELL ARRAY
(BANK #1)
X 32
CO M M A ND
DECODER
RA S#
CA S#
WE#
M O D E
R E G IS T E R
Column
Decoder
CO LU MN
COUN TER
A 1 0 /A P
Column
Decoder
4096
CELL ARRAY
(BANK #2)
X 256 X 32
ADDRESS
BUFFER
A 0
A 9
A 1 0
A 1 1
B A 0
B A 1
Sense
Amplifier
REFRESH
COUN TER
Sense
Amplifier
DQ
4096
X 256 X 32
BUFFER
CELL ARRAY
(BANK #3)
DQ 0
D Q 3 1
Column
Decoder
D Q M 0 ~3
Preliminary
2
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Pin Descriptions
Table 1. Pin Details of 4Mx32 LPSDRAM
Symbol Type Description
CLK Input Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls the
output registers.
CKE Input Clock Enable:
CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes
low synchronously with clock(set-up and hold time same as other inputs), the internal clock
is suspended from the next clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. When all banks are in the idle state, deactivating the clock
controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except
after the device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are disabled
during Power Down and Self Refresh modes, providing low standby power.
Input Bank Select:
BA0,
BA1
BA0 and BA1 defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. The bank address BA0 and BA1 is used
latched in mode register set.
A0-A11 Input Address Inputs:
A0-A11 are sampled during the BankActivate command (row address A0-
A11) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge)
to select one location out of the 1M available in the respective bank. During a Precharge
command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH).
The address inputs also provide the op-code during a Mode Register Set or Special Mode
Register Set command.
CS#
Input Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external
bank selection on systems with multiple banks. It is considered part of the command code.
RAS# Input Row Address Strobe:
The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS#
and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate
command or the Precharge command is selected by the WE# signal. When the WE# is
asserted "HIGH," the BankActivate command is selected and the bank designated by BS is
turned on to the active state. When the WE# is asserted "LOW," the Precharge command is
selected and the bank designated by BS is switched to the idle state after the precharge
operation.
CAS# Input Column Address Strobe:
The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of CLK.
When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by
asserting CAS# "LOW." Then, the Read or Write command is selected by asserting WE#
"LOW" or "HIGH."
WE# Input Write Enable:
The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is
used to select the BankActivate or Precharge command and Read or Write command.
Input Data Input/Output Mask: Data Input Mask:
DQM0 -
DQM3
DM0-DM3 are byte specific. Input data is
masked when DM is sampled HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2
masks DQ23-DQ16, DM1 masks DQ15-DQ8, and DM0 masks DQ7-DQ0.
Data I/O:
DQ0- Input/
The DQ0-31 input and output data are synchronized with the positive edges of
DQ31 Output CLK. The I/Os are byte-maskable during Reads and Writes.
No Connect:
NC
-
These pins should be left unconnected.
DQ Power:
VDDQ Supply
Provide isolated power to DQs for improved noise immunity.
Preliminary
3
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
Provide isolated ground to DQs for improved noise immunity.
4M x 32 LPSDRAM
DQ Ground:
VSSQ Supply
VDD Supply
VSS Supply
Power Supply:
Ground
+3.0V 0.3V, or +3.3V 0.3V
Preliminary
4
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State
Idle(3)
Any
CKEn-1 CKEn DQM(6) BS
0,1
A
A , A CS# RAS# CAS# WE#
10 11 9-0
BankActivate
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
V
Row address
L
L
L
L
L
L
L
H
H
H
L
H
L
L
L
L
BankPrecharge
PrechargeAll
V
X
V
V
L
H
L
X
X
Any
L
Active(3)
Active(3)
H
H
Write
Column
address
(A0 ~ A7)
Write and AutoPrecharge
H
L
Active(3)
Active(3)
H
H
X
X
X
X
V
V
L
L
L
H
H
L
L
H
H
Read
Column
address
(A0 ~ A7)
Read and Autoprecharge
H
Mode Register Set
No-Operation
Idle
Any
Active(4)
H
H
H
H
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
OP code
L
L
L
H
H
X
L
L
H
H
X
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Burst Stop
L
Device Deselect
AutoRefresh
Any
H
L
X
H
H
X
H
X
H
X
H
X
X
H
X
X
Idle
SelfRefresh Entry
SelfRefresh Exit
Idle
L
L
L
Idle
(SelfRefresh)
H
H
L
X
H
X
H
X
H
X
X
H
X
X
X
H
X
H
X
H
X
X
H
X
X
Clock Suspend Mode Entry
Power Down Mode Entry
Active
Any(5)
Active
H
H
L
L
X
X
X
X
X
X
X
X
H
L
H
L
Clock Suspend Mode Exit
Power Down Mode Exit
L
L
H
H
X
X
X
X
X
X
X
X
X
H
L
Any
(PowerDown)
Data Write/Output Enable
Data Mask/Output Disable
Active
Active
H
H
X
X
L
X
X
X
X
X
X
X
X
H
Note:
1. V = Valid, X = Don't care, L = Logic low, H = Logic high
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. DQM0-3
Preliminary
5
Rev 0.6
Sep. 2003
Et r on Tech
Commands
EM669325
4M x 32 LPSDRAM
1
BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BA 0,1= Bank, A0-A11 = Row Address)
The BankActivate command activates the idle bank designated by the BA0,1 (Bank Select)
signal. By latching the row address on A0 to A11 at the time of this command, the selected row
access is initiated. The read or write operation in the same bank can occur after a time delay of
tRCD(min.) from the time of bank activation. A subsequent BankActivate command to a different row
in the same bank can only be issued after the previous active row has been precharged (refer to the
following figure). The minimum time interval between successive BankActivate commands to the
same bank is defined by tRC(min.). The SDRAM has four internal banks on the same chip and shares
part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of
the four banks. tRRD(min.) specifies the minimum time required between activating different banks.
After this command is used, the Write command and the Block Write command perform the no mask
write operation.
T0
T1
T2
T3
Tn+3
Tn+4
Tn+5
Tn+6
CLK
..............
..............
Bank A
Bank A
Bank B
Bank A
ADDRESS
Row Addr.
Col Addr.
Row Addr.
Row Addr.
RAS# - RAS# delay time (tRRD)
NOP
RAS# - CAS# delay (tRCD)
NOP
R/W A with
AutoPrecharge
Bank A
Activate
Bank B
Activate
Bank A
Activate
..............
COMMAND
NOP
NOP
RAS# Cycle time (tRC)
AutoPrecharge
Begin
: "H" or "L"
BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3)
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BA0,1 = Bank, A10 = "L", A0-A9, A11 = Don't care)
2
The BankPrecharge command precharges the bank disignated by BA0,1 signal. The
precharged bank is switched from the active state to the idle state. This command can be asserted
anytime after tRAS(min.) is satisfied from the BankActivate command in the desired bank. The
maximum time any bank can be active is specified by tRAS(max.). Therefore, the precharge function
must be performed in any active bank within tRAS(max.). At the end of precharge, the precharged
bank is still in the idle state and is ready to be activated again.
3
4
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BA0,1 = Don’t care, A10 = "H", A0-A9, A11 = Don't care)
The PrechargeAll command precharges all the four banks simultaneously and can be issued
even if all banks are not in the active state. All banks are then switched to the idle state.
Read command
(RAS# = "H", CAS# = "L", WE# = "H", BA0,1 = Bank, A10 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent data-
out element will be valid by the next positive clock edge (refer to the following figure). The DQs go
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).
Preliminary
6
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A
DOUT A
DOUT A
DOUT A
3
CAS# latency=2
0
1
2
t
, DQ's
CK2
DOUT A
DOUT A
DOUT A
DOUT A
3
CAS# latency=3
, DQ's
0
1
2
t
CK3
Burst Read Operation(Burst Length = 4, CAS# Latency = 2, 3)
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier
(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function
may be interrupted by a subsequent Read or Write command to the same bank or the other active
bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll
command to the same bank too. The interrupt coming from the Read command can occur on any
clock cycle following a previous Read command (refer to the following figure).
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=2
DOUT A
DOUT B
DOUT B
DOUT B
DOUT B
3
0
0
1
2
t
, DQ's
CK2
CAS# latency=3
, DQ's
DOUT A
DOUT B
DOUT B
DOUT B
DOUT B
3
0
0
1
2
t
CK3
Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from
a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write
command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a
single cycle with high-impedance on the DQ pins must occur between the last read data and the
Write command (refer to the following three figures). If the data output of the burst read occurs at the
second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the
Write command to avoid internal bus contention.
Preliminary
7
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
DQ's
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
DINB
NOP
NOP
DOUT A
0
DINB
DINB
2
0
1
Must be Hi-Z before
the Write Command
: "H" or "L"
Read to Write Interval (Burst Length
4, CAS# Latency = 3)
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
1 Clk Interval
DQM
BANKA
ACTIVATE
READ A
COMMAND
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=2
, DQ's
DIN A
0
DIN A
DIN A
DIN A
3
t
1
2
CK2
: "H" or "L"
Read to Write Interval (Burst Length 4, CAS# Latency = 2)
≥
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
READ A
COMMAND
NOP
NOP
NOP
WRITE B
DIN B
NOP
NOP
NOP
CAS# latency=2
DIN B
1
DIN B
DIN B
3
t
, DQ's
0
2
CK2
: "H" or "L"
Read to Write Interval (Burst Length 4, CAS# Latency = 2)
≥
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
Preliminary
8
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank,
Col A
Bank,
Row
ADDRESS
Bank(s)
tRP
READ A
NOP
NOP
NOP
COMMAND
NOP
NOP
Precharge
NOP
Activate
CAS# latency=2
DOUT A
DOUT A
2
DOUT A
DOUT A
0
1
3
t
, DQ's
CK2
CAS# latency=3
, DQ's
DOUT A
DOUT A
2
DOUT A
DOUT A
0
1
3
t
CK3
Read to Precharge (CAS# Latency = 2, 3)
5
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after
the read operation. Once this command is given, any subsequent command cannot occur within a
time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this
command and the auto precharge function is ignored.
6
Write command
(RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
DIN
A
DIN A
DIN
A
DIN A
3
don't care
DQ0 - DQ3
0
1
2
The first data element and the write
Extra data is masked.
are registered on the same clock edge.
Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
Preliminary
9
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
W RITE A
WRITE B
NOP
NOP
NOP
1 Clk Interval
DIN DIN B
A
DIN B
DIN B
DIN B
3
DQ's
0
0
1
2
Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
CAS# latency=2
NOP
WRITE A
READ B
don't care
don't care
NOP
NOP
NOP
DOUT B
DOUT B
DIN A
0
DOUT B
DOUT B
1
2
3
0
t
, DQ's
CK2
CAS# latency=3
, DQ's
DOUT B
DOUT B
DOUT B
DOUT B
3
DIN A
0
don't care
t
0
1
2
CK3
Input data must beremoved from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Input data for the write is masked.
Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
m
precharge function should be issued cycles after the clock edge in which the last data-in element
m
is registered, where
equals tWR/tCK rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
t
RP
COMMAND
WRITE
Precharge
BANK (S)
NOP
NOP
Activate
ROW
NOP
NOP
BANK
COL n
ADDRESS
DQ
t
WR
DIN
n
DIN
n + 1
: don't care
Note:
The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
Preliminary
10
Rev 0.6
Sep. 2003
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EM669325
4M x 32 LPSDRAM
7
Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.
8
Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", BS0,1 and A11-A0 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The default
values of the Mode Register after power-up are undefined; therefore this command must be issued
at the power-up sequence. The state of pins BA0,1 and A11~A0 in the same cycle is the data written
to the mode register. One clock cycle is required to complete the write in the mode register (refer to
the following figure). The contents of the mode register can be changed using the same command
and the clock cycle requirements during operation as long as all banks are in the idle state.
T0
T 1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CK2
CKE
CS#
Clock min.
RAS#
CAS#
WE#
Address Key
ADDR.
DQM
tRP
Hi-Z
DQ
Mode Register
Set Command
PrechargeAll
Any
Command
Mode Register Set Cycle (CAS# Latency = 2, 3)
Preliminary
11
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Mode Resistor Bitmap
BA1
0
BA0
0
A11
0
A10
0
A9
W.B.L
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
TM
CAS Latency
Burst Length
A9
0
1
Length
Burst
Single Bit
A8
0
1
A7
0
0
Mode
A3
0
1
Type
Sequential
Interleave
Normal
Reserved
Reserved
0
1
A6
0
0
0
0
A5
0
0
1
1
A4
0
1
0
1
CAS Latency
Reserved
1 clock
2 clocks
3 clocks
Reserved
A2
A1
0
0
1
1
A0
0
1
0
1
Burst Length
0
0
0
0
1
1
2
4
8
1
0
1
1
1
Full Page (Sequential)
All other Reserved
All other Reserved
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Start Address
Burst Length
2
Sequential
Interleave
A2
X
X
X
X
X
X
0
A1
X
X
0
0
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
4
1
0
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0
0
0
1
0
1
8
1
0
1
0
1
1
1
1
Preliminary
12
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
9
No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS#
is Low). This prevents unwanted commands from being registered during idle or wait states.
10 Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst ends after a delay equal to the CAS# latency (refer to the following figure). The
termination of a write burst is shown in the following figure.
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
NOP
NOP
NOP
COMMAND
NOP
NOP
Burst Stop
DOUT A
NOP
NOP
Theburst ends after a delay equal totheCAS# latency.
CAS# latency=2
DOUT A
DOUT A
DOUT A
3
0
1
2
t
, DQ's
CK2
CAS# latency=3
, DQ's
DOUT A
DOUT A
DOUT A
DOUT A
3
0
1
2
t
CK3
Termination of a Burst Read Operation (Burst Length
4, CAS# Latency = 2, 3)
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
WRITE A
NOP
Burst Stop
don't care
NOP
NOP
CAS# latency= 2, 3
DQ's
DIN A
DIN A
0
DIN A
1
2
Input data for the Write is masked.
Termination of a Burst Write Operation (Burst Length = X, CAS# Latency = 1, 2, 3)
Preliminary
13
Rev 0.6
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EM669325
4M x 32 LPSDRAM
11 Device Deselect command (CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
to the No Operation command.
12 AutoRefresh command
(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", BA0,1 = “Don‘t care, A0-A11 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 4096 times within 64ms. The time required to complete the auto
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, all banks need to
be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP(min), must be met before successive auto refresh operations are
performed.
13 SelfRefresh Entry command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A11 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by
restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
14 SelfRefresh Exit command
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
This command is used to exit from the SelfRefresh mode. Once this command is registered,
NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 4096 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.
15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command
performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are
turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown
state longer than the refresh period (64ms) since the command does not perform any refresh
operations.
16 Clock Suspend Mode Exit / PowerDown Mode Exit command
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from
the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the
PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active
state. tPDE(min.) is required when the device exits from the PowerDown mode. Any subsequent
commands can be issued after one clock cycle from the end of this command.
17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")
During a write cycle, the DQM signal functions as a Data Mask and can control every word of
the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is
also used for device selection, byte selection and bus control in a memory system.
Preliminary
14
Rev 0.6
Sep. 2003
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EM669325
4M x 32 LPSDRAM
Absolute Maximum Rating
Symbol
VIN, VOUT
VDD, VDDQ
TOPR
Item
Input, Output Voltage
Rating
Unit
V
- 1.0 ~ +4.6
-1.0 ~ +4.6
-25 ~ +85
- 55~ +150
260
Power Supply Voltage
Operating Temperature
Storage Temperature
V
C
C
C
°
°
°
TSTG
TSOLDER
PD
Soldering Temperature (10s)
Power Dissipation
1.0
W
IOUT
Short Circuit Output Current
50
mA
Note:
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
Recommended D.C. Operating Conditions (Ta = -25~85°C)
Parameter/ Condition
DRAM Core Supply VOLTAGE
I/O Supply Voltage
Symbol
VDD
VDDQ
VIH
Min
2.7
2.7
2.0
-0.3
2.4
Typ
3.0
3.0
2.5
0
Max
Unit
V
Note
1
3.6
3.6
V
1
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Data Output High (Logic 1) Voltage
Data Output High (Logic 1) Voltage
Input Leakage Current
VDDQ+0.3
V
1
VIL
0.8
-
V
1
VOH
VOL
IIL
-
V
1,2,4
1,3,5
-
-
0.4
1.5
V
-1.5
µA
( 0V VIN VDD, All other pins not under
test = 0V )
Note:
1
All voltages are referenced to VSS.
2
3
4
5
IOUT = - 2.0mA
IOUT = + 2.0mA
VIH (max) = 5.6V AC. The overshoot voltage duration is
5ns.
5ns.
VIL (min) =-2.0V AC. The undershoot voltage duration is
Capacitance (VDD = 2.5V, f = 1MHz, Ta = 25°C)
Symbol
CI
Parameter
Input Capacitance
Input/Output Capacitance
Min.
Max.
Unit
pF
5
8
CI/O
6
pF
Note:
These parameters are periodically sampled and are not 100% tested.
Preliminary
15
Rev 0.6
Sep. 2003
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EM669325
4M x 32 LPSDRAM
D.C. CHARACTERISTICS (Ta = -25~85°C)
- 75/8/1H/1L
Max.
Description/Test condition
Symbol
Unit
Operating Current
tRC ≥ tRC(min), Outputs Open, Input
signal one transition per one cycle
1 bank
operation
ICC1
150/145/140/130
Precharge Standby Current in power down mode
tCK = 15ns, CKE ≤ VIL(max)
Precharge Standby Current in power down mode
tCK = ∞, CKE ≤ VIL(max)
ICC2P
2
2
ICC2PS
Precharge Standby Current in non-power down mode
tCK = 15ns, CS# ≥ VIH(min), CKE ≥ VIH
Input signals are changed once during 30ns.
Precharge Standby Current in non-power down mode
tCK = ∞, CLK ≤ VIL(max), CKE ≥ VIH
Active Standby Current in power down mode
CKE ≤ VIL(max), tCK = 15ns
Active Standby Current in power down mode
CKE & CLK ≤ VIL(max), tCK = ∞
Active Standby Current in non-power down mode
CKE ≥ VIH(min), CS# ≥ VIH(min), tCK = 15ns
Active Standby Current in non-power down mode
CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞
Operating Current (Burst mode)
ICC2N
30
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
12
6
mA
6
60
50
220/210/180/170
250/240/220/210
800
tCK =tCK(min), Outputs Open, Multi-bank interleave
Refresh Current
tRC ≥ TrC(min)
Self Refresh Current
ICC5
ICC6
uA
CKE ≤ 0.2V
Preliminary
16
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 2.7V~3.6V, Ta = -25~85°C) (Note: 1, 2, 3, 4)
-
75/8/1H/1L
Symbol
A.C. Parameter
Unit
Note
Min.
Max.
tRC
tRCD
tRP
Row cycle time( same bank )
65/66/70/84
20/20/20/24
20/20/20/24
5
5
RAS# to CAS# delay (same bank)
Precharge to refresh / row activate command
(same bank)
5
5
ns
ns
tRRD
Row activate to row active delay
(different banks)
15/16/20/20
45/46/50/60
tRAS
Row activate to percharge time
(same bank)
100,000
5
5
tRDL
tCK1
tCK2
tCK3
Last data in to row precharge
10
Clock cycle time
CL* = 1
CL* = 2
CL* = 3
- /- /- /25
10/10/10/12
7.5/8/10/10
2.5/2.7/3/3
2.5/2.7/3/3
Clock high time
Clock low time
tCH
tCL
ns
6
5
tAC1
tAC2
tAC3
tCCD
tOH
Access time from CLk
(positive edge)
CL* = 1
CL* = 2
CL* = 3
- /- / -/18
6/6/6/6
5.5/5.6/6/6
CAS# to CAS# Delay time
Data output hold time
1
2
1
CLK
ns
5
5
5
tLZ
Data output low impedance
Data output high impedance
tHZ1
tHZ2
tHZ3
TIS
CL* = 1
CL* = 2
CL* = 3
-/- /-/18
6/6/6/6
4
5.5/5.6/6/6
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
Refresh period (4096 refresh cycles)
2.5/2.7/3/3
1
6
6
tIH
ns
tREF
64
ms
*CL is CAS# Latency.
Preliminary
17
Rev 0.6
Sep. 2003
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4M x 32 LPSDRAM
Note:
1
2
Power-up sequence is described in Note 7.
A.C. Test Conditions
LVTTL Interface
Reference Level of Output Signals
1.4V/1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels (VIH/VIL)
2.4V/0.4V
1ns
Transition Time (Rise and Fall) of Input Signals
Reference Level of Input Signals
1.4V
3.0V
1.4V
50Ω
1.2kΩ
50Ω
Z0=
Output
Output
30pF
30pF
870Ω
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
3. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed
slope (1 ns).
4. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
5. If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
6. Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
should be added to the parameter.
7. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state
and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time.
2) After power-up, a pause of 200µ seconds minimum is required. Then, it is recommended that DQM
is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.
Preliminary
18
Rev 0.6
Sep. 2003
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4M x 32 LPSDRAM
Timing Waveforms
Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCL
tCK2
tCH
tIS
tIH
Begin AutoPrecharge
Bank A
Begin AutoPrecharge
Bank B
CKE
CS#
tIS
tIS
RAS#
CAS#
WE#
BA0,1
tIH
CAx
tIS
ADDR.
DQM
RBx
CBx
RAy
RAz
RBx
CAy
RBy
tDAL
tRCD
tIS
tRC
Ax0 Ax1 Ax2
tWR
tRP
tRRD
tIH
Hi-Z
DQ
Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3
Activate
Writewith
Activate Writewith
Activate
Write
Comm and
Bank A
Precharge Activate
Comm and Comm and
Activate
Command
Bank B
Comm and AutoPrecharge Comm andAutoPrecharge Comm and
Bank A
Command
Bank A
Bank B
Comm and
Bank B
Bank A
Bank A
Bank A
Preliminary
19
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10
T 11 T12
T13
CLK
CKE
tCK2
tIS
tCH tCL
Begin AutoPrecharge
Bank B
tIH
tIH
tIS
CS#
RAS#
CAS#
WE#
BA0,1
A10
tIH
RBx
RBx
RAx
RAx
RAy
RAy
tIS
A0-A11
CBx
CAx
tRRD
tRAS
tRC
tHZ
DQM
tAC2
tLZ
tAC2
Ax0
tRP
tRCD
Hi-Z
Bx0
Bx1
DQ
Ax1
tHZ
tOH
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read with
Precharge
Command
Bank A
Activate
Command
Bank A
Auto Precharge
Command
Bank B
Preliminary
20
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Sep. 2003
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EM669325
4M x 32 LPSDRAM
Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A11
DQM
RAx
CAx
tRC
tRC
tRP
Ax0
Ax2
Ax3
Ax1
DQ
Read
Command
Bank A
PrechargeAll AutoRefresh
AutoRefresh
Command
Activate
Command
Bank A
Comm and
Comm and
Preliminary
21
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Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 4. Power on Sequene and Auto Refresh (CBR)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
High level
is reauired
Minimum of 2 Refresh Cycles are required
CS#
RAS#
CAS#
WE#
BA0,1
A10
Address Key
A0-A11
DQM
DQ
tRP
tRC
Hi-Z
PrechargeALL
Command
1st AutoRefresh
Command
2nd Auto Refresh
Command
Any
Command
Mode Register
Set Command
Inputs must be
stable for 200 µs
Preliminary
22
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Sep. 2003
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EM669325
4M x 32 LPSDRAM
Figure 5. Self Refresh Entry & Exit Cycle
T0
T1
T2 T3
T4
T5
T7
T8
T9
T10 T11 T12 T13
T14 T15 T16
T17 T18
T19
T6
CLK
*Note 2
tRC(min) *Note 7
*Note 4
*Note 1
*Note 3
tPDE
CKE
CS#
tSRX
*Note 5
tIS
*Note 6
RAS#
CAS#
BA0,1
*Note 8
*Note 8
A0-A11
WE#
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Enter
SelfRefresh Exit
AutoRefresh
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
To Exit SelfRefresh Mode
5. System clock restart and be stable before returning CKE high.
6. Enable CKE and CKE should be set high for minimum time of tSRX
.
7. CS# starts from high.
8. Minimum tRC is required after CKE going high to complete SelfRefresh exit.
9. 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
Preliminary
23
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Sep. 2003
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4M x 32 LPSDRAM
Figure 6.1. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6
T
7
T8 T9 T10 T 11 T1 T13 T14 T15 T16 T17 T1 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
BA0,1
RAx
A10
A0-A11
RAx CAx
DQM
DQ
tHZ
Ax3
Hi-Z
Ax0
Ax1
Ax2
Activate
Command
Bank A
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Read
Command
Bank A
Note:
CKE to CLK disable/enable = 1 clock
Preliminary
24
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 6.2. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A11
DQM
CAx
RAx
tHZ
Hi-Z
DQ
Ax3
Ax0
Ax1
Ax2
Clock Suspend
2 Cycles
Activate
Command
Bank A
Read
Comm and
Bank A
Clock Suspend
1 Cycle
Clock Suspend
3 Cycles
Note:
CKE to CLK disable/enable = 1 clock
Preliminary
25
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Sep. 2003
Et r on Tech
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4M x 32 LPSDRAM
Figure 6.3. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T 2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK3
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
DQM
DQ
CAx
RAx
tHZ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Clock Suspend
3 Cycles
Activate
Command
Bank A
Read
Comm and
Bank A
Clock Suspend Clock Suspend
1 Cycle
2 Cycles
Note:
CKE to CLK disable/enable = 1 clock
Preliminary
26
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 7.1. Clock Suspension During Burst Write (Using CKE)
(Burst Length = 4, CAS# Latency = 1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A11
RAx CAx
DQM
DQ
DAx0
DAx1
Hi-Z
DAx2
DAx3
Activate Clock Suspend Clock Suspend
Command
Bank A
Clock Suspend
3 Cycles
1 Cycle
2 Cycles
Write
Command
Bank A
Note:
CKE to CLK disable/enable = 1 clock
Preliminary
27
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 7.2. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
A0-A11
DQM
RAx
RAx
CAx
Hi-Z
DQ
DAx1
DAx2
DAx3
DAx0
Activate
Comm and
Bank A
Clock Suspend Clock Suspend
1 Cycle 2 Cycles
Clock Suspend
3 Cycles
Write
Command
Bank A
Note:
CKE to CLK disable/enable = 1 clock
Preliminary
28
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 7.3. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK3
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A11
RAx
CAx
DQM
DQ
Hi-Z
DAx0
DAx2
DAx3
DAx1
Activate
Command
Bank A
Clock Suspend Clock Suspend
1 Cycle 2 Cycles
Write
Command
Bank A
Clock Suspend
3 Cycles
Note:
CKE to CLK disable/enable = 1 clock
Preliminary
29
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 8. Power Down Mode and Clock Mask (Burst Lenght=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
tCK2
tPDE
tIS
Valid
RAS#
CAS#
WE#
BS0,1
A10
RAx
CAx
RAx
A0~A11
DQM
tHZ
Hi-Z
Ax0
Ax1
Ax3
Ax2
DQ
ACTIVE
STANDBY
PRECHARGE
STANDBY
Activate
Command
Bank A
Read
Command
Bank A
Clock Mask
Start
Clock Mask
End
Precharge
Command
Bank A
Power Down
Mode Exit
Any
Power Down
ModeEntry
Power Down
Mode Exit
Command
Power Down
ModeEntry
Preliminary
30
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 9.1. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAz
RAw
RAw
CAw
CAy
RAz
CAz
A0~A11
DQM
CAx
Hi-Z
DQ
Aw0 Aw1 Aw2
Aw3Ax0
Ax1
Ay1Ay2 Ay3
Az1Az2 Az3
Ay0
Az0
Activate
Command
Bank A
Read
Command Comm and
Bank A Bank A
Read
Precharge
Read
Command
Command
Bank A
Bank A
Activate
Command
Bank A
Read
Comm and
Bank A
Preliminary
31
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 9.2. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAz
RAw
RAz
CAz
CAw
CAx
CAy
RAw
A0~A11
DQM
Hi-Z
DQ
Az0
Ay0
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1
Ay1 Ay2 Ay3
Az1 Az2 Az3
Activate
Read
Read
Command
Bank A
Read
Command
Bank A
Precharge Activate
Command Command
Read
Comm and
Bank A
Command Command
Bank A
Bank A
Bank A
Bank A
Preliminary
32
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 9.3. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK3
CS#
RAS#
CAS#
WE#
BA0,
1
RAz
A10
RAw
CAy
CAz
A0~A11
CAw
RAz
RAw
CAx
DQM
Az0
Hi-Z
Ay0
Aw0 Aw1 Aw2
Aw3 Ax0 Ax1
Ay1 Ay2 Ay3
DQ
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Preliminary
33
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 10.1. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBz
RBw
CBw
CBy
RBw
RBz
CBz
A0~A11
DQM
CBx
Hi-Z
DQ
DBy1 DBy2 DBy3
DBw0DBw1DBw2 DBw3 DBx0 DBx1
DBz1 DBz2 DBz3
DBy0
DBz0
Activate
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Write
Comm and
Bank B
Activate
Command
Bank B
Preliminary
34
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 10.2. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RBz
RBz
RBw
RBw
CBy
CBw
A0~A11
DQM
CBz
CBx
DBz0
Write
Hi-Z
DQ
DBz2 DBz3
DBz1
DBy0
DBw0 DBwD1Bw2 DBw3 DBx0 DBx1
DBy1
DBy2 DBy3
Activate
Write
Write
Command
Bank B
Write
Command
Bank B
Precharge Activate
Command Command
Command Command
Command
Bank B
Bank A
Bank B
Bank B
Bank B
Preliminary
35
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 10.3. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBz
RBz
RBw
RBw
CBx
CBy
CBw
A0~A11
DQM
CBz
Hi-Z
DBy0
DBz0
Write
DBz2
DQ
DBw0 DBw1DBw2 DBw3 DBx0 DBx1
DBy1 DBy2 DBy3
DBz1
Activate
Command
Bank A
Write
Command
Bank B
Write
Comm and Command
Bank B Bank B
Write
Precharge
Comm and
Bank B
Activate
Comm and
Bank B
Command
Bank B
Preliminary
36
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 11.1. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
High
CS#
RAS#
CAS#
WE#
BA0,1
RBx
RBx
RAx
RAx
RBy
RBy
A10
CBy
CBx
A0~A11
CAx
tRCD
tRP
tAC1
DQM
DQ
Hi-Z
By0
By1
By2
Bx6
Bx0
Bx1 Bx2 Bx3 Bx4 Bx5
Bx7
Ax0 Ax1 Ax2 Ax3
Ax4
Ax5 Ax6 Ax7
Activate
Precharge
Read
Command
Bank B
Precharge
Comm and
Bank A
Activate
Comm and
Bank A
Comm and
Comm and
Bank B
Bank B
Activate
Comm and
Bank B
Read
Read
Command
Bank B
Command
Bank A
Preliminary
37
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 11.2. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
RBx
RBx
A10
RAx
RAx
RBy
RBy
CBx
CAx
CBy
A0~A11
tRCD
tAC2
tRP
DQM
Bx0
Bx1
Bx2
Bx3 Bx4
Bx5 Bx6 Bx7
Ax1
Ax2Ax3
Hi-Z
DQ
Ax0
By0 By1
Ax6
Ax7
Ax4 Ax5
Activate
Command
Bank B
Read
Comm and
Bank B
Activate
Comm and
Bank A
Precharge
Activate
Command
Bank B
Read
Command
Bank B
Command
Bank B
Read
Command
Bank A
Preliminary
38
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 11.3. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBx
RAx
RAx
RBy
RBx
RBy
CAx
A0~A9
DQM
CBy
CBx
tRCD
tAC3
tRP
Hi-Z
DQ
Ax7
By0
Bx6
Bx0 Bx1 Bx2 Bx3
Bx4 Bx5
Bx7
Ax0 Ax1 Ax2
Ax3
Ax4 Ax5Ax6
Activate
Command
Bank B
Activate
Command
Bank A
Read
Comm and
Bank A
Precharge
Comm and
Bank B
Activate
Comm and
Bank B
Read
Command
Bank B
Precharge
Command
Bank A
Read
Command
Bank B
Preliminary
39
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 12.1. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAy
RAy
RAx
RBx
RBx
A0~A11
DQM
RAx
CAy
CBx
CAx
tRCD
tRP
tWR
Hi-Z
DQ
DBx7
DAx6
DAx7 DBx0 DBx1 DBx2 DBx3DBx4 DBx5 DBx6
DAy0 DAy1 DAy2
DAy3
DAx0
DAx1 DAxD2Ax3
DAx4 DAx5
Activate
Activate
Command
Bank B
Precharge
Comm and
Bank A
Precharge
Comm and
Bank B
Write
Comm and
Bank A
Command
Bank A
Write
Activate
Comm and
Bank A
Write
Command
Bank A
Comm and
Bank B
Preliminary
40
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 12.2. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAy
RBx
RAx
RAy
CAy
RBx
RAx
CAx
CBx
A0~A11
DQM
tRCD
tWR*
tRP
tWR*
Hi-Z
DQ
DBx7
DAx7 DBx0 DBx1 DBx2 DBx3 DBx4DBx5 DBx6
DAy3
DAy4
DAx6
DAy0DAy1DAy2
DAx0 DAx1 DAx2 DAx3 DAx4DAx5
Activate
Write
Activate
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank A
Write
Command Command
Bank A Bank A
Command
Bank A
Precharge
Precharge
Command
Bank B
Command
Bank A
*
tWR > tWR(min.)
Preliminary
41
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 12.3. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RBx
RAy
RAy
CAy
RAx
CAx
CBx
RBx
A0~A11
DQM
tRCD
tWR*
tRP
tWR*
Hi-Z
DQ
DAy0 DAy1 DAy2
DBx5 DBx6
Activate
DBx7
DAy3
DAx0DAx1
DAx6
DAx2 DAx3DAx4 DAx5
DAx7 DBx0 DBx1DBx2
DBx3 DBx4
Activate
Comm and
Bank A
Write
Write
Command
Bank A
Activate
Comm and
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Precharge
Comm and
Bank B
Comm and
Bank A
Command
Bank A
*
tWR > tWR(min.)
Preliminary
42
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAx CAx
CAy
CAz
A0~A11
DQM
Hi-Z
Az3
DQ
Ax0 Ax1 Ax2
Ax3
DAy0DAy1
DAy3
Az0
Az1
Read
Comm and
Bank A
The Write Data
is Maskedwith a
Zero Clock
Activate
Command
Bank A
Write
Command
Bank A
The Read Data
is Maskedwith a
Two Clock
Precharge
Command
Bank B
Read
Latency
Latency
Command
Bank A
Preliminary
43
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAx
CAx
CAz
CAy
A0~A11
DQM
Hi-Z
Az3
DQ
Ax0
Ax1
Ax2 Ax3
DAy0 DAy1
DAy3
Az0 Az1
Activate
Read
Write
The Write Data
Read
Comm and
Bank A
The Read Data
Command Comm and
Comm and is Maskedwith a
is Maskedwith a
Two Clock
Bank A
Bank A
Bank A
Zero Clock
Latency
Latency
Preliminary
44
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)
T22
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
RAx
RAx
RAx
A10
CAy
CBx
CBy
CAy
CBz
RAx
CBw
A0~A11
DQM
tRCD
tAC2
Hi-Z
Bz2 Bz3
Bz1
Ax0
Ax1 Ax2
Ax3
By0
Ay1
DQ
Bw0
Bw1
Bx0 Bx1
By1 Ay0
Bz0
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Command Command
Bank B Bank B
Read
Read
Command
Bank A
Read
Precharge
Command
Bank B
Read
Command
Bank B
Command
Bank B
Precharge
Comm and
Bank A
Preliminary
45
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 14.2. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK3
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAx
RBx
CAx RBx
CBx
CBz
CBy
CAy
A0~A11
DQM
tAC3
tRCD
Hi-Z
DQ
Bx0
Bx1
By0 By1
Bz1 Ay0
Ay2
Ax0
Ax1 Ax2
Ax3
Bz0
Ay1
Ay3
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read Prechaerge
CommanCdommand
Bank A Bank B
Activate
Command
Bank B
Preliminary
46
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RBw
CBy
CBz
CBx
CAy
RAx CAx RBw
CBw
A0~A11
tRP
tWR tRP
tRCD
DQM
DQ
tRRD
DAx0
Hi-Z
DBz2
DAx1 DAx2 DAx3 DBw0DBw1 DBx0 DBx1DBy0 DBy1 DAy0 DAy1
DBz0 DBz1
DBz3
Activate
Command
Bank A
Activate
Command
Bank B
Write
Command Comm and
Bank B Bank B
Write
Write
Write
Write
Command
Bank B
Precharge
Command
Bank B
Command Comm and
Bank B
Bank A
Precharge
Write
Command
Bank A
Comm and
Bank A
Preliminary
47
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAx
RBw
RBw
CBw
CBx
CBy
CBz
CAx
CAy
A0~A11
DQM
tWR
tRCD
tRP
tRP
tRRD
Hi-Z
DQ
DAx0
DAx1 DAx2 DAx3DBw0 DBw1DBx0
DBz2
DBx1DBy0
DBy1DAy0 DAy1 DBz0 DBz1
DBz3
Activate
Command Comm and
Bank A Bank A
Write
Activate
Comm and
Bank B
Write
Comm and Command
Bank B Bank B
Write
Write
Command Command
Bank B Bank A
Write
Write
Command
Bank B
Precharge
Command
Bank B
Precharge
Command
Bank A
Preliminary
48
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK3
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAx
RBw
CBw
CBx
CBy
CBz
CAx RBw
CAy
A0~A11
DQM
tRCD
tWR
tRP
tWR(min)
tRRD > tRRD(min)
DAx0
Hi-Z
DQ
DBz2
DAx1 DAx2 DAx3DBw0 DBw1DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1
DBz3
Activate
Command
Bank A
Activate
Command
Bank B
Write
Write
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Command Command
Bank B
Bank B
Write
Precharge
Command
Bank A
Command
Bank A
Preliminary
49
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Figure 16. Random Row Read (Interleaving Banks)
(Burst Length=2, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
High
Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto
Precharge
Bank B
Precharge
Bank A
Precharge
Bank B
Precharge
Bank A
Precharge
Bank B
Precharge
Bank A
Precharge
Bank B
Precharge
Bank A
Precharge
Bank B
Precharge
Bank A
CS#
RAS#
CAS#
WE#
BA0,1
RAu
RBx
RBu
RBw
RAw
RAx
RBz
RBv
RBv
RAv
RBy
RAy
RAz
A10
CBu RAu CAu
CAv
CBw RAw
CBx
RAx CAx
RBx
RBu
CBv
t
RAv
CAw
t
RBy CBy
RAy CAy RBz
CBz RAz
RBw
A0~A11
t
t
t
t
t
t
t
t
RP
RP
RP
RP
RP
RP
RP
RP
RP
RP
DQM
Bu0
Bu1Au0
Au1
Bv0 Bv1
Av0
Av1 Bw0 Bw1
Activate
Aw0 Aw1Bx0 Bx1
Ax0 Ax1 By0
By1 Ay0 Ay1
Bz0
DQ
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Command
Bank A
Command
Bank B
Read
Bank B
with Auto
Precharge
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Bank A
with Auto
Precharge
Bank B
with Auto
Precharge
Bank A
with Auto
Precharge
Bank B
with Auto
Precharge
Bank A
with Auto
Precharge
Bank B
with Auto
Precharge
Bank A
with Auto
Precharge
Bank B
with Auto
Precharge
Bank A
with Auto
Precharge
Bank B
with Auto
Precharge
Preliminary
50
Rev 0.6
Sep. 2003
Et r on Tech
EM669325
4M x 32 LPSDRAM
Features of the Low-Power SDRAM Package:
90-FBGA, 11mm x 13mm plastic package
9x15 ball array with 3 depopulated rows in center
0.8mm ball pitch
Low-profile, 1.2mm max height
(Ball-Side View)
6.40
0.80
11.20
0.80
13.00
5.60
6.50
3.20
5.50
11.00
= 0.45 0.05
1.40 max
0.35
All dimemsions are in mm.
Preliminary
51
Rev 0.6
Sep. 2003
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