EM636165VE-6 [ETRON]
1Mega x 16 Synchronous DRAM (SDRAM); 1Mega ×16同步DRAM （SDRAM）的
| 型号： | EM636165VE-6 |
| 厂家： | 
ETRON TECHNOLOGY, INC. |
| 描述： | 1Mega x 16 Synchronous DRAM (SDRAM) |
| 文件： | 总74页 (文件大小：767K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Et r on Tech
EM636165
1Mega x 16 Synchronous DRAM (SDRAM)
Preliminary (Rev. 1.8, 11/2001)
Features
Key Specifications
Fast access time: 4.5/5/5/5.5/6.5/7.5 ns
Fast clock rate: 200/183/166/143/125/100 MHz
Self refresh mode: standard and low power
Fully synchronous operation
Internal pipelined architecture
512K x 16 bit x 2-bank
EM636165
-5/55/6/7/7L/8/10
•
•
•
•
•
•
•
5/5.5/6/7/7/8/10 ns
tCK3 Clock Cycle time(min.)
tRAS Row Active time(max.)
tAC3 Access time from CLK(max.)
tRC Row Cycle time(min.)
30/32/36/42/42/48/60 ns
4.5/5/5/5.5/5.5/6.5/7.5 ns
48/48/54/63/63/72/90 ns
Programmable Mode registers
- CAS# Latency: 1, 2, or 3
Ordering Information
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
Individual byte controlled by LDQM and UDQM
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
1. Operating temperature : 0~70°C
Part Number
Frequency
200MHz
183MHz
166MHz
143MHz
143MHz
125MHz
100MHz
Package
EM636165TS/VE-5
EM636165TS/VE-55
EM636165TS/VE -6
EM636165TS/VE -7
EM636165TS/VE-7L
EM636165TS/VE -8
EM636165TS/VE -10
TSOP II ,VFBGA
TSOP II ,VFBGA
TSOP II ,VFBGA
TSOP II ,VFBGA
TSOP II,VFBGA
TSOP II,VFBGA
TSOP II,VFBGA
•
•
•
•
•
•
•
•
CKE power down mode
Single +3.3V 0.3V power supply
±
Interface: LVTTL
50-pin 400 mil plastic TSOP II package
60-Ball, 6.4 mm x 10.1 mm VFBGA package
(Max total package height=1.0 mm)
2. Industrial Operating temperature : -40~85°C
Part Number
Frequency
Package
EM636165TS/VE -10I
100MHz
TSOP II,VFBGA
Pin Assignment (Top View)
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
VDD
DQ 0
DQ 1
VSSQ
DQ 2
DQ 3
VDDQ
DQ 4
DQ 5
VSSQ
DQ 6
DQ 7
VDDQ
LD QM
WE#
CA S#
RA S#
CS #
A11
A10
A 0
1
2
3
4
5
6
7
8
Vss
1
2
3
4
5
6
7
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ 9
DQ 8
VDDQ
NC
UD QM
CL K
CKE
NC
A 9
A 8
D Q 0
A
B
C
D
E
F
V D D
D Q 1
D Q 2
D Q 3
D Q 5
D Q 6
D Q 7
V S S
D Q 1 5
D Q 14
D Q 13
D Q 12
D Q 10
D Q 9
V D D Q
V S S Q
D Q 4
V S S Q
V D D Q
D Q 1 1
V S S Q
V D D Q
9
V D D Q
V S S Q
N C
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
G
H
J
D Q 8
N C
N C
N C
N C
N C
N C
N C
L D Q M
U D Q M
W E #
K
L
R A S #
N C
N C
A 0
C L K
N C
A 9
C A S #
C S #
N C
C K E
A 11
A 8
M
N
A 7
A 6
A 5
A 4
A 10
A 7
A 5
A 4
A 1
A 2
A 3
VDD
P
R
A 2
A 1
A 6
A 3
V D D
V S S
Vss
Etron Technology, Inc.
No. 6, Technology Road V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
Et r on Tech
Overview
EM636165
1M x 16 SDRAM
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured
as a dual 512K x 16 bit DRAM with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the 512K x 16 bit bank is organized as 2048 rows by 256 columns by 16 bits. Read and write
accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number
of locations in a programmed sequence.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a
programmable mode register, the system can choose the most suitable modes to maximize its performance. These
devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance
PC applications.
Block Diagram
CLK
CKE
CLOCK
BUFFER
Column Decoder
2048 X 256 X 16
CELL ARRAY
(BANK #0)
CS#
CONTROL
SIGNAL
GENERATOR
RAS#
CAS#
WE#
LDQM
UDQM
COMMAND
DECODER
Sense Amplifier
COLUMN
COUNTER
DQ0
DQs Buffer
DQ15
MODE
REGISTER
A0
ADDRESS
BUFFER
A11
Sense Amplifier
REFRESH
COUNTER
2048 X 256 X 16
CELL ARRAY
(BANK #1)
Column Decoder
Preliminary
2
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Pin Descriptions
Table 1. Pin Details of EM636165
Description
Symbol
Type
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
CKE
Input
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If
CKE goes low synchronously with clock(set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state of
output and burst address is frozen as long as the CKE remains low. When both
banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device
enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are
disabled during Power Down and Self Refresh modes, providing low standby
power.
A11
Input
Input
Bank Select: A11(BS) defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
A0-A10
Address Inputs: A0-A10 are sampled during the BankActivate command (row
address A0-A10) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 256K available in the
respective bank. During a Precharge command, A10 is sampled to determine if
both banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
CS#
Input
Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
RAS#
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH," either the BankActivate command or the Precharge command is
selected by the WE# signal. When the WE# is asserted "HIGH," the
BankActivate command is selected and the bank designated by BS is turned on
to the active state. When the WE# is asserted "LOW," the Precharge command
is selected and the bank designated by BS is switched to the idle state after the
precharge operation.
CAS#
WE#
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column
access is started by asserting CAS# "LOW." Then, the Read or Write command
is selected by asserting WE# "LOW" or "HIGH."
Input
Input
Write Enable: The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK.
The WE# input is used to select the BankActivate or Precharge command and
Read or Write command.
LDQM,
UDQM
Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent
I/O buffer controls. The I/O buffers are placed in a high-z state when
LDQM/UDQM is sampled HIGH. Input data is masked when LDQM/UDQM is
sampled HIGH during a write cycle. Output data is masked (two-clock latency)
when LDQM/UDQM is sampled HIGH during a read cycle. UDQM masks DQ15-
DQ8, and LDQM masks DQ7-DQ0.
Preliminary
3
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
Data I/O: The DQ0-15 input and output data are synchronized with the positive
1M x 16 SDRAM
DQ0-DQ15 Input/Output
edges of CLK. The I/Os are byte-maskable during Reads and Writes.
NC
-
No Connect: These pins should be left unconnected.
VDDQ
Supply
DQ Power: Provide isolated power to DQs for improved noise immunity.
( 3.3V 0.3V )
±
VSSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
( 0 V )
VDD
VSS
Supply
Supply
Power Supply: +3.3V 0.3V
±
Ground
Preliminary
4
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State CKEn-1 CKEn DQM(6) A11 A10 A0-9 CS# RAS# CAS# WE#
Idle(3)
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
V
X
X
X
X
X
X
V
L
V
X
X
V
V
V
V
V
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
X
H
L
X
H
L
X
X
L
L
H
H
H
L
H
L
BankActivate
BankPrecharge
PrechargeAll
Any
Any
H
L
L
L
Active(3)
Active(3)
Active(3)
Active(3)
Idle
H
H
H
H
L
L
Write
Write and AutoPrecharge
Read
H
L
L
L
L
H
H
L
Read and Autoprecharge
Mode Register Set
No-Operation
H
V
X
X
X
X
X
X
L
L
Any
H
H
X
L
H
H
X
L
H
L
Active(4)
Burst Stop
Device Deselect
AutoRefresh
Any
X
H
H
X
H
X
X
H
X
X
H
X
X
Idle
SelfRefresh Entry
SelfRefresh Exit
Idle
L
L
Idle
H
X
H
X
X
H
X
X
H
X
X
X
H
X
X
H
X
X
H
X
X
(SelfRefresh)
Clock Suspend Mode Entry
Power Down Mode Entry
Active
Any(5)
H
H
L
L
X
X
X
X
X
X
X
X
Clock Suspend Mode Exit
Power Down Mode Exit
Active
L
L
H
H
X
X
X
X
X
X
X
X
Any
(PowerDown)
Data Write/Output Enable
Data Mask/Output Disable
Active
Active
H
H
X
X
L
X
X
X
X
X
X
H
Note: 1. V=Valid X=Don't Care L=Low level H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. LDQM and UDQM
Preliminary
5
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Commands
1
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", A11 = “V”, A10 = "L", A0-A9 = Don't care)
The BankPrecharge command precharges the bank disignated by A11 signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed
in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle
state and is ready to be activated again.
2
3
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", A11 = Don't care, A10 = "H", A0-A9 = Don't care)
The PrechargeAll command precharges both banks simultaneously and can be issued even if
both banks are not in the active state. Both banks are then switched to the idle state.
Read command
(RAS# = "H", CAS# = "L", WE# = "H", A11= “V”, A9 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent data-
out element will be valid by the next positive clock edge (refer to the following figure). The DQs go
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=1
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
3
t
, DQ's
0
1
2
1
0
CK1
CAS# latency=2
, DQ's
DOUT A
DOUT A
DOUT A
DOUT A
3
0
2
1
t
CK2
CAS# latency=3
, DQ's
DOUT A
DOUT A
t
2
3
CK3
Burst Read Operation
(Burst Length = 4, CAS# Latency = 1, 2, 3)
Preliminary
6
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks
earlier (i.e. LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto
precharge function may be interrupted by a subsequent Read or Write command to the same bank
or the other active bank before the end of the burst length. It may be interrupted by a
BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read
command can occur on any clock cycle following a previous Read command (refer to the following
figure).
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ B
DOUTA
NOP
NOP
READ A
NOP
NOP
NOP
NOP
NOP
CAS# latency=1
DOUTB
DOUTB
DOUT B
DOUT B
2
0
1
3
0
t
, DQ's
CK1
CAS# latency=2
, DQ's
DOUTA
DOUTB
DOUTB
DOUT B
DOUT B
0
0
1
2
3
t
CK2
CAS# latency=3
, DQ's
DOUTA
0
DOUTB
DOUTB
1
DOUT B
DOUTB
0
3
t
2
CK3
Read Interrupted by a Read
(Burst Length = 4, CAS# Latency = 1, 2, 3)
The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt
comes from a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior
to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O
contention, a single cycle with high-impedance on the DQ pins must occur between the last read
data and the Write command (refer to the following three figures). If the data output of the burst read
occurs at the second clock of the burst write, the LDQM/UDQM must be asserted (HIGH) at least
one clock prior to the Write command to avoid internal bus contention.
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
DINB
NOP
COMMAND
DQ's
DINB
DINB
0
DOUT A
1
2
0
Must be Hi-Z before
the Write Command
: "H" or "L"
Read to Write Interval
≥
(Burst Length 4, CAS# Latency = 3)
Preliminary
7
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
1 Clk Interval
DQM
BANKA
ACTIVATE
COMMAND
NOP
READ A
NOP
NOP
WRITE A
NOP
NOP
NOP
CAS# latency=1
DIN A
0
DIN A
DIN A
DIN A
3
t
, DQ's
1
2
CK1
Must beHi-Z before
the Write Command
CAS# latency=2
DIN A
0
DIN A
DIN A
DIN A
3
t
, DQ's
1
2
CK2
: "H" or "L"
Read to Write Interval
≥
(Burst Length 4, CAS# Latency = 1, 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
NOP
NOP
NOP
WRITE B
DIN B
NOP
NOP
NOP
NOP
READ A
CAS# latency=1
DOUT A
DIN B
DIN B
DIN B
DIN B
0
0
1
2
3
3
t
, DQ's
CK1
Must be Hi-Z before
the Write Command
CAS# latency=2
, DQ's
DIN B
DIN B
1
DIN B
t
0
2
CK2
: "H" or "L"
Read to Write Interval
≥
(Burst Length 4, CAS# Latency = 1, 2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank,
Col A
Bank,
Row
ADDRESS
Bank(s)
tRP
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
Precharge
NOP
Activate
CAS# latency=1
DOUT A
DOUT A
2
DOUT A
DOUT A
0
1
3
t
, DQ's
CK1
CAS# latency=2
, DQ's
DOUT A
DOUT A
2
DOUT A
DOUT A
0
1
3
t
CK2
CAS# latency=3
, DQ's
DOUT A
DOUT A
2
DOUT A
DOUT A
0
1
3
t
CK3
Read to Precharge
(CAS# Latency = 1, 2, 3)
Preliminary
8
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
4
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", A11 = “V”, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after
the read operation. Once this command is given, any subsequent command cannot occur within a
time delay of tRP(min.) + burst length . At full-page burst, only the read operation is performed in this
{
}
command and the auto precharge function is ignored.
5
Write command
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
DIN
A
DIN A
DIN
A
DIN A
3
don't care
DQ0 - DQ3
0
1
2
The first data element and the write
are registeredon the same clock edge.
Extra data is masked.
Burst Write Operation
(Burst Length = 4, CAS# Latency = 1, 2, 3)
A write burst without the auto precharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
1 Clk Interval
DIN DIN B
A
DIN B
DIN B
DIN B
3
DQ's
0
0
1
2
Write Interrupted by a Write
(Burst Length = 4, CAS# Latency = 1, 2, 3)
Preliminary
9
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
WRITE A
READ B
NOP
NOP
NOP
CAS# latency=1
DOUT B
DOUT B
DOUT B
DOUT B
DIN A
0
2
3
0
1
t
, DQ's
CK1
CAS# latency=2
, DQ's
DOUT B
DOUT B
DIN A
0
DOUT B
DOUT B
1
don't care
don't care
2
3
0
t
CK2
CAS# latency=3
, DQ's
DOUT B
DOUT B
DOUT B
DOUT B
3
DIN A
0
don't care
t
0
1
2
CK3
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Input data for the write is masked.
Write Interrupted by a Read
(Burst Length = 4, CAS# Latency = 1, 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the
LDQM/UDQM signals must be used to mask input data, starting with the clock edge following the
last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll
command is entered (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
t
RP
COMMAND
WRITE
Precharge
BANK (S)
NOP
NOP
Activate
ROW
NOP
NOP
BANK
COL n
ADDRESS
DQ
t
WR
DIN
n
DIN
n + 1
: don't care
Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
Preliminary
10
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
6
Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of (burst length -1) + tWR + tRP(min.) . At full-page burst, only the write operation is
{
}
performed in this command and the auto precharge function is ignored.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank A
Activate
Write A
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
NOP
AutoPrecharge
DAL
t
CAS# latency=1
DIN
DIN
DIN
A
A
A
DIN A
DIN A
DIN A
0
0
0
1
1
1
*
*
*
t
, DQ's
CK1
DAL
t
CAS# latency=2
, DQ's
t
CK2
DAL
t
CAS# latency=3
, DQ's
t
CK3
Begin AutoPrecharge
Bank can be reactivated at completion of DAL
DAL= WR + RP
t
t
t
*
t
Burst Write with Auto-Precharge
(Burst Length = 2, CAS# Latency = 1, 2, 3)
7
Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", A11 = “V”, A10 = “V”, A0-A9 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The default
values of the Mode Register after power-up are undefined; therefore this command must be issued
at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to
the mode register. One clock cycle is required to complete the write in the mode register (refer to the
following figure). The contents of the mode register can be changed using the same command and
the clock cycle requirements during operation as long as both banks are in the idle state.
Preliminary
11
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Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
T0
T 1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CK2
CKE
CS#
Clock min.
RAS#
CAS#
WE#
A11
A10
Address Key
A0-A9
DQM
RP
t
Hi-Z
DQ
ModeRegister
Set Command
PrechargeAll
Any
Command
Mode Register Set Cycle
(CAS# Latency = 1, 2, 3)
The mode register is divided into various fields depending on functionality.
Burst Length Field (A2~A0)
•
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 1, 2, 4, 8, or full page.
A2
0
A1
0
A0
0
Burst Length
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
Reserved
Reserved
Full Page
1
0
1
1
1
0
1
1
1
Preliminary
12
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Nov 2001
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EM636165
1M x 16 SDRAM
Addressing Mode Select Field (A3)
•
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode.
Sequential Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only
supports burst length of 4 and 8.
A3
0
Addressing Mode
Sequential
1
Interleave
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column
address which is input to the device. The internal column address is varied by the Burst
Length as shown in the following table. When the value of column address, (n + m), in
the table is larger than 255, only the least significant 8 bits are effective.
Data n
0
n
1
2
3
4
5
6
7
-
-
255 256 257
-
-
n+1 n+2 n+3 n+4 n+5 n+6 n+7
n+255
n
n+1
Column Address
Burst Length
2 words:
4 words:
8 words:
Full Page: Column address is repeated until terminated.
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting
the address bits in the sequence shown in the following table.
Data n
Column Address
Burst Length
Data 0 A7 A6 A5 A4 A3 A2 A1 A0
Data 1 A7 A6 A5 A4 A3 A2 A1 A0#
Data 2 A7 A6 A5 A4 A3 A2 A1# A0
Data 3 A7 A6 A5 A4 A3 A2 A1# A0#
Data 4 A7 A6 A5 A4 A3 A2# A1 A0
Data 5 A7 A6 A5 A4 A3 A2# A1 A0#
Data 6 A7 A6 A5 A4 A3 A2# A1# A0
Data 7 A7 A6 A5 A4 A3 A2# A1# A0#
4 words
8 words
CAS# Latency Field (A6~A4)
•
This field specifies the number of clock cycles from the assertion of the Read command to
the first read data. The minimum whole value of CAS# Latency depends on the frequency
of CLK. The minimum whole value satisfying the following formula must be programmed
into this field.
tCAC(min) ≤ CAS# Latency X tCK
A6
0
A5
A4
0
CAS# Latency
Reserved
1 clock
0
0
1
1
X
0
1
0
0
2 clocks
0
1
3 clocks
1
X
Reserved
Preliminary
13
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Nov 2001
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EM636165
1M x 16 SDRAM
Test Mode field (A8~A7)
•
These two bits are used to enter the test mode and must be programmed to "00" in normal
operation.
A8
0
A7
0
Test Mode
normal mode
0
1
Vendor Use Only
Vendor Use Only
1
X
Single Write Mode (A9)
•
This bit is used to select the write mode. When the BS bit is "0", the Burst-Read-Burst-
Write mode is selected. When the BS bit is "1", the Burst-Read-Single-Write mode is
selected.
A9
0
Single Write Mode
Burst-Read-Burst-Write
Burst-Read-Single-Write
1
Note: A10 and A11 should stay “L” during mode set cycle.
8
9
No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS#
is Low). This prevents unwanted commands from being registered during idle or wait states.
Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst ends after a delay equal to the CAS# latency (refer to the following figure). The
termination of a write burst is shown in the following figure.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
NOP
NOP
NOP
COMMAND
NOP
NOP
Burst Stop
DOUT A
NOP
NOP
The burst ends after a delay equal to the CAS# latency.
CAS# latency=1
DOUT A
DOUTA
DOUT A
0
1
2
3
t
, DQ's
CK1
CAS# latency=2
, DQ's
DOUT A
DOUTA
DOUT A
2
DOUT A
3
0
1
t
CK2
CAS# latency=3
, DQ's
DOUT A
0
DOUTA
DOUT A
DOUT A
3
1
2
t
CK3
Termination of a Burst Read Operation
(Burst Length
4, CAS# Latency = 1, 2, 3)
Preliminary
14
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Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
WRITE A
NOP
Burst Stop
don't care
NOP
NOP
CAS# latency=1, 2, 3
DQ's
DIN A
DIN
A
DIN A
2
1
0
Input data for the Write is masked.
Termination of a Burst Write Operation
(Burst Length = X, CAS# Latency = 1, 2, 3)
10 Device Deselect command
(CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
to the No Operation command.
11 AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms)
(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", A11 = “Don‘t care, A0-A9 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 2048 times within 32ms. The time required to complete the auto
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, both banks need
to be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP(min), must be met before successive auto refresh operations are
performed.
12 SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms)
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A9 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by
restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
13 SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms)
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
This command is used to exit from the SelfRefresh mode. Once this command is registered,
NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 4096 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.
Preliminary
15
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
14 Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in
Timing Waveforms)
(CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when both banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (64ms) since the command does not perform any
refresh operations.
15 Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing
Waveforms, CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated
from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is
in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the
active state. tPDE(min.) is required when the device exits from the PowerDown mode. Any
subsequent commands can be issued after one clock cycle from the end of this command.
16 Data Write / Output Enable, Data Mask / Output Disable command (LDQM/UDQM = "L", "H")
During a write cycle, the LDQM/UDQM signal functions as a Data Mask and can control every
word of the input data. During a read cycle, the LDQM/UDQM functions as the controller of output
buffers. LDQM/UDQM is also used for device selection, byte selection and bus control in a memory
system. LDQM controls DQ0 to DQ7, UDQM controls DQ8 to DQ15.
Preliminary
16
Rev. 1.8
Nov 2001
Et r on Tech
Absolute Maximum Rating
EM636165
1M x 16 SDRAM
Symbol
Item
Rating
-5/55/6/7/7L/8/10
- 1.0 ~ 4.6
Unit
Note
-10I
VIN, VOUT
VDD, VDDQ
TOPR
Input, Output Voltage
Power Supply Voltage
Operating Temperature
Storage Temperature
Power Dissipation
V
V
1
1
1
1
1
1
-1.0 ~ 4.6
0 ~ 70
- 55 ~ 125
-40 ~ 85
0.6
C
C
°
°
TSTG
PD
1
W
IOUT
Short Circuit Output Current
50
mA
Recommended D.C. Operating Conditions (Ta = -40~85 C)
°
Symbol
VDD
Parameter
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
V
Note
Power Supply Voltage
2
2
2
VDDQ
VIH
Power Supply Voltage(for I/O Buffer)
LVTTL Input High Voltage
3.0
3.3
3.6
V
2.0
V
DDQ+0.3
V
VIL
LVTTL Input Low Voltage
- 0.3
0.8
V
2
Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25 C)
°
Symbol
CI
Parameter
Min.
Max.
Unit
pF
Input Capacitance
2
4
5
7
CI/O
Input/Output Capacitance
pF
Note: These parameters are periodically sampled and are not 100% tested.
Recommended D.C. Operating Conditions (VDD = 3.3V ± 0.3V)
1. Ta = 0~70 C
°
- 5/55/6/7/8/10
Max.
- 7L
Description/Test condition
Operating Current
RC ≥ tRC(min), Outputs Open, Input
Symbol
Unit Note
1 bank
operation
130/125/115/100/95 /85 40
3
t
IDD1
signal one transition per one cycle
Precharge Standby Current in non-power down mode
tCK = tCK(min), CS# ≥ VIH, CKE = VIH
Input signals are changed once during 30ns.
Precharge Standby Current in power down mode
3
3
115/110/90/85/75/60
15
IDD2N
2
0.8
0.8
1.5
20
IDD2P
IDD2PS
IDD3P
IDD3N
IDD4
tCK = tCK(min), CKE ≤ VIL(max)
Precharge Standby Current in power down mode
2
tCK = ∞ CKE ≤ VIL(max)
Active Standby Current in power down mode
CKE ≤ VIL(max), tCK = tCK(min)
Active Standby Current in non-power down mode
CKE ≥ VIH(min), tCK = tCK(min)
Operating Current (Burst mode)
mA
3
2
105/100/90/80/70/55
165/160/150/140/130/115 40
115/110/100/90/90 /80 40
3, 4
3
tCK=tCK(min), Outputs Open, Multi-bank interleave,gapless data
Refresh Current
IDD5
t
RC ≥ tRC(min)
Self Refresh Current
IH ≥ VDD - 0.2, 0V ≤ VIL ≤ 0.2V
2
0.5
IDD6
V
Preliminary
17
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
2. Industrial Operating temperature : Ta = -40~85 C
°
EM636165-10I
Description/Test condition
Operating Current
RC ≥ tRC(min), Outputs Open, Input
Symbol
Max.
Note
Unit
1 bank operation
IDD1
80
3
t
signal one transition per one cycle
Precharge Standby Current in non-power down mode
tCK = tCK(min), CS# ≥ VIH, CKE = VIH
Input signals are changed once during 30ns.
IDD2N
3
3
35
Precharge Standby Current in power down mode
IDD2P
3
2
tCK = tCK(min), CKE ≤ VIL(max)
Precharge Standby Current in power down mode
tCK = ∞ CKE ≤ VIL(max)
IDD2PS
mA
Active Standby Current in power down mode
CKE ≤ VIL(max), tCK = tCK(min)
Active Standby Current in non-power down mode
CKE ≥ VIH(min), tCK = tCK(min)
Operating Current (Burst mode)
tCK=tCK(min), Outputs Open, Multi-bank interleave,gapless data
IDD3P
IDD3N
IDD4
7
3
51
100
80
3, 4
3
Refresh Current
IDD5
t
RC ≥ tRC(min)
Self Refresh Current
IH ≥ VDD - 0.2, 0V ≤ VIL ≤ 0.2V
V
IDD6
2
Parameter
Description
Min.
Max.
Unit Note
IIL
Input Leakage Current
( 0V ≤ VIN ≤ VDD, All other pins not under test = 0V )
- 10
10
µA
IOL
VOH
VOL
Output Leakage Current
Output disable, 0V ≤ VOUT ≤ VDDQ
- 10
2.4
10
µA
V
)
LVTTL Output "H" Level Voltage
( IOUT = -2mA )
LVTTL Output "L" Level Voltage
( IOUT = 2mA )
0.4
V
Preliminary
18
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V 0.3V, Ta = -40~85 C) (Note: 5, 6, 7, 8)
°
- 5/55/6/7/7L/8/10
Symbol
A.C. Parameter
Min.
Max.
Unit Note
tRC
Row cycle time
48/48/54/63/63/72/90
9
(same bank)
tRCD
RAS# to CAS# delay
(same bank)
15/16/16/16/16/16/30
9
ns
9
tRP
Precharge to refresh/row activate
command (same bank)
15/16/16/16/16/16/30
10/11/12/14/14/16/20
tRRD
Row activate to row activate delay
(different banks)
9
tRAS
Row activate to precharge time
(same bank)
30/32/36/42/42/48/60
100,000
tWR
Write recovery time
Cycle
1
tCK1
tCK2
tCK3
tCH
CL* = 1
-/19/20/20/20/20/30
-/7/7.5/8/8/8/15
5/5.5/6/7/7/8/10
2/2/2/2.5/2.5/3/3.5
2/2/2/2.5/2.5/3/3.5
10
Clock cycle time
CL* = 2
CL* = 3
ns
11
11
Clock high time
Clock low time
tCL
tAC1
tAC2
tAC3
tCCD
tOH
tLZ
Access time from CLK
(positive edge)
CL* = 1
CL* = 2
CL* = 3
-/7/8/13/13/18/27
-/5.5/6/6.5/6.5/7/12
4.5/5/5/5.5/5.5/6.5/7.5
11
10
CAS# to CAS# Delay time
Data output hold time
1
Cycle
1.8/2/2/2/2/2/3
1/1/1/1/1/2/2
Data output low impedance
Data output high impedance
tHZ
3/3.5/4/5/5/6/8
8
tIS
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
PowerDown Exit set-up time
Refresh time
2/2/2/2/2/2.5/3
1
ns
11
11
tIH
tPDE
tREF
5/5.5/6/7/7/8/10
64
ms
CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to VSS.VIH(Max)=4.6 for pulse width≤5ns.VIL(Min)=-1.5Vfor pulse width≤5ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK
.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 10.
Preliminary
19
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
6. A.C. Test Conditions
LVTTL Interface
Reference Level of Output Signals
Output Load
1.4V / 1.4V
Reference to the Under Output Load (B)
Input Signal Levels
2.4V / 0.4V
1ns
Transition Time (Rise and Fall) of Input Signals
Reference Level of Input Signals
1.4V
1.4V
3.3V
50Ω
1.2kΩ
50Ω
Z0=
Output
Output
30pF
30pF
870Ω
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed
slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. These parameters account for the number of clock cycle and depend on the operating frequency of the
clock as follows:
the number of clock cycles = specified value of timing/Clock cycle time
(count fractions as a whole number)
10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e.,
12. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state
and both CKE = "H" and LDQM/UDQM = "H." The CLK signals must be started at the same time.
2) After power-up, a pause of 200µseconds minimum is required. Then, it is recommended that
LDQM/UDQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.
Preliminary
20
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Timing Waveforms
Figure 1. AC Parameters for Write Timing
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCL
tCK2
tCH
tIS
tIH
Begin AutoPrecharge
Bank B
Begin AutoPrecharge
Bank A
CKE
CS#
tIS
tIS
RAS#
CAS#
WE#
A11
tIH
RAx
RBx
RBx
RAy
RAy
RAz
RAz
RBy
RBy
A10
tIS
A0-A9
CAx
CBx
RBx
CAy
DQM
DQ
tDAL
tRCD
tIS
tWR
tRC
tRP
tRRD
tIH
Hi-Z
Ax0 Ax1 Ax2
Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3
Activate
Writewith
Activate
Writewith
Activate
Write
Command
Bank A
Precharge
Activate
Activate
Command
Bank B
Command AutoPrecharge Command AutoPrecharge Command
Command Command
Bank A
Command
Bank A
Bank B
Command
Bank B
Bank A
Bank A
Bank A
Preliminary
21
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Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 2. AC Parameters for Read Timing
(Burst Length=2, CAS# Latency=2)
T0
T 1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T 11 T12
T13
CLK
CKE
tCK2
tIS
tCH tCL
Begin AutoPrecharge
Bank B
tIH
tIH
tIS
CS#
RAS#
CAS#
WE#
A11
A10
tIH
RBx
RAx
RAx
RAy
RAy
tIS
A0-A9
CAx
RBx
CBx
tRRD
tRAS
tRC
tHZ
DQM
DQ
tAC2
tLZ
tAC2
tRP
tRCD
Hi-Z
Ax0
Bx0
Bx1
Ax1
tHZ
tOH
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read with
Precharge
Command
Bank A
Activate
Command
Bank A
Auto Precharge
Command
Bank B
Preliminary
22
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 3. Auto Refresh (CBR)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
CS#
RAS#
CAS#
WE#
A11
RAx
A10
CAx
RAx
A0-A9
DQM
tRC
tRC
tRP
Ax0
Ax2
Ax1
Ax3
DQ
Read
Command
Bank A
PrechargeAll AutoRefresh
AutoRefresh
Command
Activate
Command
Bank A
Command
Command
Preliminary
23
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 4. Power on Sequene and Auto Refresh (CBR)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
High level
Minimum of 2 Refresh Cycles are required
is reauired
CS#
RAS#
CAS#
WE#
BS
A10
Address Key
A0-A9
DQM
DQ
tRP
tRC
Hi-Z
1st AutoRefresh
Command
PrechargeALL
Command
2nd Auto Refresh
Command
Any
Command
Mode Register
Set Command
Inputs must be
stable for 200µs
Preliminary
24
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 5. Self Refresh Entry & Exit Cycle
T0
T1
T2
T3
T4
T5
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
T6
CLK
*Note 2
tRC(min) *Note 7
*Note 4
*Note 1
*Note 3
CKE
CS#
tPDE
tSRX
*Note 5
tIS
*Note 6
RAS#
CAS#
A11
*Note 8
*Note 8
A0-A9
WE#
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Enter
SelfRefresh Exit
AutoRefresh
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
To Exit SelfRefresh Mode
1. System clock restart and be stable before returning CKE high.
2. Enable CKE and CKE should be set high for minimum time of tSRX
3. CS# starts from high.
.
4. Minimum tRC is required after CKE going high to complete SelfRefresh exit.
5. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
Preliminary
25
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 6.1. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CK1
t
CKE
CS#
RAS#
CAS#
WE#
A11
RAx
A10
A0-A9
RAx
CAx
DQM
DQ
HZ
t
Hi-Z
Ax0
Ax2
Ax3
Ax1
Clock Suspend
1 Cycle
Activate
Command
Bank A
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Read
Command
Bank A
Note: CKE to CLK disable/enable = 1 clock
Preliminary
26
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 6.2. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
CAx
A0-A9
DQM
DQ
tHZ
Hi-Z
Ax0
Ax3
Ax1
Ax2
Activate
Command
Bank A
Read
Command
Bank A
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
Preliminary
27
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 6.3. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T 2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK3
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
DQM
DQ
CAx
RAx
tHZ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Activate
Command
Bank A
Read
Command
Bank A
Clock Suspend Clock Suspend
Clock Suspend
3 Cycles
1 Cycle
2 Cycles
Note: CKE to CLK disable/enable = 1 clock
Preliminary
28
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 7.1. Clock Suspension During Burst Write (Using CKE)
(Burst Length = 4, CAS# Latency = 1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CK1
t
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A8
DQM
CAx
RAx
DQ Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate Clock Suspend Clock Suspend
Clock Suspend
3 Cycles
Command
Bank A
1 Cycle
2 Cycles
Write
Command
Bank A
Note: CKE to CLK disable/enable = 1 clock
Preliminary
29
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 7.2. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
T14 T15 T16 T17 T18 T19 T20 T21 T22
T13
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
RAx
A10
A0-A9
DQM
DQ
RAx
CAx
Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate
Command
Bank A
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Write
Command
Bank A
Note: CKE to CLK disable/enable = 1 clock
Preliminary
30
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 7.3. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK3
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
DQ
Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate
Command
Bank A
Clock Suspend Clock Suspend
1 Cycle 2 Cycles
Write
Command
Bank A
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
Preliminary
31
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 8. Power Down Mode and Clock Mask
(Burst Lenght=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
tCK2
tPDE
tIS
Valid
RAS#
CAS#
WE#
A11
RAx
A10
RAx
CAx
A0~A8
DQM
tHZ
Hi-Z
Ax0
Ax1
Ax2
Ax3
DQ
ACTIVE
STANDBY
PRECHARGE
STANDBY
Activate
Command
Bank A
Read
Command
Bank A
Clock Mask
Start
Clock Mask
End
Precharge
Command
Bank A
Power Down
Mode Exit
Any
Power Down
ModeEntry
Power Down
Mode Exit
Command
Power Down
ModeEntry
Preliminary
32
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 9.1. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAz
RAz
RAw
RAw
CAw
CAz
CAy
CAx
A0~A8
DQM
Hi-Z
DQ
Aw0 Aw1 Aw2
Ay2 Ay3
Az1 Az2 Az3
Aw3
Ax1 Ay0 Ay1
Az0
Ax0
Activate
Command
Bank A
Read
Read
Precharge
Command
Bank A
Read
Command
Bank A
Command Command
Bank A
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Preliminary
33
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 9.2. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CK2
t
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAz
RAz
RAw
RAw
CAx
CAy
CAz
CAw
A0~A8
DQM
Hi-Z
Ay0
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1
Ay1 Ay2 Ay3
Precharge
Az1 Az2 Az3
DQ
Az0
Activate
Command
Bank A
Read
Command
Bank A
Read
Command Command
Bank A Bank A
Read
Activate
Command
Bank A
Read
Command
Bank A
Command
Bank A
Preliminary
34
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 9.3. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CK3
t
CS#
RAS#
CAS#
WE#
A1
1
RAz
RAz
RAw
RAw
A10
A0~A9
DQM
CAy
CAz
CAw
CAx
Hi-Z
Aw0
Aw3
Aw1
Ax1
Az0
Aw2
Ax0
Ay0 Ay1 Ay2 Ay3
Precharge
DQ
Read
Command
Bank A
Read
Read
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Command
Bank A
Command
Bank A
Preliminary
35
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 10.1. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CAS#
WE#
A11
A10
RBz
RBz
RBw
RBw
CBw
CBz
CBx
CBy
A0~A9
DQM
DQ
Hi-Z
DBw3 DBx0
DBy0 DBy1 DBy2 DBy3
DBx1
DBw2
DBw0 DBw1
DBz0 DBz1
DBz2 DBz3
Precharge
Activate
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Command
Bank B
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Preliminary
36
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 10.2. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
CS#
RAS#
CAS#
WE#
A11
A10
RBz
RBz
RBw
RBw
CBy
CBz
CBw
CBx
A0~A8
DQM
Hi-Z
DBy2
DBy3
DBz0 DBz1 DBz2
DBz3
DBw0
Write
DBx1
DBw1 DBw2 DBw3 DBx0
Write
DBy0 DBy1
Write
DQ
Activate
Command
Bank A
Precharge
Command Command
Activate
Write
Command
Bank B
Command
Bank B
Command
Bank B
Command
Bank B
Bank B
Bank B
Preliminary
37
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 10.3. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBw
RBw
RBz
RBz
CBz
CBw
CBx
CBy
A0~A9
DQM
Hi-Z
DBz2
DBz1
DBy2 DBy3
DBy1
DBw0 DBw1 DBw2 DBw3
Write
DBx1 DBy0
Write
DBz0
Write
DQ
DBx0
Write
Precharge
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank A
Command
Bank B
Command
Command
Bank B
Command
Bank B
Bank B
Preliminary
38
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 11.1. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=1)
T5
T16
T19
T17 T18 T20 T21 T22
T0 T1 T2 T3 T4
T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
CLK
CKE
tCK1
High
CS#
RAS#
CAS#
WE#
A11
A10
RBx
RBy
RBy
RAx
CBy
RAx CAx
RBx CBx
A0~A9
tRCD
tAC1
tRP
DQM
DQ
Hi-Z
Bx3
Bx5 Bx6
Bx7
By1 By2
Ax0
Ax3 Ax4 Ax5
By0
Bx0 Bx1 Bx2
Bx4
Ax1 Ax2
Ax6 Ax7
Read
Command
Bank B
Precharge
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Read
Read
Command
Bank B
Command
Bank B
Command
Bank A
Preliminary
39
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 11.2. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
A11
RBx
RAx
RAx
RBy
RBy
A10
CBx
A0~A9
DQM
CBy
RBx
CAx
tRCD
tAC2
tRP
Hi-Z
Ax4 Ax5
By0 By1
Bx0 Bx1 Bx2 Bx3
Bx5 Bx6 Bx7
Ax2 Ax3
Ax6 Ax7
Bx4
Ax0 Ax1
DQ
Activate
Command
Bank B
Read
Command
Bank B
Activate
Command
Bank A
Precharge
Activate
Command
Bank B
Read
Command
Bank B
Command
Bank B
Read
Command
Bank A
Preliminary
40
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 11.3. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBx
RBy
RBy
RAx
RAx
RBx
CBy
CBx
CAx
A0~A9
DQM
tRCD
tAC3
tRP
Hi-Z
DQ
Ax7 By0
Bx6
Ax6
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5
Bx7 Ax0 Ax1 Ax2 Ax3
Ax5
Ax4
Activate
Command
Bank B
Read
Command
Bank B
Activate
Read
Precharge
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
Read
Command
Bank B
Command
Command
Bank A
Bank A
Preliminary
41
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 12.1. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
High
CS#
RAS#
CAS#
WE#
A11
A10
RAy
RAy
RAx
RBx
RBx
A0~A9
DQM
DQ
RAx
CAy
CBx
CAx
tRCD
tRP
tWR
Hi-Z
DBx7
DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6
DAy0 DAy1 DAy2
DAx6
DAy3
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5
Activate
Command
Bank A
Activate
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
Write
Command
Bank A
Write
Activate
Command
Bank A
Write
Command
Bank A
Command
Bank B
Preliminary
42
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 12.2. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBx
RAy
RAy
CAy
RAx
CAx
CBx
A0~A8
DQM
tRCD
tWR*
tRP
tWR*
Hi-Z
DQ
DBx7
DAy3
DAy4
DAx6
DAy0 DAy1 DAy2
Write
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5
DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6
Activate
Command
Bank B
Activate
Command Command
Bank A Bank A
Write
Write
Activate
Command
Bank A
Command
Bank B
Command
Bank A
Precharge
Precharge
Command
Bank B
Command
Bank A
* tWR > tWR(min.)
Preliminary
43
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 12.3. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CK3
t
High
CKE
CS#
RAS#
CAS#
WE#
A11
RAx
RBx
RBx
RAy
RAy
A10
CAy
RAx
CAx
CBx
A0~A9
DQM
RCD
t
WR*
t
RP
t
WR*
t
Hi-Z
DAx6
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5
DAx7 DBx0
DAy2
DAy3
DBx2
DBx5 DBx6
Activate
DAy0 DAy1
Write
DBx1
DBx3 DBx4
DBx7
DQ
Activate
Command
Bank A
Activate
Write
Write
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
Command
Command
Command
Command
Bank A
Bank A
Bank B
Bank A
* tWR > tWR(min.)
Preliminary
44
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 13.1. Read and Write Cycle
(Burst Length=4, CAS# Latency=1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
CAx
CAy
CAz
A0~A9
DQM
Hi-Z
DQ
Az3
Az1
Ax3
DAy3
Az0
Ax0 Ax1 Ax2
DAy1
DAy0
The Read Data
is Masked with a
TwoClock
The Write Data
is Masked with a
Zero Clock
Activate
Write
Command
Bank A
Precharge
Command
Bank B
Read
Command
Bank A
Command
Bank A
Latency
Latency
Read
Command
Bank A
Preliminary
45
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 13.2. Read and Write Cycle
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
CS#
RAS#
CAS#
WE#
A11
A10
RAx
CAy
CAx
CAz
RAx
A0~A9
DQM
Hi-Z
DQ
Az3
Ax0
DAy0
Az0 Az1
Ax1 Ax2 Ax3
DAy1
DAy3
Read
Command
Bank A
Write
Command
Bank A
Read
Command
Bank A
TheRead Data
Activate
Command
Bank A
The Write Data
is Masked with a
Zero Clock
is Masked with a
TwoClock
Latency
Latency
Preliminary
46
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 13.3. Read and Write Cycle
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK3
CS#
RAS#
CAS#
WE#
A11
A10
RAx
CAy
CAx
CAz
RAx
A0~A9
DQM
Hi-Z
DQ
DAy0 DAy1
Ax0 Ax1 Ax2 Ax3
DAy3
Az0 Az1
Az3
Read
Command
Bank A
The Write Data
Activate
Command
Bank A
Read
Command
Bank A
Write
Command
Bank A
The Read Data
is Masked with a
Zero Clock
Latency
is Masked with a
TwoClock
Latency
Preliminary
47
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 14.1. Interleaving Column Read Cycle
(Burst Length=4, CAS# Latency=1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
RBw
RBw
CBz
CBx
CBy
CAy
CBw
RAx
A0~A9
tRCD tAC1
DQM
DQ
Hi-Z
Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1
By0
Ay0 Ay1 Bz0
By1
Bz1 Bz2 Bz3
Activate
Activate
Command
Bank A
Read
Command
Bank B
Read
Read
Read
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
Command
Bank B
Command Command
Bank B
Bank A
Read
Read
Command
Bank B
Command
Bank A
Preliminary
48
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 14.2. Interleaving Column Read Cycle
(Burst Length=4, CAS# Latency=2)
T0 T1 T2
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
CAy
RAx
CBw
CBx
CBz
CBy
CAy
RAx
A0~A9
DQM
tRCD
tAC2
Hi-Z
DQ
Ax0
Ax2
Bz2 Bz3
Ax1
Ay1
Bz1
Ax3
By0 By1 Ay0
Bz0
Bw1
Bx1
Bw0
Bx0
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Command Command
Bank A Bank B
Read
Activate
Command
Bank A
Precharge
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank A
Preliminary
49
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 14.3. Interleaved Column Read Cycle
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
T22
CLK
CKE
tCK3
CS#
RAS#
CAS#
WE#
A11
A10
RBx
RAx
RBx
CBy
RAx
CAx
CBx
CBz
CAy
A0~A9
DQM
DQ
tAC3
tRCD
Hi-Z
Ay0 Ay1 Ay2 Ay3
By0
Ax0
Ax3
By1 Bz0 Bz1
Ax1 Ax2
Bx0 Bx1
Read
Read
Read
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank B
Read
Prechaerge
Precharge
Command
Bank A
Command
Bank A
Command Command
Command
Bank B
Bank B
Bank B
Activate
Command
Bank B
Preliminary
50
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 15.1. Interleaved Column Write Cycle
(Burst Length=4, CAS# Latency=1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBw
RAx CAx RBw
CBw
CBz
CAy
CBx
CBy
A0~A9
tRP
tWR tRP
tRCD
tRRD
DQM
DQ
Hi-Z
DBw0 DBw1 DBx0
DAy0
Write
DAx0
DAx2
DBx1 DBy0 DBy1
Write
DAy1
DBz1 DBz2 DBz3
DBz0
DAx1
DAx3
Activate
Command
Bank A
Activate
Command
Bank B
Write
Command Command
Bank B Bank B
Write
Write
Command
Bank B
Precharge
Command
Bank B
Command Command
Bank B Bank A
Precharge
Command
Bank A
Write
Command
Bank A
Preliminary
51
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 15.2. Interleaved Column Write Cycle
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CK2
t
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
RBw
RBw
CBw
CBx
CBy
CBz
CAx
CAy
A0~A9
DQM
WR
t
RCD
t
RP
RP
t
t
RRD
t
Hi-Z
DBz2
DBz3
DQ
DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1
DAx0
Activate
Write
Activate
Command
Bank B
Write
Command Command
Bank B Bank B
Write
Write
Command Command
Bank B Bank A
Write
Write
Command
Bank B
Precharge
Command
Bank B
Command Command
Bank A
Bank A
Precharge
Command
Bank A
Preliminary
52
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 15.3. Interleaved Column Write Cycle
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
T12
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
RBw
CBx
CAx RBw
CBy
CAy
CBz
CBw
A0~A9
DQM
tRCD
tRRD > tRRD(min)
tWR
tWR(min)
tRP
Hi-Z
DQ
DBw0
Write
DAx0 DAx1 DAx2 DAx3
DBw1 DBx0 DBx1
Write
DBy1
DAy1
DBz2 DBz3
DBy0
DAy0
Write
DBz0 DBz1
Write
Activate
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank B
Command Command
Bank B Bank B
Command
Bank A
Command
Bank B
Precharge
Command
Bank A
Write
Command
Bank A
Preliminary
53
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 16.1. Auto Precharge after Read Burst
(Burst Length=4, CAS# Latency=1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBy
RBy
RBz
RBx
CAx
RBx CBx
CAy
RBz CBz
RAx
CBy
A0~A9
DQM
DQ
Hi-Z
Bz0 Bz1
Ax3
Ay0
Bz3
Bx0 Bx1 Bx2 Bx3
Ay1 Ay2 Ay3
By1 By2
Bz2
Ax0 Ax1 Ax2
By0
By3
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Read with
Activate
Auto Precharge
Command
Bank B
Command
Bank B
Read with
Read
Read with
Read with
Auto Precharge
Command
Bank B
Command
Bank A
Auto Precharge
Command
Bank B
Auto Precharge
Command
Bank A
Preliminary
54
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 16.2. Auto Precharge after Read Burst
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBy
RBy
RAx
RBx
RBx
RAz
RAz
CAz
CAx
CBx
RAy
CBy
RAx
A0~A9
DQM
DQ
Hi-Z
Az0 Az1
Ax0
Ay3
By2
Ax1
Bx0
Ay1
By1
Az2
Ax2 Ax3
Read with
Ay0
Ay2
By0
By3
Bx1 Bx2 Bx3
Read with
Activate
Read
Activate
Activate
Activate
Read with
Read with
Command Command
Command Auto Precharge
Auto Precharge Command
Command Auto Precharge
Auto Precharge
Command
Bank B
Bank A
Bank A
Bank B
Command
Bank B
Command
Bank A
Bank B
Bank A
Command
Bank A
Preliminary
55
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 16.3. Auto Precharge after Read Burst
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBx
RBy
RBy
CBx
CAy
CBy
CAx
RAx
A0~A9
DQM
Hi-Z
DQ
Ay0
Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3
Ay1 Ay2 Ay3
By0 By1
By3
Ax0
By2
Activate
Command
Bank A
Activate
Read with
Activate
Command
Bank B
Read with
Command
Bank B
Auto Precharge
Command
Bank B
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Read
Command
Bank A
Bank A
Preliminary
56
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 17.1. Auto Precharge after Write Burst
(Burst Length=4, CAS# Latency=1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
High
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBx
RBx
RBy
RBy
RAz
RAz
RAx
CAz
RAx
CBx
CBy
CAy
CAx
A0~A9
DQM
DQ
Hi-Z
DAx0
DAx2
DBx2
DAy3 DBy0
DBy2
DAz0
DAz0
DAx1
DAx3 DBx0
DBx3
DAy1 DAy2
DBy1
DBy3
DAz0
DAz0
DBx1
DAy0
Activate
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Writewith
Auto Precharge
Command
Writewith
Auto Precharge
Command
Bank B
Write
Command
Bank A
Bank B
Writewith
Auto Precharge
Command
Writewith
Auto Precharge
Command
Bank A
Bank A
Preliminary
57
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 17.2. Auto Precharge after Write Burst
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
A11
RAx
RBx
RBx
RBy
RBy
RAz
RAz
A10
A0~A9
DQM
CBy
CAz
CBx
CAy
CAx
RAx
Hi-Z
DAy0
DBy2
DAz3
DAz2
DQ
DBx3
DBy1
DBy3
DAx0 DAx1 DAx2
DBx0 DBx1 DBx2
Writewith
DAy1 DAy2 DAy3
DBy0
DAz1
DAz0
DAx3
Activate
Command
Bank A
Write
Command
Bank A
Activate
Writewith
Auto Precharge
Command
Activate
Writewith
Activate
Writewith
Command Auto Precharge
Command Auto Precharge Command Auto Precharge
Bank B
Command
Bank B
Bank B
Command
Bank B
Bank A
Command
Bank A
Bank A
Preliminary
58
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 17.3. Auto Precharge after Write Burst
(Burst Length=4, CAS# Latency=3)
T11
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
`
A11
A9
RBx
RBx
RAx
RBy
CBy
RBy
CAx
CBx
CAy
RAx
A0~A9
DQM
DQ
Hi-Z
DAx0
DAy0
DAy2 DAy3
DAy1
DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3
DBy0
DBy2 DBy3
DBy1
Writewith
Activate
Writewith
Activate
Command
Bank B
Writewith
Activate
Command
Bank A
Auto Precharge
Command
Bank B
Auto Precharge
Command
Bank A
Auto Precharge
Command
Bank B
Command
Bank B
Write
Command
Bank A
Preliminary
59
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 18.1. Full Page Read Cycle
(Burst Length=Full Page, CAS# Latency=1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
High
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBy
RBy
RBx
RBx
RAx
CAx
CBx
A0~A9
DQM
RAx
tRP
tRRD
Hi-Z
DQ
Ax+2
Ax Ax+1
Bx
Bx+6 Bx+7
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Ax Ax+1
Ax-2 Ax-1
Activate
Activate
Command
Bank A
Read
Command
Bank B
Precharge
Command
Bank B
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this timeinterval
Full Page burst operation doesnot
Burst Stop
Activate
Command
Bank B
Read
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Command
Command
Bank A
Preliminary
60
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 18.2. Full Page Read Cycle
(Burst Length=Full Page, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBy
RBy
RBx
RBx
CBx
CAx
RAx
A0~A9
DQM
tRP
Hi-Z
DQ
Bx+6
Bx+2 Bx+3 Bx+4 Bx+5
Ax Ax+1 Bx
Ax
Ax-2 Ax-1
Bx+1
Ax+1 Ax+2
Activate
Read
Activate
Command
Bank B
Read
Precharge
Command
Bank B
Activate
Command
Bank B
Command Command
Command
Bank B
Full Page burst operation doesnot
Bank A
Bank A
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
The burst counter wraps
from the highest order
page address back to zero
during this timeinterval
Burst Stop
Command
Preliminary
61
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 18.3. Full Page Read Cycle
(Burst Length=Full Page, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBx
RBy
RBy
CAx
CBx
RAx
A0~A9
DQM
tRP
Hi-Z
Ax
Ax+1 Ax+2 Ax-2 Ax-1
Bx+5
Bx+4
Bx+3
DQ
Ax Ax+1
Bx+1 Bx+2
Bx
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
Full Page burst operation doesnot
terminate when the burst length is
satisfied; the burst counter
increments and continues
Theburst counter wraps
from the highest order
page address back to zero
during this timeinterval
bursting beginning with the
Burst Stop
Command
starting address.
Preliminary
62
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 19.1. Full Page Write Cycle
(Burst Length=Full Page, CAS# Latency=1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
High
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBy
RBy
RAx CAx RBx
CBx
A0~A9
DQM
Hi-Z
DBx+6
DBx+7
DAx+3 DAx-1
DAx+1
DAx
DBx+1 DBx+2 DBx+3 DBx+4
DBx
DBx+5
DAx+2
DAx+1
DQ
DAx
Activate
Command
Bank B
Data is ignored
Activate
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Burst Stop
Command
Theburst counter wraps
from the highest order
page address back to zero
during this timeinterval
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
Activate
Command
Bank B
Write
Command
Bank A
Preliminary
63
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 19.2. Full Page Write Cycle
(Burst Length=Full Page, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBy
RBy
RAx
RBx
RBx
CAx
CBx
RAx
A0~A9
DQM
Hi-Z
DBx+6
DAx+1 DAx+2
DBx+2
DBx+3 DBx+4 DBx+5
DAx
DAx+3 DAx-1 DAx DAx+1 DBx
DBx+1
DQ
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
Data is ignored
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
Burst Stop
Command
The burst counter wraps
from the highest order
page address back to zero
during this timeinterval
Preliminary
64
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 19.3. Full Page Write Cycle
(Burst Length=Full Page, CAS# Latency=3)
T16
T15
T19 T20 T21 T22
T17
T18
T0 T1 T2 T3 T4 T5 T6 T7 T8
T10 T11 T12 T13 T14
T9
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
A11
RBx
RBy
RBy
RAx
A10
CAx
RAx
RBx
CBx
A0~A9
DQM
DQ
Data is ignored
Hi-Z
DBx+5
DBx+4
DBx+2
DBx+3
DAx+2
DBx+1
DAx+1
DAx+3
DAx-1
DAx+1
DBx
DAx
DAx
Activate
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
Burst Stop
Command
Theburst counter wraps
from the highest order
page address back to zero
during this timeinterval
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
Preliminary
65
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 20. Byte Write Operation
(Burst Length=4, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
A11
RAx
A10
A0~A9
LDQM
CAy
RAx
CAx
CAz
UDQM
DQ0 - DQ7
Ax0 Ax1 Ax2
DAy1
DAy1
Az1
DAy2
Az2
Ax1
Az1 Az2 Az3
Ax2 Ax3
DAy0
DAy3
Az0
DQ8 - DQ15
Upper 3 Bytes
are masked
Activate
Command
Bank A
Read
Command
Bank A
Write
Command
Bank A
Lower Byte
is masked
Upper 3 Bytes
Read
Lower Byte
is masked
Lower Byte
is masked
are masked Command
Bank A
Preliminary
66
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 21. Random Row Read (Interleaving Banks)
(Burst Length=2, CAS# Latency=1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
High
Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto
CKE
CS#
Precharge
Bank B
Precharge
Bank A
Precharge
Bank B
Precharge
Bank A
Precharge
Bank B
Precharge
Bank A
Precharge
Bank B
Precharge
Bank A
Precharge
Bank B
Precharge
Bank A
RAS#
CAS#
WE#
A11
RAu
RAv
RBw
RBw
RAx
RAx
RBy
RAy
RBz
RAz
RBu
RBx
RBv
RAw
A10
CAu
t
RBu CBu RAu
RAv CAv
CAw RBx CBx
CAx RBy CBy RAy CAy RBz CBz RAz
RBv CBv
CBw
t
RAw
A0~A8
t
t
t
t
t
t
t
t
RP
RP
RP
RP
RP
RP
RP
RP
RP
RP
DQM
DQ
Bu0 Bu1 Au0 Au1
Bv1 Av0 Av1 Bw0 Bw1 Aw0 Aw1 Bx0 Bx1
Ax0 Ax1 By0 By1 Ay0 Ay1 Bz0
Bv0
Activate
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Read
Bank B
with Auto
Precharge
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Bank A
Bank B
Bank A
with Auto
Precharge
Bank B
with Auto
Precharge
Bank A
with Auto
Precharge
Bank B
with Auto
Precharge
Bank A
with Auto
Precharge
Bank B
with Auto
Precharge
Bank A
with Auto
Precharge
Bank B
with Auto
Precharge
with Auto
Precharge Precharge
with Auto
Preliminary
67
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 22. Full Page Random Column Read
(Burst Length=Full Page, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK2
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
RBx
RBw
RBw
RBx CAx
CAz
CBx
CBy
CBz
CAy
A0~A8
tRP
DQM
DQ
tRRD
tRCD
Ax0
Ay0
Az0
Az2
Bz1 Bz2
Bx0
Ay1
By1
Az1
Bz0
By0
Activate
Read
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command Bank B
(Precharge Temination)
Activate
Command
Bank A
Command
Bank B
Command
Bank B
Read
Read
Activate
Command
Bank B
Command
Bank A
Command
Bank A
Preliminary
68
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 23. Full Page Random Column Write
(Burst Length=Full Page, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBw
RBw
RAx
RAx
RBx
RBx
CBx CAy
CBy
CAz
CAx
CBz
A0~A9
DQM
tRP
tWR
tRRD
tRCD
DQ
DAx0
DBx0
Write
DAy1
DBy1 DAz0
Write
DAz2
DAz1
DAy0
DBz1 DBz2
DBy0
Write
DBz0
Write
Activate
Command
Bank B
Precharge
Activate
Command
Bank A
Command
Bank B
Command
Bank B
Command
Bank A
Command
Bank B
Command Bank B
(Precharge Temination)
Write
Write
Command
Bank A
Activate
Command
Bank B
Command
Bank A
Write Data
is masked
Preliminary
69
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 24.1. Precharge Termination of a Burst
(Burst Length=Full Page, CAS# Latency=1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CAS#
WE#
A11
A10
RAy
RAx
RAz
RAz
CAz
Precharge
Termination of
a Read Burst.
RAy CAy
RAx CAx
A0~A9
tWR
tRP
tRP
DQM
DQ
DAx0
Ay2
Ay0 Ay1
DAz0 DAz1
DAz7
DAx1 DAx2 DAx3 DAx4
DAz2 DAz3 DAz4 DAz5 DAz6
Read
Write
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Precharge
Command
Bank A
Precharge Termination
of a Write Burst.
Command
Bank A
Write data is masked.
Activate
Command
Bank A
Activate
Command
Bank A
Command
Bank A
Preliminary
70
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 24.2. Precharge Termination of a Burst
(Burst Length=8 or Full Page, CAS# Latency=2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
CK2
t
High
RAS#
CAS#
WE#
A11
A10
RAy
RAy
RAz
RAx
CAx
CAy
RAz
RAx
CAz
A0~A8
WR
tRP
t
RP
t
RP
t
DQM
DQ
DAx2
Az0 Az1 Az2
DAx1
DAx3
DAx0
Write
Ay0 Ay1 Ay2
Read
Command
Bank A
Precharge
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Command
Bank A
Precharge Termination
of a Write Burst.
Write data is masked.
Precharge Termination
of a Read Burst
Preliminary
71
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
Figure 24.3. Precharge Termination of a Burst
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CK3
t
High
CKE
CS#
RAS#
CAS#
WE#
A11
RAx
RAy
RAy
RAz
RAz
A10
CAy
RAx
CAx
A0~A9
WR
t
RP
RP
t
t
DQM
DQ
DAx1
Ay0 Ay1
DAx0
Ay2
Read
Command
Bank A
Precharge
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
Precharge Termination
of a Read Burst
Precharge Termination
of a Write Burst
Write Data
is masked
Preliminary
72
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
50 Pin TSOP II Package Outline Drawing Information
50
26
θ°
L
L1
1
25
D
L
L1
e
S
B
y
Symbol
Dimension in inch
Normal
Dimension in mm
Normal
Min
Max
Min
Max
0.048
1.20
A
A1
A2
B
0.002
0.037
0.012
0.005
0.008
0.042
0.018
0.05
0.94
0.3
0.125
0.20
1.07
0.45
0.015
0.006
0.825
0.400
0.031
0.375
0.155
20.95
10.16
0.80
c
0.82
0.395
0.83
0.405
20.82
10.03
21.08
10.29
D
E
e
0.455
0.016
0.463
0.020
0.0315
0.035
0.471
0.024
11.56
0.40
11.76
0.50
0.80
0.88
11.96
0.60
HE
L
L1
S
0.004
0.10
y
θ
0°
5°
0°
5°
Notes :
1. Dimension D&E do not include interiead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
4. Controlling dimension : mm
Preliminary
73
Rev. 1.8
Nov 2001
Et r on Tech
EM636165
1M x 16 SDRAM
1Mx16 SDRAM Package Diagrams
60-Ball (6.4mm x 10.1mm)VFBGA
Units in mm
BO TTO M VIE W
A1 COR NER
0.08 M
0.16 M
C
C
A
B
TO P VIEW
A1 COR NER
= 0.30
1
7
6
5
4
3
2
1
2
3
4
5
6
7
J
K
L
J
K
L
M
N
P
R
M
N
P
R
0.65
A
3.90
B
0.10(4X)
C
0.10
C
SEATING P LAN E
C
]
Preliminary
74
Rev. 1.8
Nov 2001
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