XC17V02SERIES [ETC]
XC17V00 Series Configuration PROM ; XC17V00系列配置PROM\n
| 型号： | XC17V02SERIES |
| 厂家： | 
ETC |
| 描述： | XC17V00 Series Configuration PROM
|
| 文件： | 总13页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XC17V00 Series Configuration
PROM
0
8
DS073 (v1.5) October 9, 2001
Advance Product Specification
•
•
•
•
Available in compact plastic packages: VQ44, PC44,
PC20, VO8, and SO20
Features
•
One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages.
•
•
•
Simple interface to the FPGA
Cascadable for storing longer or multiple bitstreams
Dual configuration modes for the XC17V16 and
XC17V08 devices
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
-
-
Serial slow/fast configuration (up to 33 Mb/s)
Parallel (up to 264 Mb/s at 33 MHz)
•
•
Low-power CMOS Floating Gate process
3.3V supply voltage
•
Guaranteed 20 year life data retention
Description
Xilinx introduces the high-density XC17V00 family of config-
uration PROMs which provide an easy-to-use, cost-effec-
tive method for storing large Xilinx FPGA configuration
bitstreams. Initial devices in the 3.3V family are available in
16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See Figure 1
and Figure 2 for simplified block diagrams of the XC17V00
family.
When the FPGA is in SelectMAP mode, an external oscilla-
tor will generate the configuration clock that drives the
PROM and the FPGA. After the rising CCLK edge, data are
available on the PROMs DATA (D0-D7) pins. The data will
be clocked into the FPGA on the following rising edge of the
CCLK. A free-running oscillator may be used to drive CCLK.
See Figure 3.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to most commercial PROM programmers.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS073 (v1.5) October 9, 2001
www.xilinx.com
1
Advance Product Specification
1-800-255-7778
R
XC17V00 Series Configuration PROM
V
V
PP
GND
CC
RESET/
CEO
CE
OE
or
OE/
RESET
Address Counter
CLK
TC
EPROM
Cell
Matrix
OE
Output
DATA
DS073_01_072600
Figure 1: Simplified Block Diagram for XC17V04, XC17V02, and XC17V01 (does not show programming circuit)
V
V
PP
GND
CC
RESET/
OE
or
CEO
CE
OE/
RESET
Address Counter
CLK
TC
BUSY
EPROM
Cell
Matrix
OE
7
8
Output
D0 Data
(Serial or Parallel Mode)
7
D[1:7]
(SelectMAP Interface)
DS073_02_072600
Figure 2: Simplified Block Diagram for XC17V16 and XC17V08 (does not show programming circuit)
2
www.xilinx.com
DS073 (v1.5) October 9, 2001
1-800-255-7778
Advance Product Specification
R
XC17V00 Series Configuration PROM
BUSY (XC17V16 and XC17V08 only)
Pin Description
If BUSY pin is floating, the user must program the BUSY bit
which will cause BUSY pin to be internally tied to a
pull-down resistor. When asserted High, output data are
held and when BUSY pin goes Low, data output will
resume.
DATA[0:7]
Data output is in a high-impedance state when either CE or
OE are inactive. During programming, the D0 pin is I/O.
Note that OE can be programmed to be either active High or
active Low.
VPP
Note: XC17V04, XC17V02, and XC17V01 have serial output
only.
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read oper-
ation, this pin must be connected to VCC. Failure to do so
may lead to unpredictable, temperature-dependent opera-
tion and severe problems in circuit debugging. Do not leave
VPP floating!
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
RESET/OE
VCC and GND
When High, this input holds the address counter reset and
puts the DATA output in a high-impedance state. The polar-
ity of this input pin is programmable as either RESET/OE or
OE/RESET. To avoid confusion, this document describes
the pin as RESET/OE, although the opposite polarity is pos-
sible on all devices. When RESET is active, the address
counter is held at “0”, and puts the DATA output in a
high-impedance state. The polarity of this input is program-
mable. The default is active High RESET, but the preferred
option is active Low RESET, because it can connected to
the FPGAs INIT pin and a pullup resistor.
Positive supply and ground pins.
PROM Pinouts for XC17V16 and XC17V08
(Pins not listed are “no connect”)
Pin Name
BUSY
44-pin VQFP
44-pin PLCC
24
40
29
42
27
9
30
2
D0
D1
D2
D3
D4
D5
D6
D7
CLK
35
4
The polarity of this pin is controlled in the programmer inter-
face. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have differ-
ent methods to invert this pin.
33
15
31
20
25
5
25
14
19
43
13
CE
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-ICC standby mode.
RESET/OE
(OE/RESET)
19
CEO
Chip Enable output, to be connected to the CE input of the
next PROM in the daisy chain. This output is Low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will follow CE as long as OE is active. When OE goes
inactive, CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
Low.
CE
15
21
GND
CEO
VPP
VCC
6, 18, 28, 37, 41 3, 12, 24, 34, 43
21
35
27
41
8, 16, 17, 26, 36,
38
14, 22, 23, 32,
42, 44
Capacity
Devices
XC17V16
XC17V08
Configuration Bits
16,777,216
8,388,608
DS073 (v1.5) October 9, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
3
R
XC17V00 Series Configuration PROM
PROM Pinouts for XC17V04, XC17V02, and
Xilinx FPGAs and Compatible PROMs
XC17V01 (Pins not listed are “no connect”)
Configuration
Device
XCV400
Bits
PROM
8-pi 20-pin 20-pin 44-pin 44-pin
VOIC SOIC PLCC VQFP PLCC
2,546,048
3,607,968
4,715,616
6,127,744
630,048
XC17V04
XC17V04
XC17V08
XC17V08
XC17V01
XC17V01
XC17V01
XC17V02
XC17V04
XC17V04
XC17V04
XC17V08
XC17V08
XC17V08
XC17V16
XC17V16
XC17V16
XCV600
(1)
(1)
(1,2)
(2)
(2)
Pin Name
DATA
XCV800
1
2
3
1
3
8
1
3
8
40
43
13
2
5
XCV1000
XCV50E
CLK
XCV100E
XCV200E
XCV300E
XCV400E
XCV405E
XCV600E
XCV812E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
863,840
RESET/OE
(OE/RESET)
19
1,442,106
1,875,648
2,693,440
3,430,400
3,961,632
6,519,648
6,587,520
8,308,992
10,159,648
12,922,336
16,283,712
CE
4
5
6
7
8
10
11
13
18
20
10
11
13
18
20
15
18, 41
21
21
24, 3
27
GND
CEO
VPP
35
41
VCC
38
44
Notes:
1. XC17V01 available in these packages.
2. XC17V02 and XC17V04 available in these packages.
Capacity
Notes:
1. The suggested PROM is determined by compatibility with the
higher configuration frequency of the Xilinx FPGA CCLK.
Devices
XC17V04
XC17V02
XC17V01
Configuration Bits
4,194,304
Controlling PROMs
2,097,152
Connecting the FPGA device with the PROM.
1,679,360
•
The DATA output(s) of the PROM(s) drives the DIN
input of the lead FPGA device.
Xilinx FPGAs and Compatible PROMs
Configuration
•
•
•
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
Device
Bits
PROM
XC2V40
360,160
XC17V01
XC17V01
XC17V02
XC17V04
XC17V04
XC17V08
XC17V08
XC17V16
XC17V16
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
XC2V80
635,360
The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a VCC glitch.
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
1,697,248
2,761,952
4,082,656
5,659,360
7,492,064
10,494,432
15,660,000
21,849, 568
•
•
The PROM CE input is best connected to the FPGA
DONE pin(s) and a pullup resistor. CE can also be
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
15 mA maximum.
XC17V16 +
XC17V08
SelectMAP mode is similar to Slave Serial mode. The
DATA is clocked out of the PROM one byte per CCLK
instead of one bit per CCLK cycle. See FPGA data
sheets for special configuration requirements.
XC2V8000
XCV50
29,063,072
559,200
2 of XC17V16
XC17V01
XC17V01
XC17V01
XC17V01
XC17V02
XCV100
XCV150
XCV200
XCV300
781,216
1,040,096
1,335,840
1,751,808
4
www.xilinx.com
DS073 (v1.5) October 9, 2001
1-800-255-7778
Advance Product Specification
R
XC17V00 Series Configuration PROM
address and bit counters which are incremented on every
valid rising edge of CCLK.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the three FPGA mode pins. In Master Serial
mode, the FPGA automatically loads the configuration pro-
gram from an external memory. The Xilinx PROMs have
been designed for compatibility with the Master Serial
mode.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it must still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up/down resistor or keeper circuit.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded PROMs provide additional memory. After the last bit
from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See Figure 3.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA
mode-select pins are Low (M0=0, M1=0, M2=0). Data is
read from the PROM sequentially on a single data line. Syn-
chronization is provided by the rising edge of the temporary
signal CCLK, which is generated during configuration.
After configuration is complete, the address counters of all
cascaded PROMs are reset if the FPGA PROGRAM pin
goes Low, assuming the PROM reset polarity option has
been inverted.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line, two control lines, and a clock
line are required to configure an FPGA. Data from the
PROM is read sequentially, accessed via the internal
DS073 (v1.5) October 9, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
5
R
XC17V00 Series Configuration PROM
OPTIONAL
Daisy-chained
FPGAs with
different
DOUT
V
CC
configurations
4.7K
FPGA
OPTIONAL
V
CC
Slave FPGAs
with identical
configurations
4.7K
(1)
Modes
V
CC
V
CC
V
CC
(2)
V
CC
Vpp
V
CC
Vpp
DATA
CLK
CE
DIN
BUSY
BUSY
DATA
First
PROM
CCLK
DONE
CEO
Cascaded
PROM
CLK
CE
OE/RESET
INIT
OE/RESET
PROGRAM
(Low Resets the Address Pointer)
(1) For Mode pin connections, refer to the appropriate FPGA data sheet.
(2) Virtex, Virtex-E is 300 ohms, all others are 4.7K.
Master Serial Mode
(1)
I/O
(1)
V
V
V
V
I/O
CC
CC
External
Osc
CS
(4)
(3)
Modes
WRITE
1K
1K
VIRTEX
SelectMAP
3.3V
4.7K
Vpp
Vpp
BUSY
Second
CC
CC
V
CC
BUSY
BUSY
First
PROM
(2)
CLK
CLK
CCLK
D[0:7]
DONE
INIT
PROM
8
PROGRAM
CEO
CEO
D[0:7]
CE
D[0:7]
CE
OE/RESET
OE/RESET
(1) CS and WRITE must be pulled down to be used as I/O. One option is shown.
(2) Virtex, Virtex-E is 300 ohms, all others are 4.7K.
(3) For Mode pin connections, refer to the appropriate FPGA data sheet.
(4) External oscillator required for Virtex/E SelectMAP or Virtex-II slave SelectMAP modes.
DS073_03_100901
Virtex SelectMAP Mode, XC17V16 and XC17V08 only.
Figure 3: (a) Master Serial Mode (b) Virtex SelectMAP Mode
(dotted lines indicates optional connection)
6
www.xilinx.com
DS073 (v1.5) October 9, 2001
1-800-255-7778
Advance Product Specification
R
XC17V00 Series Configuration PROM
Standby Mode
Programming
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high impedance
state regardless of the state of the OE input.
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
Table 1: Truth Table for XC17V00 Control Inputs
Control Inputs
Outputs
RESET
CE
Internal Address
DATA
CEO
ICC
Inactive
Low
If address < TC(1): increment
If address > TC(1): don’t change
Active
High-Z
High
Low
Active
Reduced
Active
Inactive
Active
Low
High
High
Held reset
Not changing
Held reset
High-Z
High-Z
High-Z
High
High
High
Active
Standby
Standby
Notes:
1. The XC17V00 RESET input has programmable polarity
1. TC = Terminal Count = highest address value. TC + 1 = address 0.
DS073 (v1.5) October 9, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
7
R
XC17V00 Series Configuration PROM
Absolute Maximum Ratings
Symbol
Description
Conditions
–0.5 to +7.0
–0.5 to +12.5
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–65 to +150
+260
Units
VCC
VPP
VIN
Supply voltage relative to GND
Supply voltage relative to GND
V
V
V
V
C
C
Input voltage relative to GND
VTS
Voltage applied to High-Z output
Storage temperature (ambient)
TSTG
TSOL
Maximum soldering temperature (10s @ 1/16 in.)
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions (3V Supply)
Symbol
Description
Min
3.0
3.0
1.0
Max
3.6
3.6
50
Units
V
(1)
VCC
Supply voltage relative to GND (TA = 0 C to +70 C)
Supply voltage relative to GND (TA = –40 C to +85 C)
VCC rise time from 0V to nominal voltage
Commercial
Industrial
V
TVCC
ms
Notes:
1. During normal read operation VPP must be connected to VCC.
2. At power up, the device requires the VCC power supply to monotonically rise from 0V to nominal voltage within the specified VCC rise
time. If the power supply cannot meet this requirement, then the device may not power-on-reset properly.
DC Characteristics Over Operating Condition
Symbol
VIH
Description
Min
Max
VCC
0.8
-
Units
V
High-level input voltage
Low-level input voltage
2
0
VIL
V
VOH
VOL
High-level output voltage (IOH = –3 mA)
2.4
-
V
Low-level output voltage (IOL = +3 mA)
0.4
100
V
ICCA
Supply current, active mode (at maximum frequency)
-
mA
(XC17V16 and XC17V08 only)
ICCA
Supply current, active mode (at maximum frequency)
-
15
mA
(XC17V04, XC17V02, and XC17V01 only)
ICCS
IL
Supply current, standby mode
-
1
mA
A
Input or output leakage current
–10
10
15
15
CIN
Input capacitance (VIN = GND, f = 1.0 MHz)
Output capacitance (VIN = GND, f = 1.0 MHz)
-
-
pF
pF
COUT
8
www.xilinx.com
DS073 (v1.5) October 9, 2001
1-800-255-7778
Advance Product Specification
R
XC17V00 Series Configuration PROM
AC Characteristics Over Operating Condition for XC17V04, XC17V02, and
XC17V01
CE
T
T
T
HCE
SCE
SCE
RESET/OE
CLK
T
HOE
T
T
HC
LC
T
CYC
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
OH
DS073_04_072600
Symbol
Description
Min
Max
Units
ns
TOE
TCE
OE to data delay
CE to data delay
CLK to data delay
-
-
30
45
45
50
-
ns
TCAC
TDF
-
ns
CE or OE to data float delay(2,3)
Data hold from CE, OE, or CLK(3)
Clock periods
-
ns
TOH
0
ns
TCYC
TLC
67
25
25
25
0
-
ns
CLK Low time(3)
-
ns
THC
CLK High time(3)
-
ns
TSCE
THCE
THOE
Notes:
CE setup time to CLK (to guarantee proper counting)
CE hold time to CLK (to guarantee proper counting)
OE hold time (guarantees counters are reset)
-
ns
-
ns
25
-
ns
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
DS073 (v1.5) October 9, 2001
www.xilinx.com
9
Advance Product Specification
1-800-255-7778
R
XC17V00 Series Configuration PROM
AC Characteristics Over Operating Condition for XC17V16 and XC17V08
CE
T
T
T
HCE
SCE
SCE
RESET/OE
CLK
T
HOE
T
T
HC
LC
T
CYC
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
T
SBUSY
OH
T
HBUSY
BUSY
DS073_05_072600
Symbol
Description
Min
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TOE
TCE
OE to data delay
CE to data delay
CLK to data delay(2)
-
-
15
20
20
35
-
TCAC
TDF
-
CE or OE to data float delay(3,4)
Data hold from CE, OE, or CLK(4)
Clock periods
-
TOH
0
TCYC
TLC
50
25
25
25
0
-
CLK Low time(4)
-
THC
CLK High time(4)
-
TSCE
THCE
THOE
CE setup time to CLK (to guarantee proper counting)
CE hold time to CLK (to guarantee proper counting)
OE hold time (guarantees counters are reset)
-
-
25
5
-
TSBUSY BUSY setup time
THBUSY BUSY hold time
-
5
-
Notes:
1. AC test load = 50 pF.
2. When BUSY = 0.
3. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
4. Guaranteed by design, not tested.
5. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
10
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DS073 (v1.5) October 9, 2001
1-800-255-7778
Advance Product Specification
R
XC17V00 Series Configuration PROM
AC Characteristics Over Operating Condition When Cascading
OE/RESET
CE
CLK
T
CDF
T
T
OCE
Last Bit
First Bit
DATA
CEO
T
OCK
OOE
DS026_07_020300
Symbol
TCDF
Description
Min
Max
50
Units
ns
CLK to data float delay(2,3)
CLK to CEO delay(3)
-
-
-
-
TOCK
30
ns
TOCE
CE to CEO delay(3)
35
ns
TOOE
RESET/OE to CEO delay(3)
30
ns
Notes:
1. AC test load = 50 pF
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady
state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
DS073 (v1.5) October 9, 2001
www.xilinx.com
11
Advance Product Specification
1-800-255-7778
R
XC17V00 Series Configuration PROM
Ordering Information
XC17V16 PC44 C
Device Number
Operating Range/Processing
XC17V16
XC17V08
XC17V04
XC17V02
XC17V01
C = Commercial (TA = 0 to +70 C)
I = Industrial (TA = –40 to +85 C)
Package Type
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
V08 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
SO20 = 20-pin Plastic Small Outline Package
Valid Ordering Combinations
XC17V16VQ44C
XC17V16PC44C
XC17V16VQ44I
XC17V16PC44I
XC17V08VQ44C
XC17V08PC44C
XC17V08VQ44I
XC17V08PC44I
XC17V04PC20C
XC17V04PC44C
XC17V04VQ44C
XC17V04PC20I
XC17V04PC44I
XC17V04VQ44I
XC17V02PC20C
XC17V02PC44C
XC17V02VQ44C
XC17V02PC20I
XC17V02PC44I
XC17V02VQ44I
XC17V01PC20C
XC17V01VO8C
XC17V01SO20C
XC17V01PC20I
XC17V01VO8I
XC17V01SO20I
Marking Information
Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on
the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:
XC17V16 PC44 C
Device Number
Operating Range/Processing
XC17V16
XC17V08
XC17V04
XC17V02
XC17V01
C = Commercial (TA = 0 to +70 C)
I = Industrial (TA = –40 to +85 C)
Package Type
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
V08 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
SO20 = 20-pin Plastic Small Outline Package
12
www.xilinx.com
DS073 (v1.5) October 9, 2001
1-800-255-7778
Advance Product Specification
R
XC17V00 Series Configuration PROM
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
07/26/00
10/09/00
11/16/00
Initial Xilinx release.
1.1
Updated 20-pin PLCC Pinouts.
1.2
Updated pinouts for XC17V16 and XC17V08, ICCA DC Characteristic from standby to active
mode; CIN and COUT from 10 pF to 15 pF, added ICCS for XC17V16 and XC17V08 at 500 A.
02/20/01
04/04/01
1.3
1.4
Added note to pinouts for “no connect,” updated Figure 3.
Added XC2V products to Compatible PROM table, updated Figure 3, updated text for
Virtex-II FPGAs.
10/09/01
1.5
Corrected bitstream length for SCV405E, added power-on supply requirements and note for
power-on reset, updated configuration bits for Virtex-II devices, removed CF from Figure 3,
and updated FPGA list.
DS073 (v1.5) October 9, 2001
www.xilinx.com
13
Advance Product Specification
1-800-255-7778
相关型号：
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