WF128K16-70CI5 [ETC]
5V FLASH MODULE; 5V闪存模块
| 型号： | WF128K16-70CI5 |
| 厂家： | 
ETC |
| 描述： | 5V FLASH MODULE |
| 文件： | 总11页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WF128K16, WF256K16-XCX5
5V FLASH MODULE
PRELIMINARY *
FEATURES
■ Access Times of 50, 60, 70, 90, 120 and 150ns
■ 5 Volt Programming; 5V ±10% Supply
■ 40 pin Ceramic DIP (Package 303)
■ Low Power CMOS
■ Organized as 128Kx16 and 256Kx16
■ Embedded Erase and Program Algorithms
■ TTL Compatible Inputs and CMOS Outputs
■ Sector Architecture
• 8 equal size sectors of 16KBytes each per chip
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
■ Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
■ Page Program Operation and Internal Program Control Time
*
This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
■ 100,000 Erase/Program Cycles Minimum (0°C to 70°C)
■ Data Retention, 10 Years at 125°C
Note: Programming information available upon request.
■ Commercial, Industrial and Military Temperature Ranges
FIG. 1 PIN CONFIGURATION AND BLOCK DIAGRAM
TOP VIEW
PIN DESCRIPTION
V
CC
CS2*/NC
CS1
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
WE
A16
A15
A14
A13
A12
A11
A10
A9
2
A0-16
I/O0-15
CS1-2
OE
Address Inputs
Data Input/Output
Chip Selects
Output Enable
Write Enable
+5.0V Power
Ground
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
3
4
5
6
7
8
WE
9
I/O8
10
11
12
13
14
15
16
17
18
19
20
VCC
GND
A8
GND
I/O7
GND
A7
I/O6
A6
I/O5
A5
I/O4
A4
I/O3
A3
I/O2
BLOCK DIAGRAM
FOR WF256K16-XCX5
A2
I/O1
A1
I/O0
A0
OE
I/O0-7
I/O8-15
* CS2 for 256Kx16 and NC for 128Kx16
WE
OE
BLOCK DIAGRAM
FOR WF128K16-XCX5
A
0-16
I/O0-7
I/O8-15
WE
128K x 8
128K x 8
128K x 8
128K x 8
OE
0-16
A
CS1(1)
CS2(1)
128K x 8
128K x 8
NOTE:
1. CS1 and CS2 are used to select the lower and upper 128Kx16 of the
device. CS1 and CS2 must not be enabled at the same time.
CS
1
October 1998
1
White Microelectronics • Phoenix, AZ • (602) 437-1520
WF128K16, WF256K16-XCX5
ABSOLUTE MAXIMUM RATINGS (1)
CAPACITANCE
(TA = 25°C)
Parameter
Unit
°C
V
Operating Temperature
-55 to +125
-2.0 to +7.0
-2.0 to +7.0
-65 to +150
+300
Test
Symbol
COE
Conditions
Max Unit
Supply Voltage Range (VCC)
OE capacitance
WE capacitance
CS capacitance
I/O0-7 capacitance
V
V
V
IN = 0 V, f = 1.0 MHz
IN = 0 V, f = 1.0 MHz
IN = 0 V, f = 1.0 MHz
50
50
30
30
pF
pF
pF
pF
Signal voltage range (any pin except A9) (2)
Storage Temperature Range
V
CWE
°C
°C
CCS
Lead Temperature (soldering, 10 seconds)
Data Retention Mil Temp
CI/O
V
V
I/O = 0 V, f = 1.0 MHz
IN = 0 V, f = 1.0 MHz
10 years
Address capacitance
CAD
50
pF
Endurance (write/erase cycles) Mil Temp
A9 Voltage for sector protect (VID) (3)
10,000 cycles min.
-2.0 to +14.0
This parameter is guaranteed by design but not tested.
V
NOTES:
1. Stresses above the absolute maximum rating may cause permanent damage
to the device. Extended operation at the maximum levels may degrade
performance and affect reliability.
2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions,
inputs may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC
voltage on output and I/O pins is VCC + 0.5V. During voltage transitions,
outputs may overshoot to Vcc + 2.0 V for periods of up to 20ns.
3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may
overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A9
is +13.5V which may overshoot to 14.0 V for periods up to 20ns.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VCC
VIH
VIL
Min
4.5
Max
5.5
Unit
Supply Voltage
V
V
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
A9 Voltage for Sector Protect
2.0
VCC + 0.3
+0.8
-0.5
-55
-40
11.5
V
TA
+125
+85
°C
°C
V
TA
VID
12.5
DC CHARACTERISTICS - CMOS COMPATIBLE
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
Conditions
128K x 16
256K x 16
Unit
Min
Max
10
Min
Max
10
Input Leakage Current
ILI
ILO
VCC = 5.5, VIN = GND to VCC
VCC = 5.5, VIN = GND to VCC
CS = VIL, OE = VIH
µA
µA
Output Leakage Current
VCC Active Current for Read (1)
10
10
ICC1
ICC2
70
80
mA
mA
VCC Active Current for Program
or Erase (2)
CS = VIL, OE = VIH
100
110
VCC Standby Current
Output Low Voltage
ICC3
VOL
VCC = 5.5, CS = VIH, f = 5MHz
IOL = 12.0 mA, VCC = 4.5
6
8
mA
V
0.45
0.45
Output High Voltage
Output High Voltage
VOH1
VOH2
IOH = -2.5 mA, VCC = 4.5
0.85xVcc
VCC -0.4
0.85xVcc
V
V
IOH = -100 µA, VCC = 4.5
VCC -0.4
Low VCC Lock Out Voltage
VLKO
3.2
3.2
V
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
White Microelectronics • Phoenix, AZ • (602) 437-1520
2
WF128K16, WF256K16-XCX5
WRITE
PRINCIPLES OF OPERATION
Device erasure and programming are accomplished via the
command register. The contents of the register serve as input
to the internal state machine. The state machine outputs
dictate the function of the device.
The following principles of operation of the WF128K16-XCX5
and WF256K16-XCX5 are applicable to each 128K x 8 memory
chip inside the MCM. Programming of the device is accom-
plished by executing the program command sequence. The
program algorithm, which is an internal algorithm, automati-
cally times the program pulse widths and verifies proper cell
margin. Sectors can be programmed and verified in less than 0.3
seconds. Erase is accomplished by executing the erase
command sequence. The erase algorithm, which is internal,
automatically preprograms the array if it is not already
programmed before executing the erase operation. During
erase, the device automatically times the erase pulse widths
and verifies proper cell margin. The entire memory is typically
erased and verified in three seconds (including pre-program-
ming).
The command register itself does not occupy an addressable
memory location. The register is a latch used to store the
commands, along with address and data information needed to
execute the command. The command register is written by
bringing Write-Enable to a logic-low level (VIL), while Chip-Select
is low and OE is at VIH. Addresses are latched on the falling edge
of the Write-Enable while data is latched on the rising edge of the
WE pulse. Standard microprocessor write timings are used. Refer
to AC Program characteristics, Figures 4 and 7.
BUS OPERATIONS
READ
The device has two control functions, both of which must be
logically active, to obtain data at the outputs. Chip-Select (CS)
is the power control and should be used for device selection.
Output-Enable (OE) is the output control and should be used to
gate data to the output pins. Figure 3 illustrates read timing
waveforms.
OUTPUT DISABLE
With Output-Enable at a logic-high level (VIH), output from the
device is disabled. Output pins are placed in a high
impedance state.
STANDBY MODE
The device has two standby modes, a CMOS standby mode (CS
input held at VCC + 0.5V), and a TTL standby mode (CS is held
VIH). In the standby mode the outputs are in a high impedance
state, independent of the OE input.
If the device is deselected during erasure or programming, the
device will draw active current until the operation is completed.
TABLE 1 - BUS OPERATIONS
Operation
CS OE WE A0 A1
A9
A9
X
I/O
DOUT
HIGH Z
HIGH Z
DIN
Read
L
H
L
L
L
L
L
X
H
X
H
L
A0
X
A1
X
Standby
Output Disable
Write
H
X
X
X
H
A0
X
A1
X
A9
VID
VID
Enable Sector Protect
Verify Sector Protect
VID
L
L
X
H
L
H
Code
3
White Microelectronics • Phoenix, AZ • (602) 437-1520
WF128K16, WF256K16-XCX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
-50
-60
-70
-90
-120
-150
Unit
Min Max
Min Max Min
Max Min Max Min Max
Min Max
Write Cycle Time
tAVAV
tWC
50
0
60
0
70
0
90
0
120
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
ns
µs
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
tELWL tCS
tWLWH tWP
tAVWL tAS
tDVWH tDS
tWHDX tDH
tWLAX tAH
tWHEH tCH
tWHWL tWPH
tWHWH1
25
0
30
0
35
0
45
0
50
0
50
0
Data Setup Time
25
0
30
0
30
0
45
0
50
0
50
0
Data Hold Time
Address Hold Time
40
0
45
0
45
0
45
0
50
0
50
0
Chip Select Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (min)
Chip and Sector Erase Time
Read Recovery Time Before Write
VCC Setup Time
20
14
20
14
2.2
0
20
14
2.2
0
20
14
2.2
0
20
14
2.2
0
20
14
tWHWH2
2.2
0
60
60
60
60
60
2.2
0
60
tGHWL
tVCS
50
50
50
50
50
50
Chip Programming Time
Output Enable Setup Time
Output Enable Hold Time (1)
1. For Toggle and Data Polling.
12.5
12.5
12.5
12.5
12.5
12.5 sec
tOES
0
0
0
0
0
0
ns
ns
tOEH
10
10
10
10
10
10
AC CHARACTERISTICS – READ ONLY OPERATIONS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
-50
Min Max Min Max
50 60
-60
-70
Min Max Min Max
70 90
-90
-120
-150
Unit
Min Max
Min Max
Read Cycle Time
tAVAV
tRC
tACC
tCE
tOE
tDF
tDF
tOH
120
120
120
50
150
150
150
55
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
50
50
25
20
20
60
60
30
20
20
70
70
35
20
20
90
90
40
25
25
Chip Select Access Time
OE to Output Valid
Chip Select to Output High Z (1)
OE High to Output High Z (1)
30
35
30
35
Output Hold from Address, CS or OE Change,
whichever is first
0
0
0
0
0
0
1. Guaranteed by design, not tested.
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
WF128K16, WF256K16-XCX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
-50
Min
-60
-70
-90
-120
Max Min Max
120
-150
Min Max
150
Unit
Max Min Max Min
Max Min
Write Cycle Time
tAVAV
tWC
50
0
60
0
70
0
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
ns
WE Setup Time
tWLEL tWS
0
0
50
0
0
50
0
CS Pulse Width
tELEH
tAVEL
tDVEH
tEHDX
tELAX
tCP
tAS
tDS
tDH
tAH
25
0
30
0
35
0
45
Address Setup Time
Data Setup Time
0
25
0
30
0
30
0
45
50
0
50
0
Data Hold Time
0
Address Hold Time
40
0
45
0
45
0
45
50
0
50
0
WE Hold from WE High
CS Pulse Width High
Duration of Programming Operation
Duration of Erase Operation
Read Recovery before Write
Chip Programming Time
tEHWH tWH
0
tEHEL
tWHWH1
tWHWH2
tGHEL
tCPH
20
14
2.2
0
20
14
2.2
0
20
14
2.2
0
20
14
20
14
20
14
60
60
60 2.2
0
60
2.2
0
60
2.2
0
60
12.5
12.5
12.5
12.5
12.5
12.5 sec
AC TEST CONDITIONS
FIG. 2
AC TEST CIRCUIT
Parameter
Typ
Unit
V
IOL
Current Source
Input Pulse Levels
VIL = 0, VIH = 3.0
Input Rise and Fall
5
ns
V
Input and Output Reference Level
Output Timing Reference Level
1.5
1.5
V
D.U.T.
VZ
≈
1.5V
(Bipolar Supply)
Ceff = 50 pf
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
IOH
Current Source
5
White Microelectronics • Phoenix, AZ • (602) 437-1520
WF128K16, WF256K16-XCX5
FIG. 3
AC WAVEFORMS FOR READ OPERATIONS
White Microelectronics • Phoenix, AZ • (602) 437-1520
6
WF128K16, WF256K16-XCX5
FIG. 4
AC WAVEFORMS FOR WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED
NOTES:
1. PA is the address of the memory location
to be programmed.
2. PD is the data to be programmed.
3. D7 is the output of the complement of the
data written (for each chip).
4. DOUT is the output of the data written to
the device.
5. Figure indicates last two bus cycles of four bus
cycle sequence.
7
White Microelectronics • Phoenix, AZ • (602) 437-1520
WF128K16, WF256K16-XCX5
FIG. 5
AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
NOTES:
1. SA is the sector address
for Sector Erase.
White Microelectronics • Phoenix, AZ • (602) 437-1520
8
WF128K16, WF256K16-XCX5
FIG. 6
AC WAVEFORMS FOR DATA POLLING DURING
EMBEDDED ALGORITHM OPERATIONS
9
White Microelectronics • Phoenix, AZ • (602) 437-1520
WF128K16, WF256K16-XCX5
FIG. 7
AC WAVEFORMS FOR WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to the device (for each chip).
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
White Microelectronics • Phoenix, AZ • (602) 437-1520
10
WF128K16, WF256K16-XCX5
PACKAGE 303: 40 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED
51.3 (2.020) ± 0.5 (0.020)
15.1 (0.595)
± 0.25 (0.010)
7.2 (0.285)
± 0.8 (0.030)
PIN 1 IDENTIFIER
3.2 (0.125) MIN
0.25 (0.010)
± 0.05 (0.002)
0.94 (0.037)
± 0.25 (0.010)
15.25 (0.600)
2.5 (0.100)
TYP
1.27 (0.050)
± 0.1 (0.005)
0.5 (0.018)
± 0.05 (0.002)
± 0.25 (0.010)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
W F XXXK16 - XXX C X 5 X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
VPP PROGRAMMING VOLTAGE
5 = 5V
DEVICE GRADE:
Q = Compliant
M = Military Screened -55°C to 125°C
I
=
Industrial
-40°C to +85°C
0 to +70°C
C = Commercial
PACKAGE TYPE:
C = 40 Pin Ceramic 0.600" DIP (Package 303)
ACCESS TIME (ns)
ORGANIZATION, 128K x 16 or 256K x 16
Flash PROM
WHITE MICROELECTRONICS
11
White Microelectronics • Phoenix, AZ • (602) 437-1520
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