WE128K8-XCX [ETC]
EEPROM MCP ; EEPROM MCP\n
| 型号： | WE128K8-XCX |
| 厂家： | 
ETC |
| 描述： | EEPROM MCP
|
| 文件： | 总13页 (文件大小：622K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WE512K8, WE256K8,
WE128K8-XCX
512Kx8 CMOS EEPROM, WE512K8-XCX, SMD 5962-93091
512KX8 BIT CMOS EEPROM
MODULE
FIGꢀ 1
PIN CONFIGURATION
FEATURES
TOP VIEW
■
Read Access Times of 150, 200, 250, 300ns
■
JEDEC Standard 32 Pin, Hermetic Ceramic DIP
(Package 300)
■
Commercial, Industrial and Military Temperature
Ranges
■
■
■
■
MIL-STD-883 Compliant Devices Available
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation:
3mA Standby Typical/100mA Operating Maximum
Automatic Page Write Operation
■
Internal Address and Data Latches for
512 Bytes, 1 to 128 Bytes/Row, Four Pages
Page Write Cycle Time 10mS Maxꢀ
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
PIN DESCRIPTION
Address Inputs
■
■
■
■
A0-18
I/O0- 7
CS
Data Input/Output
Chip Select
OE
Output Enable
Write Enable
+5!0V Power
Ground
WE
VCC
VSS
BLOCK DIAGRAM
1
White Electronic Designs Corporation (602) 437-1520 wwwꢀwhiteedcꢀcom
May 2000 Rev.1
WE512K8, WE256K8,
WE128K8-XCX
256Kx8 CMOS EEPROM, WE256K8-XCX, SMD 5962-93155
256KX8 BIT CMOS EEPROM
MODULE
FIGꢀ2
PIN CONFIGURATION
FEATURES
TOP VIEW
■
■
Read Access Times of 150, 200ns
JEDEC Standard 32 Pin, Hermetic Ceramic DIP
(Package 302)
■
Commercial, Industrial and Military Temperature
Ranges
■
■
■
■
MIL-STD-883 Compliant Devices Available
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation:
2mA Standby Typical/90mA Operating Maximum
Automatic Page Write Operation
■
Internal Address and Data Latches for
512 Bytes, 1 to 64 Bytes/Row, Eight Pages
Page Write Cycle Time 10mS Maxꢀ
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
PIN DESCRIPTION
Address Inputs
■
■
■
■
A0-17
I/O0-7
CS
Data Input/Output
Chip Select
OE
Output Enable
Write Enable
+5!0V Power
Ground
WE
VCC
VSS
BLOCK DIAGRAM
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
2
WE512K8, WE256K8,
WE128K8-XCX
128Kx8 CMOS EEPROM, WE128K8-XCX, SMD 5962-93154
128KX8 BIT CMOS EEPROM
MODULE
FIGꢀ 3
PIN CONFIGURATION
FEATURES
TOP VIEW
■
■
Read Access Times of 150, 200ns
JEDEC Standard 32 Pin, Hermetic Ceramic DIP
(Package 300)
■
Commercial, Industrial and Military Temperature
Ranges
■
■
■
■
MIL-STD-883 Compliant Devices Available
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation:
1mA Standby Typical/70mA Operating
Automatic Page Write Operation
■
Internal Address and Data Latches for
256 Bytes, 1 to 64 Bytes/Row, Four Pages
Page Write Cycle Time 10mS Maxꢀ
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
PIN DESCRIPTION
Address Inputs
■
■
■
■
A0-16
I/O0-7
CS
Data Input/Output
Chip Select
OE
Output Enable
Write Enable
+5!0V Power
Ground
WE
VCC
VSS
BLOCK DIAGRAM
3
White Electronic Designs Corporation (602) 437-1520 wwwꢀwhiteedcꢀcom
WE512K8, WE256K8,
WE128K8-XCX
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Parameter
Symbol
Unit
°C
°C
+
CS
H
L
OE
X
WE
X
Mode
Standby
Read
Data I/O
High Z
Operating Temperature
Storage Temperature
Signal Voltage Any Pin
TA
TSTG
VG
-55 to +125
-65 to +150
L
H
L
Data Out
-0!6
and
to
A9
6!25
-0!6
V
L
H
H
X
Write
Data In
Voltage
on
OE
qJC
to
+13!5
V
X
X
Out Disable
Write
High Z/Data Out
Thermal Resistance
junction to case
28
°C/W
°C
X
H
X
X
L
Inhibit
Lead Temperature
(soldering -10 secs)
+300
CAPACITANCE
(TA = +25°C)
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the deviceꢀ This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not impliedꢀ Exposure to absolute maximum rating conditions for
extended periods may affect device reliabilityꢀ
Parameter
Sym
Condition
512Kx8 256Kx8 128Kx8 Unit
Max
Max
Max
Input Capacitance
CIN VIN = 0V, f = 1MHz
45
80
45
pF
pF
Output Capacitance COUT VI/O = 0V, f = 1MHz
60
80
60
This parameter is guaranteed by design but not testedꢀ
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VCCV!5
VIH
Min
4!55
2!0
Max
Unit
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp! (Mil!)
Operating Temp! (Ind!)
VCC + 0!3
+0!8
V
V
VIL
-0!3
-55
TA
+125
°C
TA
-40
+85°C
DC CHARACTERISTICS
(VCC = 5ꢀ0V, VSS = 0V, TA = -55°C TO +125°C)
Parameter
Symbol Conditions
512K x 8
256K x 8
128K x 8
Unit
Min Typ Max Min Typ Max Min Typ Max
Input Leakage Current
Output Leakage Current
Dynamic Supply Current
Standby Current
ILI
ILO
VCC = 5!5, VIN = GND to VCC
10
10
10
10
10
10
µA
µA
mA
mA
V
CS = VIH, OE = VIH, VOUT = GND to VCC
CS = VIL, OE = VIH, f = 5MHz, VCC = 5!5
CS = VIL, OE = VIH, f = 5MHz, VCC = 5!5
IOL = 2!1mA, VCC = 4!5V
ICC
ISB
80 100
60 90
50
1
70
3
8
2
6
4
Output Low Voltage
Output High Voltage
VOL
VOH
0!45
0!45
0!45
IOH = -400µA, VCC = 4!5V
2!4
2!4
2!4
V
NOTE: DC test conditions: VIH = VCC -0ꢀ3V, VIL = 0ꢀ3V
AC TEST CONDITIONS
Typ
FIGꢀ 4
AC TEST CIRCUIT
Parameter
Unit
Input Pulse Levels
VIL = 0, VIH = 3!0
V
Input
Rise
and
Timing
and
Fall
Input
Output
Reference
Level
Output
Reference
Level
1
Notes:
VZ is programmable from -2V to +7Vꢀ
IOL & IOH programmable from 0 to 16mAꢀ
Tester Impedance Z0 = 75 ýꢀ
VZ is typically the midpoint of VOH and VOLꢀ
IOL & IOH are adjusted to simulate a typical resistive load circuitꢀ
ATE tester includes jig capacitanceꢀ
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
4
WE512K8, WE256K8,
WE128K8-XCX
READ
Figure 5 shows Read cycle waveformsꢀ A read cycle be-
gins with selection address, chip select and output en-
ableꢀ Chip select is accomplished by placing the CS line
lowꢀ Output enable is done by placing the OE line lowꢀ
The memory places the selected data byte on I/O0
through I/O7 after the access timeꢀ The output of the
memory is placed in a high impedance state shortly after
either the OE line or CS line is returned to a high levelꢀ
FIGꢀ 5
READ WAVEFORMS
NOTE:
OE may be delayed up to tACS-tOE after
the falling edge of CS without impact
on tOE or by tACC-tOE after an address
change without impact on tACCꢀ
AC READ CHARACTERISTICS (SEE FIGURE 5)
FOR WE512K8-XCX
(VCC= 5ꢀ0V, VSS = 0V, TA = -55°C TO +125°C)
Parameter
Symbol
-150
-200
-250
-300
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tACC
tACS
tOH
tOE
150
0
200
0
250
300
ns
ns
ns
ns
Address Access Time
150
150
200
200
250
250
300
300
Chip Select Access Time
Output Hold from Address Change, OE or CS
Output Enable to Output Valid
Chip Select or Output Enable to High Z Output
0
0
8581500
70
ns 125
70
tDF
70
70
ns
FOR WE256K8-XCX AND WE128K8-XCX
Parameter
Symbol
-150
-200
Unit
Min
Max
Min
Max
Read Cycle Time
tRC
tACC
tACS
tOH
tOE
150
200
ns
ns
ns
ns
Address Access Time
150
150
200
200
Chip Select Access Time
Output Hold from Address Change, OE or CS
Output Enable to Output Valid
Chip Select or Output Enable to High Z Output
10
10
ns
85100
70
tDF
70
ns
5
White Electronic Designs Corporation (602) 437-1520 wwwꢀwhiteedcꢀcom
WE512K8, WE256K8,
WE128K8-XCX
WRITE CYCLE TIMING
WRITE
Figures 6 and 7 show the write cycle timing relation-
shipsꢀ A write cycle begins with address application,
write enable and chip selectꢀ Chip select is accom-
plished by placing the CS line lowꢀ Write enable con-
sists of setting the WE line lowꢀ The write cycle begins
when the last of either CS or WE goes lowꢀ
Write operations are initiated when both CS and WE
are low and OE is highꢀ The EEPROM devices support
both a CS and WE controlled write cycleꢀ The address
is latched by the falling edge of either CS or WE, which-
ever occurs lastꢀ
The data is latched internally by the rising edge of ei-
ther CS or WE, whichever occurs firstꢀ A byte write
operation will automatically continue to completionꢀ
The WE line transition from high to low also initiates an
internal 150µsec delay timer to permit page mode op-
erationꢀ Each subsequent WE transition from high to
low that occurs before the completion of the 150µsec
time out will restart the timer from zeroꢀ The operation
of the timer is the same as a retriggerable one-shotꢀ
AC WRITE CHARACTERISTICS
(VCC = 5ꢀ0V, VSS = 0V, TA = -55°C TO +125°C)
Parameter
Symbol
512K x 8
256K x 8
128K x 8
Unit
Min
Max
10
Min
Max
10
Min
Max
10
Write Cycle Time, TYP = 6mS
Address Set-up Time
tWC
tAS
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
150
0
30
150
0
30
150
0
Write Pulse Width (WE or CS)
Chip Select Set-up Time
Address Hold Time (1)
Data Hold Time
tWP
tCS
tAH
125
10
0
50
0
50
0
tDH
Chip Select Hold Time
Data Set-up Time
tCH
0
0
tDS
100
10
10
50
100
30
0
100
30
0
Output Enable Set-up Time
Output Enable Hold Time
Write Pulse Width High
tOES
tOEH
tWPH
50
50
NOTES:
1ꢀ A17 and A18 must remain valid through WE and CS low pulse, for 512K x 8ꢀ
A15, A16, and A17 must remain valid through WE and CS low pulse, for 256K x 8ꢀ
A15 and A16 must remain valid through WE and CS low pulse, for 128K x 8ꢀ
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
6
WE512K8, WE256K8,
WE128K8-XCX
FIGꢀ 6
WRITE WAVEFORMS
WE CONTROLLED
NOTE:
1ꢀ Decoded Address Lines must be valid for the duration of the writeꢀ
FIGꢀ 7
WRITE WAVEFORMS
CS CONTROLLED
NOTE:
1ꢀ Decoded Address Lines must be valid for the duration of the writeꢀ
7
White Electronic Designs Corporation (602) 437-1520 wwwꢀwhiteedcꢀcom
WE512K8, WE256K8,
WE128K8-XCX
Data polling allows a simple bit test operation to deter-
mine the status of the EEPROMꢀ During the internal
programming cycle, a read of the last byte written will
produce the complement of the data on I/O7ꢀ For ex-
ample, if the data written consisted of I/O7 = HIGH, then
the data read back would consist of I/O7 = LOWꢀ
DATA POLLING
Operation with data polling permits a faster method of
writing to the EEPROMꢀ The actual time to complete
the memory programming cycle is faster than the guar-
anteed maximumꢀ
The EEPROM features a method to determine when
the internal programming cycle is completedꢀ After a
write cycle is initiated, the EEPROM will respond to read
cycles to provide the microprocessor with the status of
the programming cycleꢀ The status consists of the last
data byte written being returned with data bit I/O7
complemented during the programming cycle, and I/O7
true after completionꢀ
A polled byte write sequence would consist of the fol-
lowing steps:
1ꢀ write byte to EEPROM
2ꢀ store last byte and last address written
3ꢀ release a time slice to other tasks
4ꢀ read byte from EEPROM - last address
5ꢀ compare I/O7 to stored value
a) If different, write cycle is not completed, go to
step 3ꢀ
b) If same, write cycle is completed, go to step 1
or step 3ꢀ
DATA POLLING AC CHARACTERISTICS
(VCC = 5ꢀ0V, VCC = 0V, TA = -55°C TO +125°C)
Parameter
Symbol
512Kx8
Min
10
256Kx8
128Kx8
Unit
Max
Min
0
Max
Min
0
Max
Data Hold Time
tDH
tOEH
tOE
ns
ns
ns
ns
Output Enable Hold Time
Output Enable To Output Delay
Write Recovery Time
10
0
0
100
100
100
tWR
0
0
0
FIGꢀ 8
DATA POLLING
WAVEFORMS
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
8
WE512K8, WE256K8,
WE128K8-XCX
The page address must be the same for each byte load
and must be valid during each high to low transition of
WE (or CS)ꢀ The block address also must be the same
for each byte load and must remain valid throughout
the WE (or CS) low pulseꢀ The page and block address
lines are summarized below:
PAGE WRITE OPERATION
These devices have a page write operation that allows
one to 64 bytes of data (one to 128 bytes for the
WE512K8) to be written into the device and then simul-
taneously written during the internal programming pe-
riodꢀ Successive bytes may be loaded in the same man-
ner after the first data byte has been loadedꢀ An internal
timer begins a time out operation at each write cycleꢀ If
another write cycle is completed within 150µs or less, a
new time out period beginsꢀ Each write cycle restarts
the delay periodꢀ The write cycles can be continued as
long as the interval is less than the time out periodꢀ
PAGE MODE CHARACTERISTICS
(VCC = 5ꢀ0V, VSS = 0V, TA = -55°C TO +125°C)
Parameter
Symbol Min Max Unit
Write Cycle Time, TYP = 6mS
Data Set-up Time
tWC
tDS
10
ms
ns
ns
ns
µs
100
10
Data Hold Time
tDH
The usual procedure is to increment the least signifi-
cant address lines from A0 through A5 (A0 through A6 for
the WE512K8) at each write cycleꢀ In this manner a page
of up to 64 bytes (128 bytes for the WE512K8) can be
loaded into the EEPROM in a burst mode before begin-
ning the relatively long interval programming cycleꢀ
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
tWP
tBLC
tWPH
150
150
5
0
ns
Device
Block Address
Page Address
After the 150µs time out is completed, the EEPROM
begins an internal write cycleꢀ During this cycle the en-
tire page of bytes will be written at the same timeꢀ The
internal programming cycle is the same regardless of
the number of bytes accessedꢀ
WE512K8-XCX
WE256K8-XCX
WE128K8-XCX
A17-A18
A15-A17
A15-A16
A7-A16
A6-A14
A6-A14
FIGꢀ 9
PAGE WRITE WAVEFORMS
NOTE:
1ꢀ Decoded Address Lines must be valid for the duration of the writeꢀ
9
White Electronic Designs Corporation (602) 437-1520 wwwꢀwhiteedcꢀcom
WE512K8, WE256K8,
WE128K8-XCX
FIGꢀ 10
SOFTWARE BLOCK DATA
PROTECTION ENABLE ALGORITHM
(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES
ENABLED(2)
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
NOTES:
1ꢀ Data Format: I/O7-0 (Hex);
Address Format: A14 -A0 (Hex)ꢀ
A17 and A18 control selection of one of four blocks in the 512Kx8ꢀ
A15, A16, and A17 control selection of one of 8 pages in the
256Kx8ꢀ
A15 and A16 control one of the four blocks in the 128Kx8ꢀ
2ꢀ Write Protect state will be activated at end of write even if no
other data is loadedꢀ
3ꢀ Write Protect state will be deactivated at end of write period
even if no other data is loadedꢀ
4ꢀ 1 to 128 bytes of data at each of 4 blocks may be loaded in the
512Kx8ꢀ 1 to 64 bytes of data at each of 8 blocks may be
loaded in the 256Kx8 and 1 to 64 bytes on 4 blocks in the
128Kx8ꢀ
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
10
WE512K8, WE256K8,
WE128K8-XCX
SOFTWARE DATA PROTECTION
FIGꢀ 11
A software write protection feature may be enabled or
disabled by the userꢀ When shipped by White Micro-
electronics, the devices have the feature disabledꢀ Write
access to the device is unrestrictedꢀ
SOFTWARE BLOCK DATA
PROTECTION DISABLE ALGORITHM
To enable software write protection, the user writes three
access code bytes to three special internal locationsꢀ
Once write protection has been enabled, each write to
the EEPROM must use the same three byte write se-
quence to permit writingꢀ After setting software data
protection, any attempt to write to the device without
the three-byte command sequence will start the inter-
nal write timersꢀ No data will be written to the device,
however, for the duration of tWCꢀ The write protection
feature can be disabled by a six byte write sequence of
specific data to specific locationsꢀ Power transitions
will not reset the software write protectionꢀ
(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
Each 32K byte block (128K bytes for the WE512K8) of
EEPROM has independent write protectionꢀ One or
more blocks may be enabled and the rest disabled in
any combinationꢀ The software write protection guards
against inadvertent writes during power transitions or
unauthorized modification using a PROM programmerꢀ
The block selection is controlled by the upper most ad-
dress lines (A17 through A18 for the WE512K8, A15
through A17 for the WE256K8, or A15 and A16 for the
WE128K8)ꢀ
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
HARDWARE DATA PROTECTION
LAST ADDRESS
Several methods of hardware data protection have been
implemented in the White Microelectronics EEPROMꢀ
These are included to improve reliability during normal
operationsꢀ
a) VCC power on delay
As VCC climbs past 3ꢀ8V typical the device will wait
5mSec typical before allowing write cyclesꢀ
NOTES:
1ꢀ Data Format: I/O7-0 (Hex);
Address Format: A14 -A0 (Hex)ꢀ
b) VCC sense
While below 3ꢀ8V typical write cycles are inhibitedꢀ
c) Write inhibiting
A17 and A18 control selection of one of four blocks in the
512Kx8ꢀ
A15, A16, and A17 control selection of one of 8 pages in the
256Kx8ꢀ
A15 and A16 control one of the four blocks in the 128Kx8ꢀ
2ꢀ Write Protect state will be activated at end of write even if no
other data is loadedꢀ
3ꢀ Write Protect state will be deactivated at end of write period even
if no other data is loadedꢀ
Holding OE low and either CS or WE high inhibits
write cyclesꢀ
d) Noise filter
Pulses of <8ns (typ) on WE or CS will not initiate a
write cycleꢀ
4ꢀ 1 to 128 bytes of data at each of 4 blocks may be loaded in the
512Kx8ꢀ 1 to 64 bytes of data at each of 8 blocks may be loaded
in the 256Kx8 and 1 to 64 bytes on 4 blocks in the 128Kx8ꢀ
11
White Electronic Designs Corporation (602) 437-1520 wwwꢀwhiteedcꢀcom
WE512K8, WE256K8,
WE128K8-XCX
PACKAGE 300: 32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 302: 32 PIN, CERAMIC DIP, DUAL CAVITY BOTTOM BRAZED
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
12
WE512K8, WE256K8,
WE128K8-XCX
ORDERING INFORMATION
W E XXXK8 - XXX C X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
PROCESSING:
Q = MIL-STD-883 Compliant
M = Military Screened
I = Industrial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
C = Commercial
PACKAGE:
C = Ceramic DIP (Package 300 for 128Kx8)
(Package 302 for 256Kx8)
(Package 300 for 512Kx8)
ACCESS TIME (ns)
ORGANIZATION, 512Kx8, 256Kx8 or 128Kx8
EEPROM
WHITE ELECTRONIC DESIGNS
DEVICE TYPE
SPEED
PACKAGE
WM PART NOꢀ
SMD NOꢀ
512K x 8 EEPROM
512K x 8 EEPROM
512K x 8 EEPROM
512K x 8 EEPROM
150ns
300ns
250ns
200ns
32 pin DIP (C)
32 pin DIP (C)
32 pin DIP (C)
32 pin DIP (C)
WE512K8-150CQ
WE512K8-300CQ
WE512K8-250CQ
WE512K8-200CQ
5962-93091 01HYX
5962-93091 02HYX
5962-93091 03HYX
5962-93091 04HYX
256K x 8 EEPROM
256K x 8 EEPROM
200ns
150ns
32 pin DIP (C)
32 pin DIP (C)
WE256K8-200CQ
WE256K8-150CQ
5962-93155 01HYX
5962-93155 02HYX
128K x 8 EEPROM
128K x 8 EEPROM
200ns
150ns
32 pin DIP (C)
32 pin DIP (C)
WE128K8-200CQ
WE128K8-150CQ
5962-93154 01HXX
5962-93154 02HXX
DEVICE TYPE
WM PART NOꢀ
SPEED
PACKAGE
SMD NOꢀ
13
White Electronic Designs Corporation (602) 437-1520 wwwꢀwhiteedcꢀcom
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WE128K8200CCA
EEPROM Module, 128KX8, 200ns, Parallel, CMOS, CDIP32, HERMETIC SEALED, SINGLE CAVITY, SIDE BRAZED, CERAMIC, DIP-32
MERCURY
WE128K8200CIA
EEPROM Module, 128KX8, 200ns, Parallel, CMOS, CDIP32, HERMETIC SEALED, SINGLE CAVITY, SIDE BRAZED, CERAMIC, DIP-32
MERCURY
WE128K8200CM
EEPROM Module, 128KX8, 200ns, Parallel, CMOS, CDIP32, HERMETIC SEALED, SINGLE CAVITY, SIDE BRAZED, CERAMIC, DIP-32
WEDC
WE128K8200CMA
EEPROM Module, 128KX8, 200ns, Parallel, CMOS, CDIP32, HERMETIC SEALED, SINGLE CAVITY, SIDE BRAZED, CERAMIC, DIP-32
WEDC
WE128K8200CQA
EEPROM Module, 128KX8, 200ns, Parallel, CMOS, CDIP32, HERMETIC SEALED, SINGLE CAVITY, SIDE BRAZED, CERAMIC, DIP-32
WEDC
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