WCFS0808V1E [ETC]
32K x 8 3.3V Static RAM; 32K ×8 3.3V静态RAM
| 型号： | WCFS0808V1E |
| 厂家： | 
ETC |
| 描述： | 32K x 8 3.3V Static RAM |
| 文件： | 总10页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1WCFS0808V1E
WCFS0808V1E
32K x 8 3.3V Static RAM
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs are
both LOW, data on the eight data input/output pins (I/O0
through I/O7) is written into the memory location addressed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
Features
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed
— 12/15 ns
• Plastic SOJ and TSOP packaging
Functional Description
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The WCFS0808V1E is available in 28-pin stan-
dard 300-mil-wide SOJ and TSOP Type I packages.
The WCFS0808V1E is a high-performance 3.3V CMOS Static
RAM organized as 32K words by 8 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE) and ac-
tive LOW Output Enable (OE) and three-state drivers. The de-
vice has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
Logic Block Diagram
Pin Configurations
SOJ
Top View
A
A
V
CC
28
27
26
1
2
3
4
5
6
5
WE
6
A
A
7
A
4
A
3
8
25
24
A
9
A
2
A
10
A
11
A
12
23
22
A
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
8
9
10
11
12
13
OE
A
0
0
1
2
3
4
5
6
21
20
19
18
17
INPUT BUFFER
A
13
A
14
CE
I/O
A
7
0
I/O
I/O
I/O
I/O
I/O
A
0
1
2
6
5
4
1
A
2
16
15
A
I/O
I/O
3
A
GND
14
4
3
32K x 8
ARRAY
A
5
A
6
A
7
A
8
A
9
CE
WE
POWER
DOWN
COLUMN
DECODER
I/O
7
OE
Selection Guide
WCFS0808V1E 12ns
WCFS0808V1E 15ns
Maximum Access Time (ns)
12
55
15
50
Maximum Operating Current (mA)
Maximum CMOS Standby Current (µA)
500
500
Document #: 38-05225 Rev. **
Revised February 11, 2002
WCFS0808V1E
Pin Configuration
TSOP
Top View
21
20
OE
1
22
23
A
CE
I/O
I/O
I/O
I/O
I/O
0
A
A
19
18
17
16
24
2
7
6
5
4
3
A
25
26
27
28
1
3
A
4
WE
15
14
13
V
CC
A
GND
I/O
5
A
2
3
6
2
A7
12
11
I/O
I/O
A
1
0
A
4
5
8
10
9
A
14
13
12
9
10
11
A
A
A
A
6
7
8
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Temperature
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
Range
VCC
DC Voltage Applied to Outputs
Commercial
0°C to +70°C
3.3V ±300 mV
in High Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range[1]
WCFS0808V1E 12ns
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Test Conditions
Min.
Max.
Unit
V
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 4.0 mA
2.4
0.4
V
VIH
2.2
–0.3
–1
VCC +0.3V
V
V
VIL
0.8
+1
+5
IIX
µA
µA
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC
,
–5
Output Disabled
IOS
Output Short
VCC = Max., VOUT = GND
–300
55
mA
mA
mA
µA
Circuit Current[2]
ICC
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
ISB1
ISB2
Automatic CE Power-Down
Current — TTL Inputs
Max. VCC, CE ≥ VIH,
5
VIN ≥ VIH, or VIN ≤ VIL,f = fMAX
Automatic CE Power-Down
Current — CMOS Inputs[3]
Max. VCC, CE ≥ VCC – 0.3V, VIN ≥ VCC
0.3V, or VIN ≤ 0.3V,
–
500
WE ≥VCC – 0.3V or WE ≤0.3V, f = fMAX
Notes:
1. Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Device draws low standby current regardless of switching on the addresses.
Document #: 38-05225 Rev. **
Page 2 of 10
WCFS0808V1E
Electrical Characteristics Over the Operating Range (continued)
WCFS0808V1E 15ns
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 4.0 mA
Min.
Max.
Unit
V
2.4
VOL
VIH
0.4
V
2.2
VCC
V
+0.3V
VIL
IIX
Input LOW Voltage
Input Load Current
Output Leakage Current
–0.3
–1
0.8
+1
+5
V
µA
µA
IOZ
GND ≤ VI ≤ VCC
,
–5
Output Disabled
IOS
ICC
ISB1
Output Short Circuit
Current[2]
VCC = Max., VOUT = GND
–300
50
mA
mA
mA
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
AutomaticCEPower-Down Max. VCC, CE ≥ VIH,
Current — TTL Inputs IN ≥ VIH, or VIN ≤ VIL,
f = fMAX
5
V
ISB2
AutomaticCEPower-Down Max. VCC, CE ≥ VCC–0.3V, VIN ≥ VCC
–
500
µA
Current — CMOS Inputs[3] 0.3V,orVIN ≤0.3V,WE≥VCC–0.3VorWE≤
0.3V, f=fMAX
Capacitance[4]
Parameter
Description
Test Conditions
Max.
Unit
CIN: Addresses
CIN: Controls
COUT
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 3.3V
5
6
6
pF
pF
pF
Output Capacitance
AC Test Loads and Waveforms
R1 317Ω
3.3V
ALL INPUT PULSES
90%
OUTPUT
3.0V
90%
10%
10%
R2
351Ω
C
L
GND
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05225 Rev. **
Page 3 of 10
WCFS0808V1E
Switching Characteristics Over the Operating Range[5]
WCFS0808V1E 12ns
Parameter
Description
Min.
12
3
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
12
tOHA
tACE
12
5
tDOE
tLZOE
0
3
0
tHZOE
5
6
tLZCE
tHZCE
tPU
tPD
12
WRITE CYCLE[8, 9]
tWC
tSCE
tAW
Write Cycle Time
12
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
8
tHA
0
tSA
0
tPWE
tSD
8
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[8]
7
tHD
0
tHZWE
7
tLZWE
WE HIGH to Low Z[6]
3
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the
specified I /I and capacitance C = 30 pF.
OL OH
L
6. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
7.
t
, t
, t
are specified with C = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
HZOE HZCE HZWE L
8. The internal write time of the memory is defined by the overlap of CELOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
and t .
HZWE
SD
Document #: 38-05225 Rev. **
Page 4 of 10
WCFS0808V1E
Switching Characteristics Over the Operating Range[5] (Continued)
WCFS0808V1E 15ns
Parameter
Description
Min.
15
3
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
15
tOHA
tACE
15
6
tDOE
tLZOE
0
3
0
tHZOE
6
7
tLZCE
tHZCE
tPU
tPD
15
WRITE CYCLE[8, 9]
tWC
tSCE
tAW
Write Cycle Time
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
tPWE
tSD
10
8
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[8]
tHD
0
tHZWE
tLZWE
7
WE HIGH to Low Z[6]
3
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min.
2.0
0
Max.
Unit
V
VDR
tCDR
VCC for Data Retention
Chip Deselect to Data
Retention Time
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
ns
V
IN > VCC – 0.3V or
tR
Operation Recovery Time
tRC
ns
VIN < 0.3V
Document #: 38-05225 Rev. **
Page 5 of 10
WCFS0808V1E
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2[11, 12]
t
RC
CE
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
ICC
ISB
CC
SUPPLY
CURRENT
50%
50%
Notes:
10. Device is continuously selected. OE, CE = V .
IL
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05225 Rev. **
Page 6 of 10
WCFS0808V1E
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[8, 13, 14]
t
WC
ADDRESS
CE
t
t
AW
HA
t
SA
t
PWE
WE
OE
t
SD
t
HD
NOTE 15
DATA VALID
DATA I/O
IN
t
HZOE
Write Cycle No. 2 (CE Controlled)[8, 13, 14]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Write Cycle No. 3 (WE Controlled, OE LOW)[9, 14]
t
WC
ADDRESS
CE
t
t
AW
HA
t
SA
WE
t
t
HD
SD
DATA VALID
DATA I/O
NOTE 15
IN
t
t
LZWE
HZWE
Notes:
13. Data I/O is high impedance if OE = V
.
IH
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
15. During this period, the I/Os are in the output state and input signals should not be applied.
Document #: 38-05225 Rev. **
Page 7 of 10
WCFS0808V1E
Truth Table
CE
WE
OE
Input/Output
High Z
Mode
Deselect/Power-Down
Power
H
X
X
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
L
L
L
H
L
L
X
H
Data Out
Data In
High Z
Read
)
Write
)
H
Deselect, Output Disabled
)
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
WCFS0808V1E–JC12
WCFS0808V1E–JC15
WCFS0808V1E–TC15
Name
Package Type
28-Lead Molded SOJ
12
J
J
Commercial
15
28-Lead Molded SOJ
T
28-Lead Thin Small Outline Package
Document #: 38-05225 Rev. **
Page 8 of 10
WCFS0808V1E
Package Diagrams
28-Lead (300-Mil) Molded SOJ J
28-Lead Thin Small Outline Package Type 1 (8x13.4 mm) T
Document #: 38-05225 Rev. **
Page 9 of 10
WCFS0808V1E
Revision History
Document Title: WCFS0808V1E 32K x 8 3.3V Static RAM
Document Number: Document #: 38-05225 Rev. **
ORIG. OF
CHANGE
REV.
ECN NO.
ISSUE DATE
DESCRIPTION OF CHANGE
**
113103
1/25/2002
XFL
New Datasheet
Document #: 38-05225 Rev. **
Page 10 of 10
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