UPD65448 [ETC]
CMOS-9HD Family.EA-9HD Family CMOS Gate Array.CMOS Embedded ArrayMemory Ver.4.0 | Block Library[10/2000] ; CMOS -9HD Family.EA -9HD系列CMOS门Array.CMOS嵌入式ArrayMemory版本4.0 |功能块库[ 10/2000 ]
| 型号： | UPD65448 |
| 厂家： | 
ETC |
| 描述： | CMOS-9HD Family.EA-9HD Family CMOS Gate Array.CMOS Embedded ArrayMemory Ver.4.0 | Block Library[10/2000]
|
| 文件： | 总263页 (文件大小：954K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Block Library
CMOS-9HD Family,
EA-9HD Family
CMOS Gate Array, CMOS Embedded Array
Memory Ver.4.0
Document No. A13071EJ4V0BL00 (4th edition)
Date Published October 2000 N CP(K)
© NEC Corporation 1997
Printed in Japan
[MEMO]
Block Library A13071EJ4V0BL00
Summary of Contents
CHAPTER 1 HIGH DENSITY SINGLE-PORT RAM BLOCK
(Soft Macro)................................................................... 1
CHAPTER 2 HIGH DENSITY DUAL-PORT RAM BLOCK
(Soft Macro)................................................................. 93
CHAPTER 3 ROM BLOCK.............................................................. 185
APPENDIX
BASIC RAM BLOCK ................................................. 205
Block Library A13071EJ4V0BL00
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
•
The information in this document is current as of September, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
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While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
Block Library A13071EJ4V0BL00
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
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Seoul, Korea
Tel: 02-528-0303
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Scandinavia Office
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Fax: 02-2719-5951
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Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
Fax: 08-63 80 388
J00.7
Block Library A13071EJ4V0BL00
Major Revisions in this Edition
Page
Throughout
p. 185
Description
Addition of EA-9HD Family
Chapter 3 ROM BLOCK
Addition of
APPENDIX B BLOCK LIST (by Funciton)
p. 223 in previous Deletion from previous edition of
edition
The mark
shows major revised points.
Block Library A13071EJ4V0BL00
PREFACE
1. Introduction
Memory blocks of CMOS-9HD family and EA-9HD family are listed in this manual.
When carrying out circuit design, it is requested that the CMOS-9HD Family Design Manual(A12985E),
EA-9HD Family Design Manual (A13282E) should also be read. Furthermore, as there are occasions when
this block library is changed without advance notice, please contact your local NEC ASIC design center.
Please observe all items listed in this manual(general matters,cautions,limitations).
If you don't observe these things,degradation in the quality and performance of LSI's or abnormal
operation may occur.
This library is composed of Preface, Contents, three chapters, and appendix as explained below.
(1) PREFACE
The usage of this library, meanings of terminologies and some information are described.
(2) CONTENTS
This CONTENTS is useful when searching a block from its name
(3) CHAPTER 1 HIGH DENSITY SINGLE-PORT RAM BLOCK (Soft Macro)
(4) CHAPTER 2 HIGH DENSITY DUAL-PORT RAM BLOCK (Soft Macro)
(5) CHAPTER 3 ROM BLOCK
(6) APPENDIX
BASIC RAM BLOCK
CHAPTER 1 to 3 and APPENDIX list each block in alphanumerical order. Each page describes a
logic symbol, a truth table, I/O data and delay time with an integrated format.
High-density RAM blocks of CMOS-9HD family and EA-9HD family are soft macros. A soft macro
consists of a test circuit called BIST, selectors, and some hard macros called basic macro which configure
bits and words desired.
In addition, be sure to read the CMOS-9HD Family Design Manual(A12985E) , EA-9HD Family
Design Manual (A13282E) before starting design.
Especially when implementing memory blocks, note that some blocks may be impossible to be
mounted because of limit of usable gates.
Block Library A13071EJ4V0BL00
( i )
2. Data Entered in the Block Library
(1)
(2)
(3)
(1) Block Type
(2) Function
:
:
:
Name of function block
Function of that block
74 (LS) series name which has the
same function
(3) SSI Family
(4)
(5)
(4) Logic Diagram
(5) Truth Table
(6) Input
:
:
:
:
Symbol of that block
Truth table of that block
Name of input pin, fan-in
Name of output pin, fan-out
(7) Output
(8) Switching Speed : Switching characteristics
(9) Equivalent Cells No. of cells used
(6)
(7)
(8)
:
(9)
Furthermore, the tPD symbols are as follows
A
→
↑
Y (HL)
↑ ↑
(10) (11)(12)
(10) Signal path (input to output)
(11) Input signal change (H: rise L: fall Z: High impedance)
(12) Output signal change (H: rise L: fall Z: High impedance)
( ii )
BlockLibrary A13071EJ4V0BL00
3. Memory
The shaded portions changes to high impedance momentarily in the internal circuit when an address or
CSB changes, causing output to become undefined.
3.1 High Density RAM (Single-port)
(1) Write cycle timing 1 (WEB control mode)
tWC
ADDRESS
CSB
tCWR
tAH
tAS
tWP
WEB
DI
tDH
t
DS
DATA VALID
tWEC
DO
(REB = 0)
Caution WEB or CSB must be in high level during the address signal is changing. The period
during which DATA VALID is output to DO is determined by either the length of time
tWEC that elapses from the falling edge of WEB or the time from when DI changes
until DO changes, whichever is longer.
(2) Write cycle timing 2 (CSB control mode)
tWC
ADDRESS
tAH
tAS
tCWR
CSB
tWP
WEB
tDS
tDH
DI
DATA VALID
(REB = 0)
Caution WEB or CSB must be in high level during the address signal is changing.
Block Library A13071EJ4V0BL00
( iii )
(3) Read cycle timing 1 (CSB=0, WEB=1,REB=0)
tRCA
ADDRESS
tACA
tOH
DO
tACA: Time until output is secured after address is determined.
tOH : Time during which data is held before being changed when an address changes.
(4) Read cycle timing 2 (REB=0, WEB=1)
tRCA
CSB
tCSC
tCSL
tCLL
DO
Caution The address signal must remain unchanged at the same time or before the transmission
of the low level.
(5) Read cycle timing 3 (CSB=0, WEB=1)
tRCA
REB
DO
tREC
tRLL
tREL
Caution The address signal must remain unchanged at the same time or before the transmission
of the low level.
( iv )
BlockLibrary A13071EJ4V0BL00
3.2 High Density RAM (Dual-port)
(1) Write cycle timing 1 (WEB control mode)
tWC
ADDRESS
tCWR
WSB
tAH
tDH
tAS
tWP
WEB
tDS
DI
tWEC
DO
(REB = 0)
Caution WEB or WSB must be in high level during the address signal is changing. When the
READ address and WRITE address are the same, the period during which DI is
output to DO is determined by either the length of time tWEC that elapses from the
falling edge of WEB or the time from when DI changes until DO changes, whichever
is longer.
(2) Write cycle timing 2 (WSB control mode)
tWC
ADDRESS
tAH
tAS
tCWR
t
WP
WEB
WSB
t
DS
tDH
DI
tWEC
DO
(REB = 0)
Caution WEB or WSB must be in high level during the address signal is changing. When the
READ address and WRITE address are the same, the period during which DI is
output to DO is determined by either the length of time tWEC that elapses from the
falling edge of WEB or the time from when DI changes until DO changes, whichever
is longer.
Block Library A13071EJ4V0BL00
( v )
(3) Read cycle timing 1 (RSB=0)
tRCA
ADDRESS
DO
tACA
tOH
(4) Read cycle timing 2
tRCA
RSB
DO
tREL
tREC
tRLL
Caution The address signal must remain unchanged at the same time or before the transmission
of the low level.
3.3 ROM
Read cycle timing
tcycle
ADDRESS
tACC
tAOH
DO
( vi )
BlockLibrary A13071EJ4V0BL00
4 . BIST (Built In Self Test)
The BIST is the name of the circuit incorporated into each RAM soft macro for testing RAM operation.
The BIST consists of test address generator, test data generator, test enable generator, expectation
value generator and comparator. Only connecting test pins(TEB, TIN, TOUT) to external pin for testing
RAM operation. When mounting plural number of RAM, RAM operation can be tested smoothly.
Refer to NEC for details such as circuit configuration of each BIST.
Block Library A13071EJ4V0BL00
( vii )
Related Document
The related documents in this publication may include preliminary versions. However, they are not marked as
such.
• CMOS-9HD Family and EA-9HD Family
• CMOS-9HD Family, EA-9HD Family Block Library
• CMOS-9HD Family, EA-9HD Family Memory Block Library
• Design For Test User's Manual
: A13052E
: This Manual
: A14357E
• CMOS-9HD Family
• CMOS-9HD Family Design Manual
• CMOS-9HD Family Mega Macro Design Manual
• EA-9HD Family
: A12985E
: A13941E
• EA-9HD Family Design Manual
: A13282E
: A13367E
• EA-9HD Family Memory Macro Design Manual
Before starting design work, contact your local NEC sales representative for the
latest information
( viii )
BlockLibrary A13071EJ4V0BL00
CONTENTS
CHAPTER 1
HIGH DENSITY SINGLE-PORT RAM BLOCK (Soft Macro)
Page
1
SINGLE-PORT HIGH DENSITY RAM
Function
Block
Type
Basic
RAM
Test
Block
Equivalent
Page
Cells
RB47
RB49
RB4B
RB4D
RB4F
RB4H
RB4M
RB4S
RB4U
RB87
RB89
RB8B
RB8D
RB8F
RB8H
RB8M
RB8S
RBAB
RBAD
RBAF
RBAH
RBAM
RBAS
RBC7
RBC9
RBCB
RBCD
RBCF
RBCH
RBCM
16 words × 4 bits Single-port RAM
32 words × 4 bits Single-port RAM
64 words × 4 bits Single-port RAM
128 words × 4 bits Single-port RAM
256 words × 4 bits Single-port RAM
512 words × 4 bits Single-port RAM
1 K words × 4 bits Single-port RAM
2 K words × 4 bits Single-port RAM
4 K words × 4 bits Single-port RAM
16 words × 8 bits Single-port RAM
32 words × 8 bits Single-port RAM
64 words × 8 bits Single-port RAM
128 words × 8 bits Single-port RAM
256 words × 8 bits Single-port RAM
512 words × 8 bits Single-port RAM
1 K words × 8 bits Single-port RAM
2 K words × 8 bits Single-port RAM
64 words × 10 bits Single-port RAM
128 words × 10 bits Single-port RAM
256 words × 10 bits Single-port RAM
512 words × 10 bits Single-port RAM
1 K words × 10 bits Single-port RAM
2 K words × 10 bits Single-port RAM
16 words × 16 bits Single-port RAM
32 words × 16 bits Single-port RAM
64 words × 16 bits Single-port RAM
128 words × 16 bits Single-port RAM
256 words × 16 bits Single-port RAM
512 words × 16 bits Single-port RAM
1 K words × 16 bits Single-port RAM
K147
K149
K149
K14D
K14D
K14D
K14D
K14D
K14D
K147
K149
K18B
K14D
K18F
K18F
K18M
K18M
K1AB
K1AB
K1AF
K1AF
K1AM
K1AM
K147
K149
K18B
K14D
K18F
K18F
K18M
RU47
RU49
RU4B
RU4D
RU4F
RU4H
RU4M
RU4S
RU4U
RU87
RU89
RU8B
RU8D
RU8F
RU8H
RU8M
RU8S
RUAB
RUAD
RUAF
RUAH
RUAM
RUAS
RUC7
RUC9
RUCB
RUCD
RUCF
RUCH
RUCM
655
884
1567
3753
3745
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
7194
14155
28077
55775
1119
1572
2267
3753
6246
12206
22140
43983
2750
6863
7673
15042
27400
54491
2057
2946
4312
7269
12242
24114
44017
Block Library A13071EJ4V0BL00
( I )
SINGLE-PORT HIGH DENSITY RAM
Function
Block
Type
Basic
RAM
Test
Block
Equivalent
Cells
Page
RBEB
RBED
RBEF
RBEH
RBEM
RBH7
RBH9
RBHB
RBHD
RBHF
RBHH
RBKB
RBKD
RBKF
RBKH
64 words × 20 bits Single-port RAM
128 words × 20 bits Single-port RAM
256 words × 20 bits Single-port RAM
512 words × 20 bits Single-port RAM
1 K words × 20 bits Single-port RAM
16 words × 32 bits Single-port RAM
32 words × 32 bits Single-port RAM
64 words × 32 bits Single-port RAM
128 words × 32 bits Single-port RAM
256 words × 32 bits Single-port RAM
512 words × 32 bits Single-port RAM
64 words × 40 bits Single-port RAM
128 words × 40 bits Single-port RAM
256 words × 40 bits Single-port RAM
512 words × 40 bits Single-port RAM
K1AB
K1AB
K1AF
K1AF
K1AM
K147
K149
K18B
K14D
K18F
K18F
K1AB
K1AB
K1AF
K1AF
RUEB
RUED
RUEF
RUEH
RUEM
RUH7
RUH9
RUHB
RUHD
RUHF
RUHH
RUKB
RUKD
RUKF
RUKH
5286
10220
15104
29778
54541
3933
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
5694
8411
14311
24189
47955
10349
20195
29884
49856
( II )
Block Library A13071EJ4V0BL00
CHAPTER 2
HIGH DENSITY DUAL-PORT RAM BLOCK (Soft Macro)
Page
93
DUAL-PORT HIGH DENSITY RAM
Function
Block
Type
Basic
RAM
Test
Block
Equivalent
Page
Cells
R947
R949
R94B
R94D
R94F
R94H
R94M
R94S
R94U
R987
R989
R98B
R98D
R98F
R98H
R98M
R98S
R9AB
R9AD
R9AF
R9AH
R9AM
R9AS
R9C7
R9C9
R9CB
R9CD
R9CF
R9CH
R9CM
R9EB
R9ED
R9EF
R9EH
R9EM
R9H7
R9H9
R9HB
R9HD
R9HF
R9HH
R9KB
R9KD
R9KF
R9KH
16 words × 4 bits Dual-port RAM
32 words × 4 bits Dual-port RAM
64 words × 4 bits Dual-port RAM
128 words × 4 bits Dual-port RAM
256 words × 4 bits Dual-port RAM
512 words × 4 bits Dual-port RAM
1 K words × 4 bits Dual-port RAM
2 K words × 4 bits Dual-port RAM
4 K words × 4 bits Dual-port RAM
16 words × 8 bits Dual-port RAM
32 words × 8 bits Dual-port RAM
64 words × 8 bits Dual-port RAM
128 words × 8 bits Dual-port RAM
256 words × 8 bits Dual-port RAM
512 words × 8 bits Dual-port RAM
1 K words × 8 bits Dual-port RAM
2 K words × 8 bits Dual-port RAM
64 words × 10 bits Dual-port RAM
128 words × 10 bits Dual-port RAM
256 words × 10 bits Dual-port RAM
512 words × 10 bits Dual-port RAM
1 K words × 10 bits Dual-port RAM
2 K words × 10 bits Dual-port RAM
16 words × 16 bits Dual-port RAM
32 words × 16 bits Dual-port RAM
64 words × 16 bits Dual-port RAM
128 words × 16 bits Dual-port RAM
256 words × 16 bits Dual-port RAM
512 words × 16 bits Dual-port RAM
1 K words × 16 bits Dual-port RAM
64 words × 20 bits Dual-port RAM
128 words × 20 bits Dual-port RAM
256 words × 20 bits Dual-port RAM
512 words × 20 bits Dual-port RAM
1 K words × 20 bits Dual-port RAM
16 words × 32 bits Dual-port RAM
32 words × 32 bits Dual-port RAM
64 words × 32 bits Dual-port RAM
128 words × 32 bits Dual-port RAM
256 words × 32 bits Dual-port RAM
512 words × 32 bits Dual-port RAM
64 words × 40 bits Dual-port RAM
128 words × 40 bits Dual-port RAM
256 words × 40 bits Dual-port RAM
512 words × 40 bits Dual-port RAM
K247
K249
K249
K24D
K24D
K24D
K24D
K24D
K24D
K247
K249
K28B
K24D
K28F
K28F
K28M
K28M
K2AB
K2AB
K2AF
K2AF
K2AM
K2AM
K247
K249
K28B
K24D
K28F
K28F
K28M
K2AB
K2AB
K2AF
K2AF
K2AM
K247
K249
K28B
K24D
K28F
K28F
K2AB
K2AB
K2AF
K2AF
RU47
RU49
RU4B
RU4D
RU4F
RU4H
RU4M
RU4S
RU4U
RU87
RU89
RU8B
RU8D
RU8F
RU8H
RU8M
RU8S
RUAB
RUAD
RUAF
RUAH
RUAM
RUAS
RUC7
RUC9
RUCB
RUCD
RUCF
RUCH
RUCM
RUEB
RUED
RUEF
RUEH
RUEM
RUH7
RUH9
RUHB
RUHD
RUHF
RUHH
RUHB
RUKD
RUKF
RUKH
883
1427
2636
4052
7837
15343
30396
60537
120704
1554
2632
3446
6613
10369
20418
37239
74136
4187
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
8079
12791
25244
46281
92206
2902
5036
6635
12939
20439
40489
74160
8125
15878
25290
50129
92244
5606
9852
13026
25605
40559
80657
15994
31469
50227
99937
Block Library A13071EJ4V0BL00
( III )
CHAPTER 3
ROM BLOCK
Page
185
ROM BLOCK
Block
Type
Equivalent
Page
Function
Cells
J14DK
J14FK
J14HK
J14MK
J14SK
J18DK
J18FK
J18HK
J18MK
J18SK
J1CDK
J1CFK
J1CHK
J1CMK
J1CSK
J1HFK
J1HHK
J1HMK
J1HSK
128 words × 4 bits ROM
256 words × 4 bits ROM
512 words × 4 bits ROM
1024 words × 4 bits ROM
2048 words × 4 bits ROM
128 words × 8 bits ROM
256 words × 8 bits ROM
512 words × 8 bits ROM
1024 words × 8 bits ROM
2048 words × 8 bits ROM
128 words × 16 bits ROM
256 words × 16 bits ROM
512 words × 16 bits ROM
1024 words × 16 bits ROM
2048 words × 16 bits ROM
256 words × 32 bits ROM
512 words × 32 bits ROM
1024 words × 32 bits ROM
2048 words × 32 bits ROM
1113
2035
3458
6370
12194
1785
3219
5890
10850
20770
3129
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
5587
10754
19810
37922
10323
20482
37730
73968
( IV )
Block Library A13071EJ4V0BL00
APPENDIX BASIC RAM BLOCK
Page
205
SINGLE-PORT BASIC RAM
Block
Equivalent
Page
Type
Function
Cells
K147
K149
K14D
K18B
K18F
K18M
K1AB
K1AF
K1AM
16 words × 4 bits Single-port RAM
32 words × 4 bits Single-port RAM
128 words × 4 bits Single-port RAM
64 words × 8 bits Single-port RAM
256 words × 8 bits Single-port RAM
1024 words × 8 bits Single-port RAM
64 words × 10 bits Single-port RAM
256 words × 10 bits Single-port RAM
1024 words × 10 bits Single-port RAM
432
650
206
208
210
212
214
216
218
220
222
1722
1974
5920
21804
2436
7326
27048
DUAL-PORT BASIC RAM
Function
Block
Type
Equivalent
Cells
Page
K247
K249
K24D
K28B
K28F
K28M
K2AB
K2AF
K2AM
16 words × 4 bits Dual-port RAM
32 words × 4 bits Dual-port RAM
128 words × 4 bits Dual-port RAM
64 words × 8 bits Dual-port RAM
256 words × 8 bits Dual-port RAM
1024 words × 8 bits Dual-port RAM
64 words × 10 bits Dual-port RAM
256 words × 10 bits Dual-port RAM
1024 words × 10 bits Dual-port RAM
638
1166
3744
224
226
228
230
232
234
236
238
240
3120
10000
36848
3840
12400
45872
Block Library A13071EJ4V0BL00
( V )
[MEMO]
( VI )
Block Library A13071EJ4V0BL00
CHAPTER 1
HIGH DENSITY
SINGLE-PORT RAM BLOCK
(Soft Macro)
Block Library A13071EJ4V0BL00
1
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB47
16 words × 4 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO3
N01
N04
H04
H05
DI3
AD0
H08
AD3
H09
H10
H11
WEB
REB
CSB
H12
H13
TIN
TOUT
N05
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
3.73
3.72
3.62
3.62
IN → OUT
AD0 to AD3
→DO0 to DO3 (HH)
MIN.
MAX.
H01
:
H04
H05
:
DI0
:
2.4
:
N01
:
N04
N05
DO0
:
23.7
:
(LH)
2.25
2.25
1.98
1.98
6.13
6.11
6.28
6.30
DI3
AD0
:
2.4
2.4
:
DO3
TOUT
23.7
26.0
(HL)
(LL)
CSB
(LL)
→DO0 to DO3 (LH)
(HL)
1.99
1.99
0.69
3.44
3.44
1.09
5.80
5.80
1.75
H08
H09
H10
H11
H12
H13
AD3
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
REB
(LH)
0.73
0.78
1.25
1.22
2.09
1.94
→DO0 to DO3 (HL)
DI0 to DI3
→DO0 to DO3 (LL)
(HH)
1.85
1.71
3.20
2.70
5.40
4.30
Equivalent Cells
Power (mW/MHz)
Rev.
655
1
2
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
6.30
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
6.30
1.98
5.80
2.60
0.93
1.99
2.10
1.94
REB output hold time
REB output set time
0.78
0.74
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
5.37
4.03
4.03
1.01
0.33
3.34
0.42
5.45
Block Library A13071EJ4V0BL00
3
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB49
32 words × 4 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO3
N01
N04
H04
H05
DI3
AD0
H09
AD4
H10
H11
H12
WEB
REB
CSB
H13
H14
TIN
TOUT
N05
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
4.26
4.25
4.15
4.16
H01
:
H04
H05
:
DI0
:
2.4
:
N01
:
N04
N05
DO0
:
23.7
:
IN → OUT
AD0 to AD4
→DO0 to DO3 (HH)
MIN.
MAX.
(LH)
2.59
2.59
2.32
2.32
6.99
6.97
7.14
7.16
DI3
AD0
:
2.4
2.4
:
DO3
TOUT
23.7
26.0
(HL)
(LL)
H09
H10
H11
H12
H13
H14
AD4
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO3 (LH)
(HL)
2.24
2.24
0.94
3.92
3.92
1.58
6.66
6.66
2.61
REB
(LH)
0.74
0.79
1.26
1.23
2.10
1.95
→DO0 to DO3 (HL)
DI0 to DI3
→DO0 to DO3 (LL)
(HH)
1.86
1.72
3.24
2.74
5.51
4.41
Equivalent Cells
Power (mW/MHz)
Rev.
884
1
4
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
7.16
Cycle time
7.16
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
2.32
6.66
2.61
0.94
2.24
2.11
1.95
0.79
0.75
REB output hold time
REB output set time
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
5.89
4.53
4.53
1.02
0.34
3.35
0.43
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
5.55
Block Library A13071EJ4V0BL00
5
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB4B
64 words × 4 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO3
N01
N04
H04
H05
DI3
AD0
H10
AD5
H11
H12
H13
WEB
REB
CSB
H14
H15
TIN
TOUT
N05
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
AD0 to AD5
→DO0 to DO3 (HH)
MIN.
MAX.
H01
:
H04
H05
:
DI0
:
2.4
:
N01
:
N04
N05
DO0
:
24.7
:
(LH)
2.81
2.72
1.52
1.41
4.80
4.66
3.98
3.93
8.04
7.82
7.99
8.05
DI3
AD0
:
2.4
2.4
:
DO3
TOUT
24.7
26.0
(HL)
(LL)
H10
H11
H12
H13
H14
H15
AD5
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
2.4
2.4
5.0
CSB
(LL)
→DO0 to DO3 (LH)
(HL)
2.55
2.55
1.30
4.41
4.41
2.17
7.43
7.43
3.57
REB
(LH)
0.97
1.12
1.61
1.76
2.65
2.81
→DO0 to DO3 (HL)
DI0 to DI3
→DO0 to DO3 (LL)
(HH)
2.08
2.07
3.58
3.28
6.03
5.26
Equivalent Cells
Power (mW/MHz)
Rev.
1567
1
6
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
8.06
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
8.06
1.41
7.43
3.57
1.30
2.56
2.65
2.81
REB output hold time
REB output set time
1.12
0.97
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.34
4.72
4.72
1.18
0.44
3.39
0.53
6.09
Block Library A13071EJ4V0BL00
7
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB4D
128 words × 4 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO3
N01
N04
H04
H05
DI3
AD0
H11
AD6
H12
H13
H14
WEB
REB
CSB
H15
H16
TIN
TOUT
N05
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
4.48
4.47
4.30
4.31
H01
:
H04
H05
:
DI0
:
2.4
:
N01
:
N04
N05
DO0
:
23.7
:
IN → OUT
AD0 to AD6
→DO0 to DO3 (HH)
MIN.
MAX.
(LH)
2.00
2.00
1.81
1.81
8.53
8.51
8.35
8.38
DI3
AD0
:
2.4
2.4
:
DO3
TOUT
23.7
26.0
(HL)
(LL)
H11
H12
H13
H14
H15
H16
AD6
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO3 (LH)
(HL)
1.02
1.02
0.92
3.51
3.51
1.59
7.55
7.55
2.68
REB
(LH)
0.81
0.69
1.43
1.20
2.45
2.04
→DO0 to DO3 (HL)
DI0 to DI3
→DO0 to DO3 (LL)
(HH)
1.85
1.64
3.46
2.99
6.09
5.20
Equivalent Cells
Power (mW/MHz)
Rev.
3753
1
8
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
9.95
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
9.95
2.09
7.56
2.69
1.08
3.08
2.45
2.04
REB output hold time
REB output set time
0.80
0.93
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.76
3.70
3.70
1.77
1.29
3.46
0.77
5.83
Block Library A13071EJ4V0BL00
9
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB4F
256 words × 4 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO3
N01
N04
H04
H05
DI3
AD0
H12
AD7
H13
H14
H15
WEB
REB
CSB
H16
H17
TIN
TOUT
N05
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
4.51
4.35
4.43
4.41
IN → OUT
AD0 to AD7
→DO0 to DO3 (HH)
MIN.
MAX.
H01
:
H04
H05
:
DI0
:
2.4
:
N01
:
N04
N05
DO0
:
24.7
:
(LH)
1.60
1.50
1.49
1.43
9.24
9.00
9.22
9.28
DI3
AD0
:
2.4
2.4
:
DO3
TOUT
24.7
26.0
(HL)
(LL)
H12
H13
H14
H15
H16
H17
AD7
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
2.4
2.4
5.0
CSB
(LL)
→DO0 to DO3 (LH)
(HL)
1.34
1.34
1.29
4.05
4.05
2.25
8.45
8.45
3.83
REB
(LH)
1.02
0.97
1.75
1.71
2.94
2.92
→DO0 to DO3 (HL)
DI0 to DI3
→DO0 to DO3 (LL)
(HH)
2.04
1.92
3.76
3.49
6.56
6.05
Equivalent Cells
Power (mW/MHz)
Rev.
3745
1
10
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
9.28
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
9.28
1.65
8.46
3.84
1.49
4.03
2.95
2.92
REB output hold time
REB output set time
1.13
1.18
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.79
3.73
3.73
1.68
1.38
3.37
0.86
6.49
Block Library A13071EJ4V0BL00
11
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB4H
512 words × 4 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO3
N01
N04
H04
H05
DI3
AD0
H13
AD8
H14
H15
H16
WEB
REB
CSB
H17
H18
TIN
TOUT
N05
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
AD0 to AD8
→DO0 to DO3 (HH)
MIN.
MAX.
H01
:
H04
H05
:
DI0
:
2.4
:
N01
:
N04
N05
DO0
:
23.7
:
(LH)
1.81
1.68
1.78
1.77
4.90
4.86
5.02
5.04
9.94
10.05
10.30
10.37
DI3
AD0
:
2.4
2.4
:
DO3
TOUT
23.7
26.0
(HL)
(LL)
H13
H14
H15
H16
H17
H18
AD8
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO3 (LH)
(HL)
1.75
1.75
1.81
4.73
4.73
3.28
9.60
9.60
5.68
REB
(LH)
1.03
1.29
1.80
2.31
3.06
3.99
→DO0 to DO3 (HL)
DI0 to DI3
→DO0 to DO3 (LL)
(HH)
2.07
2.15
3.83
3.91
6.69
6.77
Equivalent Cells
Power (mW/MHz)
Rev.
7194
1
12
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.38
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.38
1.94
9.61
5.68
2.65
5.24
3.07
3.99
REB output hold time
REB output set time
1.49
1.20
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.73
4.15
4.15
1.69
0.89
3.42
1.53
7.48
Block Library A13071EJ4V0BL00
13
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB4M
1K words × 4 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO3
N01
N04
H04
H05
DI3
AD0
H14
AD9
H15
H16
H17
WEB
REB
CSB
H18
H19
TIN
TOUT
N05
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
5.65
5.58
5.14
5.14
IN → OUT
AD0 to AD9
→DO0 to DO3 (HH)
MIN.
MAX.
H01
:
H04
H05
:
DI0
:
2.4
:
N01
:
N04
N05
DO0
:
21.7
:
(LH)
2.23
2.07
2.01
1.93
11.22
11.32
10.24
10.38
DI3
AD0
:
2.4
2.4
:
DO3
TOUT
21.7
26.0
(HL)
(LL)
H14
H15
H16
H17
H18
H19
AD9
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO3 (LH)
(HL)
2.15
2.15
1.96
5.45
5.45
3.39
10.83
10.83
5.74
REB
(LH)
1.28
1.30
2.20
2.30
3.71
3.92
→DO0 to DO3 (HL)
DI0 to DI3
→DO0 to DO3 (LL)
(HH)
2.32
2.29
4.24
4.16
7.37
7.20
Equivalent Cells
Power (mW/MHz)
Rev.
14155
1
14
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
11.33
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
11.33
2.23
10.84
5.74
2.26
6.46
3.72
3.93
REB output hold time
REB output set time
1.50
0.89
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.24
4.58
4.58
1.71
0.95
3.52
1.67
8.47
Block Library A13071EJ4V0BL00
15
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB4S
2K words × 4 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO3
N01
N04
H04
H05
DI3
AD0
H15
AD10
H16
H17
H18
WEB
REB
CSB
H19
H20
TIN
TOUT
N05
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H04
H05
:
DI0
:
2.4
:
N01
:
N04
N05
DO0
:
17.7
:
IN → OUT
AD0 to AD10
→DO0 to DO3 (HH)
MIN.
MAX.
(LH)
2.26
2.05
2.12
2.04
5.99
5.74
5.37
5.35
12.07
11.75
10.68
10.74
DI3
AD0
:
2.4
2.4
:
DO3
TOUT
17.7
26.0
(HL)
(LL)
H15
H16
H17
H18
H19
H20
AD10
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
2.4
2.4
5.0
CSB
(LL)
→DO0 to DO3 (LH)
(HL)
2.27
2.27
2.14
5.68
5.68
3.80
11.25
11.25
6.51
REB
(LH)
1.29
1.41
2.22
2.55
3.75
4.42
→DO0 to DO3 (HL)
DI0 to DI3
→DO0 to DO3 (LL)
(HH)
2.32
2.38
4.24
4.36
7.37
7.60
Equivalent Cells
Power (mW/MHz)
Rev.
28077
1
16
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
12.07
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
12.07
2.36
11.26
6.52
2.47
5.77
3.77
4.43
REB output hold time
REB output set time
1.63
1.49
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.54
4.76
4.76
1.70
1.08
3.44
1.95
8.86
Block Library A13071EJ4V0BL00
17
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB4U
4K words × 4 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO3
N01
N04
H04
H05
DI3
AD0
H16
AD11
H17
H18
H19
WEB
REB
CSB
H20
H21
TIN
TOUT
N05
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
6.30
6.21
5.87
5.84
IN → OUT
AD0 to AD11
→DO0 to DO3 (HH)
MIN.
MAX.
H01
:
H04
H05
:
DI0
:
2.4
:
N01
:
N04
N05
DO0
:
17.7
:
(LH)
2.28
2.11
2.25
2.23
12.85
12.91
11.78
11.73
DI3
AD0
:
2.4
2.4
:
DO3
TOUT
17.7
26.0
(HL)
(LL)
H16
H17
H18
H19
H20
H21
AD11
WEB
REB
CSB
TIN
TEB
2.4
2.4
2.4
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO3 (LH)
(HL)
2.72
2.72
2.63
6.44
6.44
4.65
12.50
12.50
7.95
REB
(LH)
1.39
1.66
2.38
3.03
3.99
5.26
→DO0 to DO3 (HL)
DI0 to DI3
→DO0 to DO3 (LL)
(HH)
2.57
2.72
4.65
4.95
8.04
8.59
Equivalent Cells
Power (mW/MHz)
Rev.
55775
1
18
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
12.91
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
12.91
2.44
12.51
7.95
3.04
6.90
3.99
5.28
REB output hold time
REB output set time
1.92
1.60
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.28
5.20
5.20
1.78
1.30
3.55
2.46
9.80
Block Library A13071EJ4V0BL00
19
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB87
16 words × 8 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO7
N01
N08
H08
H09
DI7
AD0
H12
AD3
H13
H14
H15
WEB
REB
CSB
H16
H17
TIN
TOUT
N09
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H08
H09
:
DI0
:
2.4
:
N01
:
N08
N09
DO0
:
23.7
:
IN → OUT
AD0 to AD3
→DO0 to DO7 (HH)
MIN.
MAX.
(LH)
2.31
2.29
2.02
2.03
3.81
3.78
3.68
3.70
6.26
6.21
6.38
6.43
DI7
AD0
:
2.4
2.4
:
DO7
TOUT
23.7
26.0
(HL)
(LL)
H12
H13
H14
H15
H16
H17
AD3
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO7 (LH)
(HL)
2.02
2.02
0.74
3.49
3.49
1.17
5.89
5.89
1.86
REB
(LH)
0.76
0.83
1.30
1.29
2.17
2.04
→DO0 to DO7 (HL)
DI0 to DI7
→DO0 to DO7 (LL)
(HH)
1.85
1.71
3.20
2.70
5.41
4.31
Equivalent Cells
Power (mW/MHz)
Rev.
1119
1
20
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
6.44
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
6.44
2.02
5.89
2.71
0.99
2.02
2.14
2.04
REB output hold time
REB output set time
0.84
0.77
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
5.68
4.05
4.05
1.27
0.36
3.30
0.51
5.57
Block Library A13071EJ4V0BL00
21
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB89
32 words × 8 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO7
N01
N08
H08
H09
DI7
AD0
H13
AD4
H14
H15
H16
WEB
REB
CSB
H17
H18
TIN
TOUT
N09
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
4.34
4.31
4.21
4.24
IN → OUT
AD0 to AD4
→DO0 to DO7 (HH)
MIN.
MAX.
H01
:
H08
H09
:
DI0
:
2.4
:
N01
:
N08
N09
DO0
:
23.7
:
(LH)
2.65
2.63
2.36
2.37
7.12
7.06
7.23
7.29
DI7
AD0
:
2.4
2.4
:
DO7
TOUT
23.7
26.0
(HL)
(LL)
CSB
(LL)
→DO0 to DO7 (LH)
(HL)
2.27
2.27
0.99
3.97
3.97
1.65
6.74
6.74
2.72
H13
H14
H15
H16
H17
H18
AD4
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
REB
(LH)
0.77
0.84
1.31
1.30
2.18
2.05
→DO0 to DO7 (HL)
DI0 to DI7
→DO0 to DO7 (LL)
(HH)
1.86
1.72
3.25
2.75
5.52
4.42
Equivalent Cells
Power (mW/MHz)
Rev.
1572
1
22
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
7.30
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
7.30
2.36
6.74
2.72
1.00
2.28
2.15
2.05
REB output hold time
REB output set time
0.85
0.78
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.20
4.55
4.55
1.28
0.37
3.31
0.52
5.68
Block Library A13071EJ4V0BL00
23
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB8B
64 words × 8 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO7
N01
N08
H08
H09
DI7
AD0
H14
AD5
H15
H16
H17
WEB
REB
CSB
H18
H19
TIN
TOUT
N09
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
4.45
4.44
4.44
4.45
H01
:
H08
H09
:
DI0
:
2.4
:
N01
:
N08
N09
DO0
:
23.7
:
IN → OUT
AD0 to AD5
→DO0 to DO7 (HH)
MIN.
MAX.
(LH)
2.86
2.86
2.46
2.46
7.04
7.02
7.67
7.69
DI7
AD0
:
2.4
2.4
:
DO7
TOUT
23.7
26.0
(HL)
(LL)
H14
H15
H16
H17
H18
H19
AD5
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO7 (LH)
(HL)
2.34
2.34
1.03
4.25
4.25
1.71
7.38
7.38
2.80
REB
(LH)
0.76
0.79
1.27
1.25
2.11
1.99
→DO0 to DO7 (HL)
DI0 to DI7
→DO0 to DO7 (LL)
(HH)
1.74
1.60
3.17
2.92
5.51
5.06
Equivalent Cells
Power (mW/MHz)
Rev.
2267
1
24
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
6.85
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
6.85
2.46
7.39
2.80
1.04
2.34
2.12
2.00
REB output hold time
REB output set time
0.79
0.76
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.48
3.63
3.63
2.62
0.23
2.62
1.50
4.78
Block Library A13071EJ4V0BL00
25
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB8D
128 words × 8 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO7
N01
N08
H08
H09
DI7
AD0
H15
AD6
H16
H17
H18
WEB
REB
CSB
H19
H20
TIN
TOUT
N09
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
AD0 to AD6
→DO0 to DO7 (HH)
MIN.
MAX.
H01
:
H08
H09
:
DI0
:
2.4
:
N01
:
N08
N09
DO0
:
23.7
:
(LH)
2.02
2.01
1.82
1.83
4.52
4.49
4.31
4.34
8.58
8.53
8.38
8.43
DI7
AD0
:
2.4
2.4
:
DO7
TOUT
23.7
26.0
(HL)
(LL)
H15
H16
H17
H18
H19
H20
AD6
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO7 (LH)
(HL)
1.03
1.03
0.94
3.52
3.52
1.61
7.59
7.59
2.71
REB
(LH)
0.82
0.70
1.45
1.22
2.47
2.08
→DO0 to DO7 (HL)
DI0 to DI7
→DO0 to DO7 (LL)
(HH)
1.85
1.64
3.46
2.99
6.09
5.20
Equivalent Cells
Power (mW/MHz)
Rev.
3753
1
26
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.02
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.02
2.11
7.60
2.71
1.08
3.12
2.48
2.08
REB output hold time
REB output set time
0.71
0.82
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.45
3.73
3.73
1.78
1.29
3.82
0.79
5.87
Block Library A13071EJ4V0BL00
27
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB8F
256 words × 8 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO7
N01
N08
H08
H09
DI7
AD0
H16
AD7
H17
H18
H19
WEB
REB
CSB
H20
H21
TIN
TOUT
N09
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
5.21
5.20
4.66
4.67
IN → OUT
AD0 to AD7
→DO0 to DO7 (HH)
MIN.
MAX.
H01
:
H08
H09
:
DI0
:
2.4
:
N01
:
N08
N09
DO0
:
23.7
:
(LH)
2.33
2.33
1.99
1.99
9.92
9.89
9.01
9.04
DI7
AD0
:
2.4
2.4
:
DO7
TOUT
23.7
26.0
(HL)
(LL)
H16
H17
H18
H19
H20
H21
AD7
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO7 (LH)
(HL)
1.10
1.10
0.98
3.98
3.98
1.68
8.67
8.67
2.81
REB
(LH)
0.95
0.72
1.59
1.26
2.64
2.13
→DO0 to DO7 (HL)
DI0 to DI7
→DO0 to DO7 (LL)
(HH)
1.99
1.75
3.70
3.23
6.49
5.65
Equivalent Cells
Power (mW/MHz)
Rev.
6246
1
28
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
9.92
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
9.92
2.29
8.67
2.81
1.13
3.31
2.64
2.13
REB output hold time
REB output set time
0.83
1.10
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.43
4.15
4.15
1.91
1.37
3.64
0.95
6.53
Block Library A13071EJ4V0BL00
29
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB8H
512 words × 8 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO7
N01
N08
H08
H09
DI7
AD0
H17
AD8
H18
H19
H20
WEB
REB
CSB
H21
H22
TIN
TOUT
N09
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
5.01
4.93
4.71
4.70
IN → OUT
AD0 to AD8
→DO0 to DO7 (HH)
MIN.
MAX.
H01
:
H08
H09
:
DI0
:
2.4
:
N01
:
N08
N09
DO0
:
24.7
:
(LH)
1.68
1.59
1.54
1.49
10.44
10.39
9.89
DI7
AD0
:
2.4
2.4
:
DO7
TOUT
24.7
26.0
(HL)
(LL)
9.94
H17
H18
H19
H20
H21
H22
AD8
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
2.4
2.4
5.0
CSB
(LL)
→DO0 to DO7 (LH)
(HL)
1.42
1.42
1.34
4.52
4.52
2.34
9.57
9.57
3.97
REB
(LH)
1.16
1.01
1.91
1.77
3.14
3.01
→DO0 to DO7 (HL)
DI0 to DI7
→DO0 to DO7 (LL)
(HH)
2.18
2.03
4.00
3.73
6.97
6.51
Equivalent Cells
Power (mW/MHz)
Rev.
12206
1
30
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.44
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.44
1.71
9.57
3.97
1.55
4.26
3.15
3.01
REB output hold time
REB output set time
1.16
1.34
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.59
4.18
4.18
1.82
0.59
3.54
0.94
6.99
Block Library A13071EJ4V0BL00
31
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB8M
1K words × 8 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO7
N01
N08
H08
H09
DI7
AD0
H18
AD9
H19
H20
H21
WEB
REB
CSB
H22
H23
TIN
TOUT
N09
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
AD0 to AD9
→DO0 to DO7 (HH)
MIN.
MAX.
H01
:
H08
H09
:
DI0
:
2.4
:
N01
:
N08
N09
DO0
:
23.7
:
(LH)
2.91
2.91
2.38
2.38
7.02
7.01
6.40
6.41
13.72
13.69
12.96
12.99
DI7
AD0
:
2.4
2.4
:
DO7
TOUT
23.7
26.0
(HL)
(LL)
H18
H19
H20
H21
H22
H23
AD9
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO7 (LH)
(HL)
1.19
1.19
1.06
4.81
4.81
1.87
10.70
10.70
3.19
REB
(LH)
1.01
0.74
1.72
1.35
2.88
2.35
→DO0 to DO7 (HL)
DI0 to DI7
→DO0 to DO7 (LL)
(HH)
2.94
2.61
5.58
4.86
9.88
8.52
Equivalent Cells
Power (mW/MHz)
Rev.
22140
1
32
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
13.72
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
13.72
2.75
10.70
3.19
1.23
3.58
2.89
2.35
REB output hold time
REB output set time
0.86
1.16
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.71
5.22
5.22
2.61
0.88
5.22
0.80
9.82
Block Library A13071EJ4V0BL00
33
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RB8S
2K words × 8 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO7
N01
N08
H08
H09
DI7
AD0
H19
AD10
H20
H21
H22
WEB
REB
CSB
H23
H24
TIN
TOUT
N09
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
6.51
6.43
6.26
6.25
IN → OUT
AD0 to AD10
→DO0 to DO7 (HH)
MIN.
MAX.
H01
:
H08
H09
:
DI0
:
2.4
:
N01
:
N08
N09
DO0
:
24.7
:
(LH)
1.77
1.67
1.61
1.56
14.23
14.19
13.84
13.89
DI7
AD0
:
2.4
2.4
:
DO7
TOUT
24.7
26.0
(HL)
(LL)
H19
H20
H21
H22
H23
H24
AD10
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
2.4
2.4
5.0
CSB
(LL)
→DO0 to DO7 (LH)
(HL)
1.50
1.50
1.42
5.34
5.34
2.53
11.60
11.60
4.34
REB
(LH)
1.21
1.02
2.03
1.86
3.38
3.23
→DO0 to DO7 (HL)
DI0 to DI7
→DO0 to DO7 (LL)
(HH)
3.13
2.89
5.88
5.35
10.36
9.36
Equivalent Cells
Power (mW/MHz)
Rev.
43983
1
34
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
14.24
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
14.24
1.81
11.60
4.34
1.64
4.53
3.38
3.23
REB output hold time
REB output set time
1.18
1.40
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.29
4.86
4.86
2.52
0.91
5.12
0.88
10.34
Block Library A13071EJ4V0BL00
35
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBAB
64 words × 10 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO9
N01
N10
H10
H11
DI9
AD0
H16
AD5
H17
H18
H19
WEB
REB
CSB
H20
H21
TIN
TOUT
N11
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H10
H11
:
DI0
:
2.4
:
N01
:
N10
N11
DO0
:
23.7
:
IN → OUT
AD0 to AD5
→DO0 to DO9 (HH)
MIN.
MAX.
(LH)
2.86
2.86
2.40
2.40
4.73
4.72
4.27
4.28
7.78
7.76
7.33
7.35
DI9
AD0
:
2.4
2.4
:
DO9
TOUT
23.7
26.0
(HL)
(LL)
H16
H17
H18
H19
H20
H21
AD5
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO9 (LH)
(HL)
2.29
2.29
1.05
4.30
4.30
1.73
7.56
7.56
2.85
REB
(LH)
0.76
0.79
1.27
1.25
2.11
2.00
→DO0 to DO9 (HL)
DI0 to DI9
→DO0 to DO9 (LL)
(HH)
1.74
1.60
3.20
2.92
5.60
5.07
Equivalent Cells
Power (mW/MHz)
Rev.
2750
1
36
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
7.79
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
7.79
2.40
7.58
2.85
1.05
2.29
2.12
2.01
REB output hold time
REB output set time
0.79
0.76
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.03
3.90
3.90
1.90
0.23
2.47
0.73
4.70
Block Library A13071EJ4V0BL00
37
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBAD
128 words × 10 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO9
N01
N10
H10
H11
DI9
AD0
H17
AD6
H18
H19
H20
WEB
REB
CSB
H21
H22
TIN
TOUT
N11
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
5.19
5.05
4.11
4.06
IN → OUT
AD0 to AD6
→DO0 to DO9 (HH)
MIN.
MAX.
H01
:
H10
H11
:
DI0
:
2.4
:
N01
:
N10
N11
DO0
:
23.7
:
(LH)
2.88
2.78
1.61
1.50
8.97
8.74
8.19
8.24
DI9
AD0
:
2.4
2.4
:
DO9
TOUT
23.7
26.0
(HL)
(LL)
H17
H18
H19
H20
H21
H22
AD6
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
2.5
CSB
(LL)
→DO0 to DO9 (LH)
(HL)
2.62
2.62
1.39
4.80
4.80
2.31
8.35
8.35
3.81
REB
(LH)
1.02
1.10
1.64
1.77
2.66
2.87
→DO0 to DO9 (HL)
DI0 to DI9
→DO0 to DO9 (LL)
(HH)
1.97
1.94
3.55
3.46
6.13
5.93
Equivalent Cells
Power (mW/MHz)
Rev.
6383
1
38
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
8.97
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
8.97
1.51
8.36
3.81
1.40
2.62
2.68
2.88
REB output hold time
REB output set time
1.11
1.02
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.05
3.96
3.96
1.76
0.33
2.50
0.83
5.23
Block Library A13071EJ4V0BL00
39
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBAF
256 words × 10 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO9
N01
N10
H10
H11
DI9
AD0
H18
AD7
H19
H20
H21
WEB
REB
CSB
H22
H23
TIN
TOUT
N11
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H10
H11
:
DI0
:
2.4
:
N01
:
N10
N11
DO0
:
23.7
:
IN → OUT
AD0 to AD7
→DO0 to DO9 (HH)
MIN.
MAX.
(LH)
2.27
2.27
2.11
2.11
5.25
5.24
4.91
4.91
10.11
10.08
9.47
DI9
AD0
:
2.4
2.4
:
DO9
TOUT
23.7
26.0
(HL)
(LL)
9.49
H18
H19
H20
H21
H22
H23
AD7
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO9 (LH)
(HL)
1.13
1.13
0.99
3.95
3.95
1.73
8.56
8.56
2.94
REB
(LH)
0.97
0.74
1.62
1.31
2.68
2.25
→DO0 to DO9 (HL)
DI0 to DI9
→DO0 to DO9 (LL)
(HH)
1.99
1.75
3.70
3.23
6.49
5.65
Equivalent Cells
Power (mW/MHz)
Rev.
7673
1
40
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.21
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.21
2.44
8.57
2.94
1.15
3.38
2.69
2.25
REB output hold time
REB output set time
0.86
1.13
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.67
4.41
4.41
1.89
1.37
3.59
1.01
6.48
Block Library A13071EJ4V0BL00
41
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBAH
512 words × 10 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO9
N01
N10
H10
H11
DI9
AD0
H19
AD8
H20
H21
H22
WEB
REB
CSB
H23
H24
TIN
TOUT
N11
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
5.10
5.02
4.90
4.88
IN → OUT
AD0 to AD8
→DO0 to DO9 (HH)
MIN.
MAX.
H01
:
H10
H11
:
DI0
:
2.4
:
N01
:
N10
N11
DO0
:
24.7
:
(LH)
1.71
1.60
1.55
1.50
10.64
10.58
10.35
10.39
DI9
AD0
:
2.4
2.4
:
DO9
TOUT
24.7
26.0
(HL)
(LL)
CSB
(LL)
→DO0 to DO9 (LH)
(HL)
1.44
1.44
1.35
4.49
4.49
2.40
9.46
9.46
4.10
H19
H20
H21
H22
H23
H24
AD8
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
2.4
2.4
5.0
REB
(LH)
1.18
1.02
1.94
1.82
3.18
3.12
→DO0 to DO9 (HL)
DI0 to DI9
→DO0 to DO9 (LL)
(HH)
2.18
2.03
4.00
3.73
6.97
6.51
Equivalent Cells
Power (mW/MHz)
Rev.
15042
1
42
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.64
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.64
1.73
9.46
4.10
1.56
4.33
3.18
3.12
REB output hold time
REB output set time
1.18
1.36
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.81
4.44
4.44
1.78
0.59
3.49
0.99
6.94
Block Library A13071EJ4V0BL00
43
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBAM
1K words × 10 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO9
N01
N10
H10
H11
DI9
AD0
H20
AD9
H21
H22
H23
WEB
REB
CSB
H24
H25
TIN
TOUT
N11
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
7.41
7.39
6.71
6.72
H01
:
H10
H11
:
DI0
:
2.4
:
N01
:
N10
N11
DO0
:
23.7
:
IN → OUT
AD0 to AD9
→DO0 to DO9 (HH)
MIN.
MAX.
(LH)
3.03
3.03
2.38
2.38
14.54
14.51
13.79
13.81
DI9
AD0
:
2.4
2.4
:
DO9
TOUT
23.7
26.0
(HL)
(LL)
H20
H21
H22
H23
H24
H25
AD9
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO9 (LH)
(HL)
1.21
1.21
1.07
5.03
5.03
1.91
11.26
11.26
3.27
REB
(LH)
1.02
0.77
1.75
1.40
2.94
2.42
→DO0 to DO9 (HL)
DI0 to DI9
→DO0 to DO9 (LL)
(HH)
2.94
2.61
5.58
4.81
9.88
8.39
Equivalent Cells
Power (mW/MHz)
Rev.
27400
1
44
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
14.54
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
14.54
2.75
11.27
3.27
1.23
3.64
2.94
2.42
REB output hold time
REB output set time
0.90
1.18
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.90
5.04
5.04
2.94
0.92
5.17
0.90
9.53
Block Library A13071EJ4V0BL00
45
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBAS
2K words × 10 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO9
N01
N10
H10
H11
DI9
AD0
H21
AD10
H22
H23
H24
WEB
REB
CSB
H25
H26
TIN
TOUT
N11
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
AD0 to AD10
→DO0 to DO9 (HH)
MIN.
MAX.
H01
:
H10
H11
:
DI0
:
2.4
:
N01
:
N10
N11
DO0
:
24.7
:
(LH)
1.79
1.70
1.63
1.57
6.83
6.76
5.49
6.56
15.07
15.01
11.78
14.71
DI9
AD0
:
2.4
2.4
:
DO9
TOUT
24.7
26.0
(HL)
(LL)
H21
H22
H23
H24
H25
H26
AD10
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
2.4
2.4
5.0
CSB
(LL)
→DO0 to DO9 (LH)
(HL)
1.53
1.53
1.43
5.57
5.57
2.57
12.16
12.16
4.43
REB
(LH)
1.23
1.06
2.07
1.91
3.43
3.30
→DO0 to DO9 (HL)
DI0 to DI9
→DO0 to DO9 (LL)
(HH)
3.13
2.89
5.88
5.30
10.36
9.23
Equivalent Cells
Power (mW/MHz)
Rev.
54491
1
46
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
15.07
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
15.07
1.81
12.16
4.43
1.65
4.59
3.45
3.30
REB output hold time
REB output set time
1.23
1.43
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
12.85
5.06
5.06
2.85
0.96
5.07
0.99
10.05
Block Library A13071EJ4V0BL00
47
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBC7
16 words × 16 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N16
H16
H17
DI15
AD0
DO15
H20
AD3
H21
H22
H23
WEB
REB
CSB
H24
H25
TIN
TOUT
N17
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
3.98
3.90
3.80
3.88
IN → OUT
AD0 to AD3
→DO0 to DO15 (HH)
MIN.
MAX.
H01
:
H16
H17
:
DI0
:
2.4
:
N01
:
N16
N17
DO0
:
23.7
:
(LH)
2.43
2.39
2.11
2.15
6.52
6.38
6.55
6.70
DI15
AD0
:
2.4
2.4
:
DO15
TOUT
23.7
26.0
(HL)
(LL)
H20
H21
H22
H23
H24
H25
AD3
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
2.5
CSB
(LL)
→DO0 to DO15 (LH)
(HL)
2.11
2.11
0.83
3.60
3.60
1.30
6.03
6.03
2.05
REB
(LH)
0.86
0.92
1.42
1.42
2.33
2.24
→DO0 to DO15 (HL)
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
2.21
1.73
3.29
2.71
5.06
4.31
Equivalent Cells
Power (mW/MHz)
Rev.
2057
1
48
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
6.70
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
6.70
2.20
6.05
2.90
1.08
2.35
2.33
2.24
REB output hold time
REB output set time
0.92
0.86
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.05
4.34
4.34
1.29
0.42
3.20
0.69
5.80
Block Library A13071EJ4V0BL00
49
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBC9
32 words × 16 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N16
H16
H17
DI15
AD0
DO15
H21
AD4
H22
H23
H24
WEB
REB
CSB
H25
H26
TIN
TOUT
N17
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
4.51
4.44
4.33
4.41
IN → OUT
AD0 to AD4
→DO0 to DO15 (HH)
MIN.
MAX.
H01
:
H16
H17
:
DI0
:
2.4
:
N01
:
N16
N17
DO0
:
23.7
:
(LH)
2.76
2.72
2.44
2.49
7.37
7.23
7.40
7.55
DI15
AD0
:
2.4
2.4
:
DO15
TOUT
23.7
26.0
(HL)
(LL)
H21
H22
H23
H24
H25
H26
AD4
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO15 (LH)
(HL)
2.36
2.36
1.08
4.08
4.08
1.78
6.89
6.89
2.91
REB
(LH)
0.87
0.92
1.43
1.43
2.34
2.25
→DO0 to DO15 (HL)
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
1.86
1.74
3.25
2.76
5.52
4.42
Equivalent Cells
Power (mW/MHz)
Rev.
2946
1
50
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
7.55
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
7.55
2.45
6.90
2.91
1.08
2.36
2.34
2.25
REB output hold time
REB output set time
0.93
0.87
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.57
4.84
4.84
1.30
0.43
3.21
0.70
5.91
Block Library A13071EJ4V0BL00
51
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBCB
64 words × 16 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N16
H16
H17
DI15
AD0
DO15
H22
AD5
H23
H24
H25
WEB
REB
CSB
H26
H27
TIN
TOUT
N17
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
AD0 to AD5
→DO0 to DO15 (HH)
MIN.
MAX.
H01
:
H16
H17
:
DI0
:
2.4
:
N01
:
N16
N17
DO0
:
23.7
:
(LH)
2.92
2.91
2.51
2.52
4.54
4.51
4.51
4.54
7.18
7.12
7.77
7.83
DI15
AD0
:
2.4
2.4
:
DO15
TOUT
23.7
26.0
(HL)
(LL)
H22
H23
H24
H25
H26
H27
AD5
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
2.5
CSB
(LL)
→DO0 to DO15 (LH)
(HL)
2.39
2.39
1.09
4.32
4.32
1.78
7.47
7.47
2.91
REB
(LH)
0.82
0.84
1.34
1.32
2.19
2.10
→DO0 to DO15 (HL)
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
1.75
1.61
3.21
2.92
5.61
5.06
Equivalent Cells
Power (mW/MHz)
Rev.
4312
1
52
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
7.83
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
7.83
2.51
7.48
2.91
1.09
2.39
2.20
2.11
REB output hold time
REB output set time
0.85
0.82
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.72
3.68
3.68
2.78
0.26
2.57
1.60
4.90
Block Library A13071EJ4V0BL00
53
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBCD
128 words × 16 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N16
H16
H17
DI15
AD0
DO15
H23
AD6
H24
H25
H26
WEB
REB
CSB
H27
H28
TIN
TOUT
N17
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
4.56
4.53
4.35
4.39
IN → OUT
AD0 to AD6
→DO0 to DO15 (HH)
MIN.
MAX.
H01
:
H16
H17
:
DI0
:
2.4
:
N01
:
N16
N17
DO0
:
23.7
:
(LH)
2.05
2.03
1.85
1.86
8.67
8.60
8.44
8.52
DI15
AD0
:
2.4
2.4
:
DO15
TOUT
23.7
26.0
(HL)
(LL)
H23
H24
H25
H26
H27
H28
AD6
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO15 (LH)
(HL)
1.06
1.06
0.96
3.56
3.56
1.65
7.64
7.64
2.77
REB
(LH)
0.84
0.72
1.48
1.26
2.54
2.13
→DO0 to DO15 (HL)
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
1.85
1.64
3.46
2.99
6.09
5.20
Equivalent Cells
Power (mW/MHz)
Rev.
7269
1
54
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.13
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.13
2.13
7.64
2.78
1.11
3.18
2.54
2.13
REB output hold time
REB output set time
0.72
0.85
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.89
3.78
3.78
1.80
1.31
3.41
0.85
5.96
Block Library A13071EJ4V0BL00
55
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBCF
256 words × 16 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N16
H16
H17
DI15
AD0
DO15
H24
AD7
H25
H26
H27
WEB
REB
CSB
H28
H29
TIN
TOUT
N17
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H16
H17
:
DI0
:
2.4
:
N01
:
N16
N17
DO0
:
23.7
:
IN → OUT
AD0 to AD7
→DO0 to DO15 (HH)
MIN.
MAX.
(LH)
2.34
2.34
2.00
2.01
5.24
5.22
4.68
4.70
9.96
9.92
9.04
9.10
DI15
AD0
:
2.4
2.4
:
DO15
TOUT
23.7
26.0
(HL)
(LL)
H24
H25
H26
H27
H28
H29
AD7
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO15 (LH)
(HL)
1.12
1.12
0.99
4.00
4.00
1.70
8.70
8.70
2.85
REB
(LH)
0.96
0.73
1.61
1.27
2.66
2.16
→DO0 to DO15 (HL)
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
1.99
1.75
3.70
3.23
6.49
5.65
Equivalent Cells
Power (mW/MHz)
Rev.
12242
1
56
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
9.97
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
9.97
2.31
8.70
2.85
1.15
3.34
2.68
2.16
REB output hold time
REB output set time
0.85
1.11
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.47
4.18
4.18
1.92
1.37
3.62
0.97
7.39
Block Library A13071EJ4V0BL00
57
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBCH
512 words × 16 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N16
H16
H17
DI15
AD0
DO15
H25
AD8
H26
H27
H28
WEB
REB
CSB
H29
H30
TIN
TOUT
N17
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
5.06
4.97
4.75
4.74
IN → OUT
AD0 to AD8
→DO0 to DO15 (HH)
MIN.
MAX.
H01
:
H16
H17
:
DI0
:
2.4
:
N01
:
N16
N17
DO0
:
24.7
:
(LH)
1.71
1.60
1.55
1.50
10.53
10.45
9.96
DI15
AD0
:
2.4
2.4
:
DO15
TOUT
24.7
26.0
(HL)
(LL)
10.03
H25
H26
H27
H28
H29
H30
AD8
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
2.4
2.4
5.0
CSB
(LL)
→DO0 to DO15 (LH)
(HL)
1.44
1.44
1.35
4.55
4.55
2.36
9.61
9.61
4.00
REB
(LH)
1.18
1.02
1.94
1.80
3.20
3.06
→DO0 to DO15 (HL)
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
2.18
2.03
4.00
3.73
6.97
6.51
Equivalent Cells
Power (mW/MHz)
Rev.
24114
1
58
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.53
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.53
1.73
9.62
4.00
1.56
4.33
3.20
3.07
REB output hold time
REB output set time
1.18
1.36
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.64
4.23
4.23
1.83
0.58
3.51
0.97
7.96
Block Library A13071EJ4V0BL00
59
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBCM
1K words × 16 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N16
H16
H17
DI15
AD0
DO15
H26
AD9
H27
H28
H29
WEB
REB
CSB
H30
H31
TIN
TOUT
N17
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H16
H17
:
DI0
:
2.4
:
N01
:
N16
N17
DO0
:
23.7
:
IN → OUT
AD0 to AD9
→DO0 to DO15 (HH)
MIN.
MAX.
(LH)
2.94
2.92
2.39
2.40
7.05
7.02
6.42
6.45
13.76
13.72
12.99
13.04
DI15
AD0
:
2.4
2.4
:
DO15
TOUT
23.7
26.0
(HL)
(LL)
H26
H27
H28
H29
H30
H31
AD9
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO15 (LH)
(HL)
1.20
1.20
1.07
4.82
4.82
1.89
10.73
10.73
3.22
REB
(LH)
1.02
0.76
1.74
1.37
2.91
2.38
→DO0 to DO15 (HL)
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
2.94
2.61
5.58
4.86
9.88
8.52
Equivalent Cells
Power (mW/MHz)
Rev.
44017
1
60
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
13.77
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
13.77
2.76
10.73
3.22
1.23
3.60
2.91
2.39
REB output hold time
REB output set time
0.87
1.18
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.36
4.86
4.86
2.62
0.88
5.20
0.81
9.87
Block Library A13071EJ4V0BL00
61
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBEB
64 words × 20 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N20
H20
H21
DI19
AD0
DO19
H26
AD5
H27
H28
H29
WEB
REB
CSB
H30
H31
TIN
TOUT
N21
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
4.83
4.80
4.35
4.37
IN → OUT
AD0 to AD5
→DO0 to DO19 (HH)
MIN.
MAX.
H01
:
H20
H21
:
DI0
:
2.4
:
N01
:
N20
N21
DO0
:
23.7
:
(LH)
2.92
2.91
2.46
2.47
7.93
7.86
7.43
7.48
DI19
AD0
:
2.4
2.4
:
DO19
TOUT
23.7
26.0
(HL)
(LL)
CSB
(LL)
→DO0 to DO19 (LH)
(HL)
2.34
2.34
1.10
4.36
4.36
1.80
7.66
7.66
2.94
H26
H27
H28
H29
H30
H31
AD5
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
REB
(LH)
0.82
0.84
1.35
1.32
2.20
2.11
→DO0 to DO19 (HL)
DI0 to DI19
→DO0 to DO19 (LL)
(HH)
1.75
1.61
3.21
2.93
5.61
5.07
Equivalent Cells
Power (mW/MHz)
Rev.
5286
1
62
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
7.93
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
7.93
2.46
7.67
2.95
1.11
2.35
2.21
2.12
REB output hold time
REB output set time
0.85
0.82
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.10
3.78
3.78
2.06
0.26
2.42
0.83
4.83
Block Library A13071EJ4V0BL00
63
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBED
128 words × 20 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N20
H20
H21
DI19
AD0
DO19
H27
AD6
H28
H29
H30
WEB
REB
CSB
H31
H32
TIN
TOUT
N21
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
5.30
5.16
4.23
4.22
H01
:
H20
H21
:
DI0
:
2.4
:
N01
:
N20
N21
DO0
:
23.7
:
IN → OUT
AD0 to AD6
→DO0 to DO19 (HH)
MIN.
MAX.
(LH)
2.95
2.86
1.68
1.57
9.13
8.91
8.39
8.54
DI19
AD0
:
2.4
2.4
:
DO19
TOUT
23.7
26.0
(HL)
(LL)
H27
H28
H29
H30
H31
H32
AD6
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
2.5
CSB
(LL)
→DO0 to DO19 (LH)
(HL)
2.69
2.69
1.45
4.90
4.90
2.39
8.52
8.52
3.93
REB
(LH)
1.09
1.21
1.76
1.93
2.85
3.09
→DO0 to DO19 (HL)
DI0 to DI19
→DO0 to DO19 (LL)
(HH)
1.99
1.97
3.57
3.48
6.15
5.95
Equivalent Cells
Power (mW/MHz)
Rev.
10220
1
64
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
9.14
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
9.14
1.58
8.52
3.94
1.45
2.69
2.85
3.09
REB output hold time
REB output set time
1.22
1.09
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.56
4.09
4.09
2.14
0.33
2.42
0.95
5.50
Block Library A13071EJ4V0BL00
65
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBEF
256 words × 20 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N20
H20
H21
DI19
AD0
DO19
H28
AD7
H29
H30
H31
WEB
REB
CSB
H32
H33
TIN
TOUT
N21
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
AD0 to AD7
→DO0 to DO19 (HH)
MIN.
MAX.
H01
:
H20
H21
:
DI0
:
2.4
:
N01
:
N20
N21
DO0
:
23.7
:
(LH)
2.29
2.28
2.12
2.13
5.28
5.26
4.92
4.95
10.17
10.11
9.49
DI19
AD0
:
2.4
2.4
:
DO19
TOUT
23.7
26.0
(HL)
(LL)
9.54
H28
H29
H30
H31
H32
H33
AD7
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO19 (LH)
(HL)
1.13
1.13
1.01
3.97
3.97
1.75
8.59
8.59
2.96
REB
(LH)
0.98
0.76
1.64
1.33
2.71
2.27
→DO0 to DO19 (HL)
DI0 to DI19
→DO0 to DO19 (LL)
(HH)
1.99
1.75
3.70
3.23
6.49
5.65
Equivalent Cells
Power (mW/MHz)
Rev.
15104
1
66
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.17
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.17
2.44
8.59
2.97
1.16
3.41
2.71
2.28
REB output hold time
REB output set time
0.87
1.13
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.71
4.44
4.44
1.90
1.37
3.57
1.03
7.34
Block Library A13071EJ4V0BL00
67
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBEH
512 words × 20 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N20
H20
H21
DI19
AD0
DO19
H29
AD8
H30
H31
H32
WEB
REB
CSB
H33
H34
TIN
TOUT
N21
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
5.14
5.06
4.92
4.91
IN → OUT
AD0 to AD8
→DO0 to DO19 (HH)
MIN.
MAX.
H01
:
H20
H21
:
DI0
:
2.4
:
N01
:
N20
N21
DO0
:
24.7
:
(LH)
1.72
1.63
1.56
1.50
10.72
10.65
10.41
10.48
DI19
AD0
:
2.4
2.4
:
DO19
TOUT
24.7
26.0
(HL)
(LL)
H29
H30
H31
H32
H33
H34
AD8
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
2.4
2.4
5.0
CSB
(LL)
→DO0 to DO19 (LH)
(HL)
1.46
1.46
1.36
4.52
4.52
2.41
9.50
9.50
4.12
REB
(LH)
1.20
1.05
1.97
1.86
3.23
3.18
→DO0 to DO19 (HL)
DI0 to DI19
→DO0 to DO19 (LL)
(HH)
2.18
2.03
4.00
3.73
6.97
6.51
Equivalent Cells
Power (mW/MHz)
Rev.
29778
1
68
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.72
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.72
1.74
9.51
4.13
1.58
4.39
3.24
3.18
REB output hold time
REB output set time
1.21
1.39
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.89
4.49
4.49
1.82
0.58
3.45
1.02
7.91
Block Library A13071EJ4V0BL00
69
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBEM
1K words × 20 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N20
H20
H21
DI19
AD0
DO19
H30
AD9
H31
H32
H33
WEB
REB
CSB
H34
H35
TIN
TOUT
N21
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
7.44
7.42
6.73
6.76
IN → OUT
AD0 to AD9
→DO0 to DO19 (HH)
MIN.
MAX.
H01
:
H20
H21
:
DI0
:
2.4
:
N01
:
N20
N21
DO0
:
23.7
:
(LH)
3.06
3.05
2.39
2.40
14.58
14.54
13.81
13.87
DI19
AD0
:
2.4
2.4
:
DO19
TOUT
23.7
26.0
(HL)
(LL)
H30
H31
H32
H33
H34
H35
AD9
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO19 (LH)
(HL)
1.23
1.23
1.08
5.05
5.05
1.93
11.29
11.29
3.31
REB
(LH)
1.03
0.79
1.77
1.42
2.96
2.45
→DO0 to DO19 (HL)
DI0 to DI19
→DO0 to DO19 (LL)
(HH)
2.94
2.61
5.58
4.81
9.88
8.39
Equivalent Cells
Power (mW/MHz)
Rev.
54541
1
70
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
14.59
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
14.59
2.76
11.29
3.31
1.25
3.67
2.97
2.45
REB output hold time
REB output set time
0.91
1.20
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.93
5.06
5.06
2.95
0.92
5.15
0.92
9.58
Block Library A13071EJ4V0BL00
71
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBH7
16 words × 32 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N32
H32
H33
DI31
AD0
DO31
H36
AD3
H37
H38
H39
WEB
REB
CSB
H40
H41
TIN
TOUT
N33
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
AD0 to AD3
→DO0 to DO31 (HH)
MIN.
MAX.
H01
:
H32
H33
:
DI0
:
2.4
:
N01
:
N32
N33
DO0
:
23.7
:
(LH)
2.65
2.55
2.28
2.37
4.34
4.16
4.05
4.23
7.09
6.77
6.93
7.27
DI31
AD0
:
2.4
2.4
:
DO31
TOUT
23.7
26.0
(HL)
(LL)
H36
H37
H38
H39
H40
H41
AD3
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
2.5
CSB
(LL)
→DO0 to DO31 (LH)
(HL)
2.26
2.26
1.02
3.81
3.81
1.55
6.35
6.35
2.43
REB
(LH)
1.01
1.11
1.63
1.68
2.64
2.61
→DO0 to DO31 (HL)
DI0 to DI31
→DO0 to DO31 (LL)
(HH)
1.86
1.73
3.21
2.71
5.42
4.31
Equivalent Cells
Power (mW/MHz)
Rev.
3933
1
72
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
7.27
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
7.27
2.37
6.36
3.27
1.26
2.50
2.64
2.61
REB output hold time
REB output set time
1.11
1.01
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.72
4.60
4.60
2.05
0.55
3.02
1.09
6.31
Block Library A13071EJ4V0BL00
73
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBH9
32 words × 32 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N32
H32
H33
DI31
AD0
DO31
H37
AD4
H38
H39
H40
WEB
REB
CSB
H41
H42
TIN
TOUT
N33
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
4.87
4.69
4.58
4.76
IN → OUT
AD0 to AD4
→DO0 to DO31 (HH)
MIN.
MAX.
H01
:
H32
H33
:
DI0
:
2.4
:
N01
:
N32
N33
DO0
:
23.7
:
(LH)
2.98
2.89
2.62
2.70
7.95
7.63
7.79
8.12
DI31
AD0
:
2.4
2.4
:
DO31
TOUT
23.7
26.0
(HL)
(LL)
H37
H38
H39
H40
H41
H42
AD4
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
2.5
CSB
(LL)
→DO0 to DO31 (LH)
(HL)
2.51
2.51
1.27
4.29
4.29
2.03
7.20
7.20
3.28
REB
(LH)
1.02
1.12
1.64
1.69
2.65
2.62
→DO0 to DO31 (HL)
DI0 to DI31
→DO0 to DO31 (LL)
(HH)
1.86
1.74
3.26
2.76
5.53
4.42
Equivalent Cells
Power (mW/MHz)
Rev.
5694
1
74
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
8.12
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
8.12
2.62
7.21
3.28
1.27
2.51
2.65
2.62
REB output hold time
REB output set time
1.12
1.02
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.72
5.10
5.10
2.06
0.56
3.03
1.10
6.42
Block Library A13071EJ4V0BL00
75
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBHB
64 words × 32 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N32
H32
H33
DI31
AD0
DO31
H38
AD5
H39
H40
H41
WEB
REB
CSB
H42
H43
TIN
TOUT
N33
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H32
H33
:
DI0
:
2.4
:
N01
:
N32
N33
DO0
:
23.7
:
IN → OUT
AD0 to AD5
→DO0 to DO31 (HH)
MIN.
MAX.
(LH)
3.05
3.01
2.60
2.65
4.73
4.65
4.64
4.73
7.47
7.32
7.97
8.13
DI31
AD0
:
2.4
2.4
:
DO31
TOUT
23.7
26.0
(HL)
(LL)
H38
H39
H40
H41
H42
H43
AD5
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
2.5
CSB
(LL)
→DO0 to DO31 (LH)
(HL)
2.47
2.47
1.18
4.44
4.44
1.92
7.65
7.65
3.12
REB
(LH)
0.90
0.92
1.46
1.45
2.36
2.31
→DO0 to DO31 (HL)
DI0 to DI31
→DO0 to DO31 (LL)
(HH)
1.75
1.61
3.22
2.92
5.62
5.06
Equivalent Cells
Power (mW/MHz)
Rev.
8411
1
76
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
8.13
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
8.13
2.60
7.65
3.12
1.18
2.47
2.38
2.31
REB output hold time
REB output set time
0.93
0.90
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.31
3.82
3.82
3.16
0.33
2.47
1.80
5.17
Block Library A13071EJ4V0BL00
77
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBHD
128 words × 32 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N32
H32
H33
DI31
AD0
DO31
H39
AD6
H40
H41
H42
WEB
REB
CSB
H43
H44
TIN
TOUT
N33
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
4.68
4.60
4.42
4.51
IN → OUT
AD0 to AD6
→DO0 to DO31 (HH)
MIN.
MAX.
H01
:
H32
H33
:
DI0
:
2.4
:
N01
:
N32
N33
DO0
:
23.7
:
(LH)
2.12
2.07
1.89
1.93
8.86
8.72
8.56
8.71
DI31
AD0
:
2.4
2.4
:
DO31
TOUT
23.7
26.0
(HL)
(LL)
H39
H40
H41
H42
H43
H44
AD6
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO31 (LH)
(HL)
1.10
1.10
1.02
3.63
3.63
1.74
7.75
7.75
2.91
REB
(LH)
0.88
0.76
1.55
1.33
2.64
2.25
→DO0 to DO31 (HL)
DI0 to DI31
→DO0 to DO31 (LL)
(HH)
1.85
1.64
3.46
2.99
6.09
5.20
Equivalent Cells
Power (mW/MHz)
Rev.
14311
1
78
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.41
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.41
2.18
7.75
2.91
1.18
3.31
2.64
2.25
REB output hold time
REB output set time
0.88
1.02
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
9.81
3.88
3.88
1.86
1.35
3.32
0.97
6.13
Block Library A13071EJ4V0BL00
79
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBHF
256 words × 32 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N32
H32
H33
DI31
AD0
DO31
H40
AD7
H41
H42
H43
WEB
REB
CSB
H44
H45
TIN
TOUT
N33
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H32
H33
:
DI0
:
2.4
:
N01
:
N32
N33
DO0
:
23.7
:
IN → OUT
AD0 to AD7
→DO0 to DO31 (HH)
MIN.
MAX.
(LH)
2.38
2.36
2.02
2.04
5.30
5.26
4.72
4.75
10.06
9.98
9.11
9.18
DI31
AD0
:
2.4
2.4
:
DO31
TOUT
23.7
26.0
(HL)
(LL)
H40
H41
H42
H43
H44
H45
AD7
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO31 (LH)
(HL)
1.13
1.13
1.02
4.03
4.03
1.74
8.74
8.74
2.91
REB
(LH)
0.98
0.76
1.65
1.31
2.73
2.21
→DO0 to DO31 (HL)
DI0 to DI31
→DO0 to DO31 (LL)
(HH)
1.99
1.75
3.70
3.23
6.49
5.65
Equivalent Cells
Power (mW/MHz)
Rev.
24189
1
80
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.06
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.06
2.34
8.75
2.91
1.18
3.41
2.73
2.21
REB output hold time
REB output set time
0.87
1.13
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.55
4.23
4.23
1.94
1.38
3.58
1.03
6.66
Block Library A13071EJ4V0BL00
81
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBHH
512 words × 32 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N32
H32
H33
DI31
AD0
DO31
H41
AD8
H42
H43
H44
WEB
REB
CSB
H45
H46
TIN
TOUT
N33
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
5.15
5.03
4.80
4.83
IN → OUT
AD0 to AD8
→DO0 to DO31 (HH)
MIN.
MAX.
H01
:
H32
H33
:
DI0
:
2.4
:
N01
:
N32
N33
DO0
:
24.7
:
(LH)
1.74
1.64
1.57
1.52
10.72
10.57
10.07
10.22
DI31
AD0
:
2.4
2.4
:
DO31
TOUT
24.7
26.0
(HL)
(LL)
CSB
(LL)
→DO0 to DO31 (LH)
(HL)
1.48
1.48
1.38
4.60
4.60
2.40
9.69
9.69
4.07
H41
H42
H43
H44
H45
H46
AD8
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
2.4
2.4
5.0
REB
(LH)
1.23
1.07
2.02
1.87
3.31
3.18
→DO0 to DO31 (HL)
DI0 to DI31
→DO0 to DO31 (LL)
(HH)
2.18
2.03
4.00
3.73
6.97
6.51
Equivalent Cells
Power (mW/MHz)
Rev.
47955
1
82
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.72
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.72
1.76
9.70
4.07
1.59
4.43
3.31
3.18
REB output hold time
REB output set time
1.23
1.41
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.79
4.32
4.32
1.89
0.58
3.43
1.03
8.15
Block Library A13071EJ4V0BL00
83
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBKB
64 words × 40 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N40
H40
H41
DI39
AD0
DO39
H46
AD5
H47
H48
H49
WEB
REB
CSB
H50
H51
TIN
TOUT
N41
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
5.01
4.93
4.48
4.56
H01
:
H40
H41
:
DI0
:
2.4
:
N01
:
N40
N41
DO0
:
23.7
:
IN → OUT
AD0 to AD5
→DO0 to DO39 (HH)
MIN.
MAX.
(LH)
3.05
3.01
2.55
2.59
8.22
8.06
7.63
7.78
DI39
AD0
:
2.4
2.4
:
DO39
TOUT
23.7
26.0
(HL)
(LL)
H46
H47
H48
H49
H50
H51
AD5
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
2.5
CSB
(LL)
→DO0 to DO39 (LH)
(HL)
2.43
2.43
1.20
4.48
4.48
1.95
7.83
7.83
3.17
REB
(LH)
0.90
0.94
1.46
1.47
2.36
2.33
→DO0 to DO39 (HL)
DI0 to DI39
→DO0 to DO39 (LL)
(HH)
1.75
1.61
3.21
2.93
5.61
5.08
Equivalent Cells
Power (mW/MHz)
Rev.
10349
1
84
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
8.22
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
8.22
2.55
7.83
3.18
1.20
2.43
2.38
2.33
REB output hold time
REB output set time
0.94
0.90
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.86
4.09
4.09
2.44
0.33
2.31
1.03
5.71
Block Library A13071EJ4V0BL00
85
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBKD
128 words × 40 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N40
H40
H41
DI39
AD0
DO39
H47
AD6
H48
H49
H50
WEB
REB
CSB
H51
H52
TIN
TOUT
N41
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
AD0 to AD6
→DO0 to DO39 (HH)
MIN.
MAX.
H01
:
H40
H41
:
DI0
:
2.4
:
N01
:
N40
N41
DO0
:
23.7
:
(LH)
3.07
2.99
1.78
1.67
5.50
5.36
4.46
4.53
9.47
9.22
8.83
9.20
DI39
AD0
:
2.4
2.4
:
DO39
TOUT
23.7
26.0
(HL)
(LL)
H47
H48
H49
H50
H51
H52
AD6
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
2.5
CSB
(LL)
→DO0 to DO39 (LH)
(HL)
2.81
2.81
1.56
5.10
5.10
2.55
8.83
8.83
4.16
REB
(LH)
1.27
1.41
1.99
2.22
3.18
3.53
→DO0 to DO39 (HL)
DI0 to DI39
→DO0 to DO39 (LL)
(HH)
1.99
1.97
3.57
3.49
6.15
5.97
Equivalent Cells
Power (mW/MHz)
Rev.
20195
1
86
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
9.47
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
9.47
1.67
8.84
4.16
1.56
2.82
3.18
3.54
REB output hold time
REB output set time
1.41
1.27
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.91
4.39
4.39
3.04
0.48
2.32
1.40
6.08
Block Library A13071EJ4V0BL00
87
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBKF
256 words × 40 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N40
H40
H41
DI39
AD0
DO39
H48
AD7
H49
H50
H51
WEB
REB
CSB
H52
H53
TIN
TOUT
N41
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
5.34
5.29
4.96
5.00
IN → OUT
AD0 to AD7
→DO0 to DO39 (HH)
MIN.
MAX.
H01
:
H40
H41
:
DI0
:
2.4
:
N01
:
N40
N41
DO0
:
23.7
:
(LH)
2.33
2.30
2.14
2.16
10.25
10.18
9.57
DI39
AD0
:
2.4
2.4
:
DO39
TOUT
23.7
26.0
(HL)
(LL)
9.63
H48
H49
H50
H51
H52
H53
AD7
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
5.0
CSB
(LL)
→DO0 to DO39 (LH)
(HL)
1.16
1.16
1.02
4.00
4.00
1.79
8.63
8.63
3.03
REB
(LH)
1.01
0.77
1.67
1.37
2.76
2.33
→DO0 to DO39 (HL)
DI0 to DI39
→DO0 to DO39 (LL)
(HH)
1.99
1.75
3.70
3.23
6.49
5.65
Equivalent Cells
Power (mW/MHz)
Rev.
29884
1
88
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.25
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.25
2.47
8.65
3.04
1.18
3.48
2.77
2.33
REB output hold time
REB output set time
0.90
1.16
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.80
4.49
4.49
1.93
1.38
3.52
1.09
6.61
Block Library A13071EJ4V0BL00
89
HIGH DENSITY SINGLE-PORT RAM BLOCK
Block Type
Function
SSI Family
RBKH
512 words × 40 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
N01
N40
H40
H41
DI39
AD0
DO39
H49
AD8
H50
H51
H52
WEB
REB
CSB
H53
H54
TIN
TOUT
N41
TEB
Truth Table
X
: Irrelevant
TEB TIN
DIn ADn CSB WEB REB DOn TOUT
Operation
DIn : Input data
ADn : Address data
CSB : Chip select
WEB : Write enable
REB : Read enable
DOn : Output data
TEB : Test enable
TIN : Test clock
TOUT: Output test
result
1
1
1
1
1
0
X
DIn ADn
DIn ADn
0
0
0
1
X
X
0
0
1
X
1
X
1
0
0
X
1
X
0
DIn
DOn
0
X
Write
X
X
Write , Read
Read
X
X
X
X
X
X
ADn
X
X
X
Hold
X
X
0
X
Hold
CLOCK
X
X
Result
Test Mode
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
5.24
5.12
4.99
5.00
IN → OUT
AD0 to AD8
→DO0 to DO39 (HH)
MIN.
MAX.
H01
:
H40
H41
:
DI0
:
2.4
:
N01
:
N40
N41
DO0
:
24.7
:
(LH)
1.76
1.66
1.59
1.53
10.91
10.76
10.53
10.67
DI39
AD0
:
2.4
2.4
:
DO39
TOUT
24.7
26.0
(HL)
(LL)
H49
H50
H51
H52
H53
H54
AD8
WEB
REB
CSB
TIN
TEB
2.4
2.4
1.0
2.4
2.4
5.0
CSB
(LL)
→DO0 to DO39 (LH)
(HL)
1.50
1.50
1.39
4.57
4.57
2.45
9.59
9.59
4.18
REB
(LH)
1.24
1.09
2.04
1.93
3.34
3.30
→DO0 to DO39 (HL)
DI0 to DI39
→DO0 to DO39 (LL)
(HH)
2.18
2.03
4.00
3.73
6.97
6.51
Equivalent Cells
Power (mW/MHz)
Rev.
49856
1
90
Block Library A13071EJ4V0BL00
HIGH DENSITY SINGLE-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.91
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.91
1.76
9.60
4.19
1.60
5.57
3.35
3.30
REB output hold time
REB output set time
1.26
1.44
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.05
4.59
4.59
1.88
0.58
3.38
1.08
8.10
Block Library A13071EJ4V0BL00
91
[MEMO]
92
Block Library A13071EJ4V0BL00
CHAPTER 2
HIGH DENSITY
DUAL-PORT RAM BLOCK
(Soft Macro)
Block Library A13071EJ4V0BL00
93
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R947
16 words × 4 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H04
H05
DI3
DO3
RA0
N04
H09
WA0
H08
WA3
RA3
H12
H13
H14
WEB
WSB
RSB
H15
N05
H16
H17
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
DI0
:
2.4
:
N01
:
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA3
→DO0 to DO3
(LH)
(HH)
(HL)
(LL)
1.28
1.28
2.20
2.20
3.48
3.48
4.12
4.12
7.06
7.06
7.26
7.26
H04
H05
:
H08
H09
:
H12
H13
H14
H15
H16
H17
DI3
WA0
:
WA3
RA0
:
RA3
WEB
WSB
RSB
TIN
TEB
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N04
N05
DO3
TOUT
23.7
26.0
RSB
→DO0 to DO3
(LH)
(HL)
0.61
0.70
1.00
1.05
1.65
1.64
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
1.47
1.56
2.98
3.13
5.44
5.69
Equivalent Cells
Power (mW/MHz)
883
Rev.
1
94
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
7.26
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
7.26
1.90
1.65
2.20
0.70
0.61
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
8.14
5.10
5.10
2.83
0.21
3.34
0.31
tDH
tWEC
8.28
Block Library A13071EJ4V0BL00
95
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R949
32 words × 4 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H04
H05
DI3
DO3
RA0
N04
H10
WA0
H09
WA4
RA4
H14
H15
H16
WEB
WSB
RSB
H17
N05
H18
H19
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H04
H05
:
H09
H10
:
H14
H15
H16
H17
H18
H19
DI0
:
DI3
WA0
:
WA5
RA0
:
RA5
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N04
N05
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA5
→DO0 to DO3
(LH)
(HH)
(HL)
(LL)
1.38
1.38
2.30
2.30
3.61
3.61
4.26
4.26
7.26
7.26
7.46
7.46
DO3
TOUT
23.7
26.0
RSB
(LH)
(HL)
0.62
0.71
1.01
1.06
1.66
1.65
→DO0 to DO3
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
1.48
1.57
3.02
3.18
5.54
5.79
Equivalent Cells
Power (mW/MHz)
1427
Rev.
1
96
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
7.46
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
7.46
1.99
1.66
2.21
0.71
0.62
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
8.56
5.50
5.50
2.84
0.22
3.35
0.32
tDH
tWEC
8.38
Block Library A13071EJ4V0BL00
97
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R94B
64 words × 4 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H04
H05
DI3
DO3
RA0
N04
H11
WA0
H10
WA5
RA5
H16
H17
H18
WEB
WSB
RSB
H19
N05
H20
H21
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H04
H05
:
H10
H11
:
H16
H17
H18
H19
H20
H21
DI0
:
DI3
WA0
:
WA5
RA0
:
RA5
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
2.5
N01
:
N04
N05
DO0
:
24.7
:
IN → OUT
MIN.
MAX.
RA0 to RA5
→DO0 to DO3
(LH)
(HH)
(HL)
(LL)
0.54
0.46
1.53
1.46
3.22
3.17
3.91
3.87
7.60
7.60
7.80
7.80
DO3
TOUT
24.7
26.0
RSB
(LH)
(HL)
0.89
1.04
1.38
1.53
2.18
2.35
→DO0 to DO3
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
1.67
1.86
3.30
3.61
5.96
6.45
Equivalent Cells
Power (mW/MHz)
2636
Rev.
1
98
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
7.80
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
7.80
2.08
2.23
2.36
1.04
0.89
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
8.60
5.54
5.54
2.74
0.32
3.35
0.42
tDH
tWEC
8.84
Block Library A13071EJ4V0BL00
99
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R94D
128 words × 4 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H04
H05
DI3
DO3
RA0
N04
H12
WA0
H11
WA6
RA6
H18
H19
H20
WEB
WSB
RSB
H21
N05
H22
H23
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H04
H05
:
H11
H12
:
H18
H19
H20
H21
H22
H23
DI0
:
DI3
WA0
:
WA6
RA0
:
RA6
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N04
N05
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA6
→DO0 to DO3
(LH)
(HH)
(HL)
(LL)
1.71
1.71
2.58
2.58
4.10
4.10
4.72
4.72
8.01
8.01
8.21
8.21
DO3
TOUT
23.7
26.0
RSB
(LH)
(HL)
0.62
0.71
1.01
1.06
1.66
1.65
→DO0 to DO3
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
1.77
1.81
3.48
3.58
6.28
6.45
Equivalent Cells
Power (mW/MHz)
4052
Rev.
1
100
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
8.21
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
8.21
2.27
1.66
1.65
0.71
0.62
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
8.94
5.38
5.38
3.34
0.22
3.35
0.32
tDH
tWEC
9.08
Block Library A13071EJ4V0BL00
101
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R94F
256 words × 4 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H04
H05
DI3
DO3
RA0
N04
H13
WA0
H12
WA7
RA7
H20
H21
H22
WEB
WSB
RSB
H23
N05
H24
H25
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H04
H05
:
H12
H13
:
H20
H21
H22
H23
H24
H25
DI0
:
DI3
WA0
:
WA7
RA0
:
RA7
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N04
N05
DO0
:
21.7
:
IN → OUT
MIN.
MAX.
RA0 to RA7
→DO0 to DO3
(LH)
(HH)
(HL)
(LL)
0.54
0.46
1.53
1.46
3.51
3.46
4.20
4.15
8.35
8.35
8.55
8.55
DO3
TOUT
21.7
26.0
RSB
(LH)
(HL)
0.90
1.05
1.39
1.55
2.18
2.37
→DO0 to DO3
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
1.97
2.11
3.77
4.02
6.70
7.12
Equivalent Cells
Power (mW/MHz)
7837
Rev.
1
102
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
8.55
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
8.55
2.29
2.23
2.37
1.05
0.90
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
9.01
5.44
5.44
3.24
0.33
3.36
0.43
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
9.55
Block Library A13071EJ4V0BL00
103
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R94H
512 words × 4 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H04
H05
DI3
DO3
RA0
N04
H14
WA0
H13
WA8
RA8
H22
H23
H24
WEB
WSB
RSB
H25
N05
H26
H27
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H04
H05
:
H13
H14
:
H22
H23
H24
H25
H26
H27
DI0
:
DI3
WA0
:
WA8
RA0
:
RA8
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N04
N05
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA8
→DO0 to DO3
(LH)
(HH)
(HL)
(LL)
0.68
0.73
1.78
1.86
3.83
3.86
4.59
4.64
8.97
8.97
9.17
9.17
DO3
TOUT
23.7
26.0
RSB
(LH)
(HL)
1.26
1.59
1.94
2.41
3.05
3.75
→DO0 to DO3
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
2.05
2.36
3.88
4.43
6.86
7.80
Equivalent Cells
Power (mW/MHz)
15343
Rev.
1
104
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
9.17
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
9.17
2.30
3.62
3.76
1.59
1.26
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
10.06
5.56
5.56
3.32
1.18
3.47
1.28
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
10.27
Block Library A13071EJ4V0BL00
105
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R94M
1K words × 4 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H04
H05
DI3
DO3
RA0
N04
H15
WA0
H14
WA9
RA9
H24
H25
H26
WEB
WSB
RSB
H27
N05
H28
H29
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H04
H05
:
H14
H15
:
H24
H25
H26
H27
H28
H29
DI0
:
DI3
WA0
:
WA9
RA0
:
RA9
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N04
N05
DO0
:
21.7
:
IN → OUT
MIN.
MAX.
RA0 to RA9
→DO0 to DO3
(LH)
(HH)
(HL)
(LL)
0.96
1.01
1.86
1.92
4.13
4.16
4.77
4.80
9.31
9.31
9.51
9.51
DO3
TOUT
21.7
26.0
RSB
(LH)
(HL)
1.59
1.63
2.46
2.41
3.89
3.68
→DO0 to DO3
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
2.33
2.54
4.30
4.71
7.53
8.25
Equivalent Cells
Power (mW/MHz)
30396
Rev.
1
106
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
9.51
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
9.51
2.29
3.89
3.69
1.63
1.59
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
10.57
5.88
5.88
3.47
1.22
3.73
1.32
tDH
tWEC
10.53
Block Library A13071EJ4V0BL00
107
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R94S
2K words × 4 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H04
H05
DI3
DO3
RA0
N04
H16
WA0
H15
WA10
RA10
H26
H27
H28
WEB
WSB
RSB
H29
N05
H30
H31
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
X
X
X
1
0
0
X
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
MIN.
MAX.
H01
:
H04
H05
:
H15
H16
:
H26
H27
H28
H29
H30
H31
DI0
:
DI3
WA0
:
WA10
RA0
:
RA10
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
2.5
N01
:
N04
N05
DO0
:
17.7
:
RA0 to RA10
→DO0 to DO3
(LH)
(HH)
(HL)
(LL)
1.20
1.14
2.14
2.03
4.41
4.37
5.07
5.00
9.65
9.65
9.85
9.85
DO3
TOUT
17.7
26.0
RSB
(LH)
(HL)
1.76
1.81
2.67
2.70
4.17
4.16
→DO0 to DO3
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
2.44
2.70
4.45
5.00
7.72
8.74
Equivalent Cells
Power (mW/MHz)
60537
Rev.
1
108
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
9.85
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
9.85
2.08
4.17
4.16
1.81
1.76
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
10.81
5.93
5.93
3.53
1.35
3.78
1.45
tDH
tWEC
10.84
Block Library A13071EJ4V0BL00
109
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R94U
4K words × 4 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H04
H05
DI3
DO3
RA0
N04
H17
WA0
H16
WA11
RA11
H28
H29
H30
WEB
WSB
RSB
H31
N05
H32
H33
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
X
X
X
1
0
0
X
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H04
H05
:
H16
H17
:
H28
H29
H30
H31
H32
H33
DI0
:
DI3
WA0
:
WA11
RA0
:
RA11
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N04
N05
DO0
:
17.7
:
IN → OUT
MIN.
MAX.
RA0 to RA11
→DO0 to DO3
(LH)
(HH)
(HL)
(LL)
1.40
1.44
2.36
2.39
4.95
4.97
5.62
5.64
10.73
10.73
10.93
10.93
DO3
TOUT
17.7
26.0
RSB
(LH)
(HL)
2.14
2.26
3.26
3.38
5.09
5.22
→DO0 to DO3
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
2.76
3.05
4.92
5.54
8.44
9.59
Equivalent Cells
Power (mW/MHz)
120704
Rev.
1
110
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
10.93
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
10.93
2.50
5.09
5.23
2.26
2.14
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
11.42
5.89
5.89
3.73
1.80
3.78
1.90
tDH
tWEC
11.70
Block Library A13071EJ4V0BL00
111
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R987
16 words × 8 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H08
H09
DI7
DO7
RA0
N08
H13
WA0
H12
WA3
RA3
H16
H17
H18
WEB
WSB
RSB
H19
N09
H20
H21
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H08
H09
:
H12
H13
:
H16
H17
H18
H19
H20
H21
DI0
:
DI7
WA0
:
WA3
RA0
:
RA3
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N08
N09
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA3
→DO0 to DO7
(LH)
(HH)
(HL)
(LL)
1.30
1.30
2.21
2.22
3.50
3.50
4.14
4.15
7.10
7.10
7.30
7.30
DO7
TOUT
23.7
26.0
RSB
(LH)
(HL)
0.64
0.72
1.04
1.08
1.69
1.68
→DO0 to DO7
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
1.47
1.56
2.98
3.13
5.44
5.69
Equivalent Cells
Power (mW/MHz)
1554
Rev.
1
112
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
7.30
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
7.30
1.92
1.70
1.69
0.73
0.64
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
8.22
5.14
5.14
2.86
0.22
3.29
0.36
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.34
Block Library A13071EJ4V0BL00
113
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R989
32 words × 8 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H08
H09
DI7
DO7
RA0
N08
H14
WA0
H13
WA4
RA4
H18
H19
H20
WEB
WSB
RSB
H21
N09
H22
H23
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
MIN.
MAX.
H01
:
H08
H09
:
H13
H14
:
DI0
:
DI7
WA0
:
WA4
RA0
:
2.4
:
2.4
2.4
:
2.4
2.4
:
N01
:
N08
N09
DO0
:
23.7
:
RA0 to RA4
→DO0 to DO7
(LH)
(HH)
(HL)
(LL)
1.40
1.40
2.31
2.32
3.64
3.64
4.28
4.29
7.30
7.30
7.50
7.50
DO7
TOUT
23.7
26.0
RSB
(LH)
(HL)
0.65
0.73
1.05
1.09
1.70
1.69
→DO0 to DO7
H18
H19
H20
H21
H22
H23
RA4
WEB
WSB
RSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
2.5
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
1.48
1.57
3.02
3.18
5.54
5.79
Equivalent Cells
Power (mW/MHz)
2632
Rev.
1
114
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
7.50
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
7.50
2.01
1.71
1.70
0.73
0.65
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
8.64
5.54
5.54
2.87
0.23
3.30
0.37
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.44
Block Library A13071EJ4V0BL00
115
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R98B
64 words × 8 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H08
H09
DI7
DO7
RA0
N08
H15
WA0
H14
WA5
RA5
H20
H21
H22
WEB
WSB
RSB
H23
N09
H24
H25
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H08
H09
:
H14
H15
:
H20
H21
H22
H23
H24
H25
DI0
:
DI7
WA0
:
WA5
RA0
:
RA5
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N08
N09
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA5
→DO0 to DO7
(LH)
(HH)
(HL)
(LL)
1.56
1.56
2.47
2.47
3.87
3.87
4.51
4.51
7.64
7.64
7.84
7.84
DO7
TOUT
23.7
26.0
RSB
(LH)
(HL)
0.65
0.75
1.06
1.12
1.72
1.72
→DO0 to DO7
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
1.61
1.69
3.23
3.38
5.88
6.12
Equivalent Cells
Power (mW/MHz)
3446
Rev.
1
116
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
7.84
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
7.84
2.17
1.73
1.73
0.75
0.65
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
7.94
5.38
5.38
2.34
0.22
3.25
0.32
tDH
tWEC
8.81
Block Library A13071EJ4V0BL00
117
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R98D
128 words × 8 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H08
H09
DI7
DO7
RA0
N08
H16
WA0
H15
WA6
RA6
H22
H23
H24
WEB
WSB
RSB
H25
N09
H26
H27
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H08
H09
:
H15
H16
:
H22
H23
H24
H25
H26
H27
DI0
:
DI7
WA0
:
WA6
RA0
:
RA6
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
2.5
N01
:
N08
N09
DO0
:
24.7
:
IN → OUT
MIN.
MAX.
RA0 to RA6
→DO0 to DO7
(LH)
(HH)
(HL)
(LL)
0.56
0.48
1.56
1.50
3.38
3.33
4.08
4.04
7.98
7.98
8.18
8.18
DO7
TOUT
24.7
26.0
RSB
(LH)
(HL)
0.93
1.09
1.43
1.60
2.24
2.44
→DO0 to DO7
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
1.81
1.99
3.52
3.82
6.30
6.79
Equivalent Cells
Power (mW/MHz)
6613
Rev.
1
118
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
8.18
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
8.18
2.17
2.25
2.45
1.09
0.93
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
8.00
5.43
5.43
2.24
0.33
3.26
0.43
tDH
tWEC
9.28
Block Library A13071EJ4V0BL00
119
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R98F
256 words × 8 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H08
H09
DI7
DO7
RA0
N08
H17
WA0
H16
WA7
RA7
H24
H25
H26
WEB
WSB
RSB
H27
N09
H28
H29
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H08
H09
:
H16
H17
:
H24
H25
H26
H27
H28
H29
DI0
:
DI7
WA0
:
WA7
RA0
:
RA7
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N08
N09
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA7
→DO0 to DO7
(LH)
(HH)
(HL)
(LL)
2.16
2.16
2.87
2.87
4.75
4.75
5.27
5.27
8.98
8.98
9.18
9.18
DO7
TOUT
23.7
26.0
RSB
(LH)
(HL)
0.67
0.80
1.08
1.19
1.74
1.83
→DO0 to DO7
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
2.14
2.06
4.09
3.99
7.27
7.14
Equivalent Cells
Power (mW/MHz)
10369
Rev.
1
120
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
9.18
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
9.18
2.57
1.75
1.83
0.80
0.67
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
9.78
5.62
5.62
3.94
0.22
3.45
0.42
tDH
tWEC
10.10
Block Library A13071EJ4V0BL00
121
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R98H
512 words × 8 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H08
H09
DI7
DO7
RA0
N08
H18
WA0
H17
WA8
RA8
H26
H27
H28
WEB
WSB
RSB
H29
N09
H30
H31
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
X
X
X
1
0
0
X
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H08
H09
:
H17
H18
:
DI0
:
DI7
WA0
:
WA8
RA0
:
2.4
:
2.4
2.4
:
2.4
2.4
:
N01
:
N08
N09
DO0
:
24.7
:
IN → OUT
MIN.
MAX.
RA0 to RA8
→DO0 to DO7
(LH)
(HH)
(HL)
(LL)
0.60
0.52
1.58
1.53
3.91
3.86
4.60
4.57
9.32
9.32
9.52
9.52
DO7
TOUT
24.7
26.0
RSB
(LH)
(HL)
0.97
1.12
1.47
1.66
2.30
2.54
→DO0 to DO7
H26
H27
H28
H29
H30
H31
RA8
WEB
WSB
RSB
TIN
TEB
2.4
2.4
2.4
2.4
2.4
2.5
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
2.34
2.36
4.37
4.44
7.69
7.82
Equivalent Cells
20418
Power (mW/MHz)
Rev.
1
122
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
9.52
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
9.52
2.57
2.41
2.55
1.12
0.97
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
9.87
5.68
5.68
3.85
0.34
3.46
0.54
tDH
tWEC
10.57
Block Library A13071EJ4V0BL00
123
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R98M
1K words × 8 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H08
H09
DI7
DO7
RA0
N08
H19
WA0
H18
WA9
RA9
H28
H29
H30
WEB
WSB
RSB
H31
N09
H32
H33
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H08
H09
:
H18
H19
:
H28
H29
H30
H31
H32
H33
DI0
:
DI7
WA0
:
WA9
RA0
:
RA9
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N08
N09
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA9
→DO0 to DO7
(LH)
(HH)
(HL)
(LL)
4.28
4.28
4.14
4.14
7.23
7.23
7.21
7.21
12.03
12.03
12.23
12.23
DO7
TOUT
23.7
26.0
RSB
(LH)
(HL)
0.74
0.90
1.17
1.31
1.87
2.00
→DO0 to DO7
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
4.15
3.74
6.99
6.75
11.63
11.66
Equivalent Cells
Power (mW/MHz)
37239
Rev.
1
124
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
12.23
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
12.23
3.84
1.87
2.00
0.90
0.74
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
12.74
6.58
6.58
5.94
0.22
4.05
0.52
tDH
tWEC
14.40
Block Library A13071EJ4V0BL00
125
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R98S
2K words × 8 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H08
H09
DI7
DO7
RA0
N08
H20
WA0
H19
WA10
RA10
H30
H31
H32
WEB
WSB
RSB
H33
N09
H34
H35
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
X
X
X
1
0
0
X
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
MIN.
MAX.
H01
:
H08
H09
:
H19
H20
:
H30
H31
H32
H33
H34
H35
DI0
:
DI7
WA0
:
WA10
RA0
:
RA10
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
2.5
N01
:
N08
N09
DO0
:
24.7
:
RA0 to RA10
→DO0 to DO7
(LH)
(HH)
(HL)
(LL)
0.66
0.59
1.67
1.61
5.12
5.08
5.82
5.79
12.40
12.40
12.60
12.60
DO7
TOUT
24.7
26.0
RSB
(LH)
(HL)
1.06
1.23
1.58
1.80
2.44
2.73
→DO0 to DO7
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
4.36
4.05
7.29
7.22
12.07
12.38
74136
Rev.
1
Equivalent Cells
Power (mW/MHz)
126
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
12.60
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
12.60
1.55
2.60
2.74
1.23
1.06
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
12.87
6.66
6.66
5.86
0.35
4.08
0.65
tDH
tWEC
14.90
Block Library A13071EJ4V0BL00
127
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9AB
64 words × 10 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H10
H11
DI9
DO9
RA0
N10
H17
WA0
H16
WA5
RA5
H22
H23
H24
WEB
WSB
RSB
H25
N11
H26
H27
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H10
H11
:
H16
H17
:
H22
H23
H24
H25
H26
H27
DI0
:
DI9
WA0
:
WA5
RA0
:
RA5
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N10
N11
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA5
→DO0 to DO9
(LH)
(HH)
(HL)
(LL)
1.56
1.56
2.49
2.49
3.88
3.88
4.53
4.53
7.67
7.67
7.87
7.87
DO9
TOUT
23.7
26.0
RSB
(LH)
(HL)
0.66
0.77
1.07
1.14
1.75
1.76
→DO0 to DO9
DI0 to DI9
→DO0 to DO9
(HH)
(LL)
1.60
1.69
3.23
3.38
5.88
6.13
Equivalent Cells
Power (mW/MHz)
4187
Rev.
1
128
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
7.87
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
7.87
2.18
1.76
1.77
0.77
0.66
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
8.04
5.38
5.38
2.44
0.22
3.25
0.32
tDH
tWEC
8.85
Block Library A13071EJ4V0BL00
129
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9AD
128 words × 10 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H10
H11
DI9
DO9
RA0
N10
H18
WA0
H17
WA6
RA6
H24
H25
H26
WEB
WSB
RSB
H27
N11
H28
H29
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H10
H11
:
H17
H18
:
H24
H25
H26
H27
H28
H29
DI0
:
DI9
WA0
:
WA6
RA0
:
RA6
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
2.5
N01
:
N10
N11
DO0
:
24.7
:
IN → OUT
MIN.
MAX.
RA0 to RA6
→DO0 to DO9
(LH)
(HH)
(HL)
(LL)
0.57
0.49
1.58
1.51
3.40
3.35
4.10
4.06
8.02
8.02
8.22
8.22
DO9
TOUT
24.7
26.0
RSB
(LH)
(HL)
0.94
1.11
1.44
1.63
2.27
2.49
→DO0 to DO9
DI0 to DI9
→DO0 to DO9
(HH)
(LL)
1.80
1.99
3.51
3.82
6.30
6.80
Equivalent Cells
Power (mW/MHz)
8079
Rev.
1
130
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
8.22
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
8.22
2.19
2.35
2.49
1.11
0.94
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
9.60
5.44
5.44
3.94
0.22
3.45
0.42
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
10.16
Block Library A13071EJ4V0BL00
131
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9AF
256 words × 10 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H10
H11
DI9
DO9
RA0
N10
H19
WA0
H18
WA7
RA7
H26
H27
H28
WEB
WSB
RSB
H29
N11
H30
H31
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H10
H11
:
H18
H19
:
H26
H27
H28
H29
H30
H31
DI0
:
DI9
WA0
:
WA7
RA0
:
RA7
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N10
N11
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA7
→DO0 to DO9
(LH)
(HH)
(HL)
(LL)
2.17
2.17
2.91
2.91
4.76
4.76
5.30
5.30
8.99
8.99
9.19
9.19
DO9
TOUT
23.7
26.0
RSB
(LH)
(HL)
0.69
0.84
1.11
1.24
1.79
1.90
→DO0 to DO9
DI0 to DI9
→DO0 to DO9
(HH)
(LL)
2.14
2.06
4.09
3.99
7.27
7.14
Equivalent Cells
Power (mW/MHz)
12791
Rev.
1
132
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
9.19
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
9.19
2.61
1.80
1.90
1.11
0.69
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
9.78
5.62
5.62
3.94
0.22
3.45
0.42
tDH
tWEC
10.16
Block Library A13071EJ4V0BL00
133
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9AH
512 words × 10 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H10
H11
DI9
DO9
RA0
N10
H20
WA0
H19
WA8
RA8
H28
H29
H30
WEB
WSB
RSB
H31
N11
H32
H33
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
MIN.
MAX.
H01
:
H10
H11
:
H19
H20
:
H28
H29
H30
H31
H32
H33
DI0
:
DI9
WA0
:
WA8
RA0
:
RA8
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
2.5
N01
:
N10
N11
DO0
:
24.7
:
RA0 to RA8
→DO0 to DO9
(LH)
(HH)
(HL)
(LL)
0.62
0.53
1.62
1.56
3.93
3.88
4.63
4.59
9.34
9.34
9.54
9.54
DO9
TOUT
24.7
26.0
RSB
(LH)
(HL)
0.99
1.16
1.51
1.71
2.35
2.61
→DO0 to DO9
DI0 to DI9
→DO0 to DO9
(HH)
(LL)
2.34
2.37
4.37
4.45
7.69
7.83
Equivalent Cells
Power (mW/MHz)
25244
Rev.
1
134
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
9.54
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
9.54
2.61
2.48
2.62
1.16
0.99
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
9.88
5.69
5.69
3.85
0.34
3.47
0.54
tDH
tWEC
10.64
Block Library A13071EJ4V0BL00
135
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9AM
1K words × 10 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H10
H11
DI9
DO9
RA0
N10
H21
WA0
H20
WA9
RA9
H30
H31
H32
WEB
WSB
RSB
H33
N11
H34
H35
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H10
H11
:
H20
H21
:
H30
H31
H32
H33
H34
H35
DI0
:
DI9
WA0
:
WA9
RA0
:
RA9
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N10
N11
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA9
→DO0 to DO9
(LH)
(HH)
(HL)
(LL)
4.39
4.39
4.18
4.18
7.29
7.29
7.24
7.24
12.03
12.03
12.23
12.23
DO9
TOUT
23.7
26.0
RSB
(LH)
(HL)
0.79
0.94
1.22
1.37
1.93
2.09
→DO0 to DO9
DI0 to DI9
→DO0 to DO9
(HH)
(LL)
4.15
3.74
6.99
6.75
11.63
11.66
Equivalent Cells
Power (mW/MHz)
46281
Rev.
1
136
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
12.23
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
12.23
3.88
1.95
2.09
0.94
0.79
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
13.08
6.82
6.82
6.04
0.22
3.85
0.52
tDH
tWEC
14.40
Block Library A13071EJ4V0BL00
137
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9AS
2K words × 10 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H10
H11
DI9
DO9
RA0
N10
H22
WA0
H21
WA10
RA10
H32
H33
H34
WEB
WSB
RSB
H35
N11
H36
H37
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
X
X
X
1
0
0
X
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H10
H11
:
H21
H22
:
H32
H33
H34
H35
H36
H37
DI0
:
DI9
WA0
:
WA10
RA0
:
RA10
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
2.5
N01
:
N10
N11
DO0
:
24.7
:
IN → OUT
MIN.
MAX.
RA0 to RA10
→DO0 to DO9
(HH)
(LH)
(LL)
(HL)
0.72
0.64
1.70
1.65
5.16
5.11
5.84
5.81
12.40
12.40
12.60
12.60
DO9
TOUT
24.7
26.0
RSB
(LH)
(HL)
1.12
1.27
1.65
1.86
2.51
2.84
→DO0 to DO9
DI0 to DI9
→DO0 to DO9
(HH)
(LL)
4.37
4.05
7.29
7.22
12.07
12.38
Equivalent Cells
Power (mW/MHz)
92206
Rev.
1
138
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
12.60
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
12.60
1.60
2.70
2.84
1.27
1.12
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
13.22
6.90
6.90
5.96
0.36
3.88
0.66
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
15.14
Block Library A13071EJ4V0BL00
139
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9C7
16 words × 16 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H16
H17
DI15
WA0
DO15
RA0
N16
H21
H20
WA3
RA3
H24
H25
H26
WEB
WSB
RSB
H27
N17
H28
H29
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H16
H17
:
H20
H21
:
H24
H25
H26
H27
H28
H29
DI0
:
DI15
WA0
:
WA3
RA0
:
RA3
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N16
N17
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA3
→DO0 to DO15 (HH)
(LH)
1.36
1.34
2.25
2.28
3.59
3.57
4.21
4.23
7.22
7.22
7.42
7.42
DO15
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.69
0.78
1.10
1.16
1.78
1.79
→DO0 to DO15 (HL)
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
1.47
1.56
2.98
3.14
5.45
5.70
Equivalent Cells
Power (mW/MHz)
2902
Rev.
1
140
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
7.42
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
7.42
1.95
1.79
1.79
0.78
0.69
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
8.50
5.26
5.26
2.97
0.27
3.21
0.49
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.59
Block Library A13071EJ4V0BL00
141
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9C9
32 words × 16 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H16
H17
DI15
WA0
DO15
RA0
N16
H22
H21
WA4
RA4
H26
H27
H28
WEB
WSB
RSB
H29
N17
H30
H31
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H16
H17
:
H21
H22
:
H26
H27
H28
H29
H30
H31
DI0
:
DI15
WA0
:
WA4
RA0
:
RA4
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N16
N17
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA4
→DO0 to DO15 (HH)
(LH)
1.46
1.44
2.35
2.38
3.72
3.71
4.35
4.37
7.42
7.42
7.62
7.62
DO15
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.70
0.79
1.11
1.17
1.79
1.80
→DO0 to DO15 (HL)
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
1.48
1.57
3.03
3.18
5.55
5.80
Equivalent Cells
Power (mW/MHz)
5036
Rev.
1
142
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
7.62
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
7.62
2.05
1.80
1.80
0.79
0.70
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
8.92
5.66
5.66
2.98
0.28
3.22
0.50
tDH
tWEC
8.60
Block Library A13071EJ4V0BL00
143
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9CB
64 words × 16 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H16
H17
DI15
WA0
DO15
RA0
N16
H23
H22
WA5
RA5
H28
H29
H30
WEB
WSB
RSB
H31
N17
H32
H33
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H16
H17
:
H22
H23
:
H28
H29
H30
H31
H32
H33
DI0
:
DI15
WA0
:
WA5
RA0
:
RA5
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N16
N17
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA5
→DO0 to DO15 (HH)
(LH)
1.59
1.58
2.50
2.50
3.91
3.90
4.55
4.55
7.69
7.69
7.89
7.89
DO15
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.68
0.78
1.10
1.16
1.78
1.79
→DO0 to DO15 (HL)
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
1.61
1.69
3.24
3.38
5.89
6.13
Equivalent Cells
Power (mW/MHz)
6635
Rev.
1
144
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
7.89
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
7.89
2.19
1.78
1.79
0.78
0.68
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
8.05
5.44
5.44
2.37
0.24
3.21
0.38
tDH
tWEC
8.89
Block Library A13071EJ4V0BL00
145
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9CD
128 words × 16 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H16
H17
DI15
WA0
DO15
RA0
N16
H24
H23
WA6
RA6
H30
H31
H32
WEB
WSB
RSB
H33
N17
H34
H35
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H16
H17
:
H23
H24
:
H30
H31
H32
H33
H34
H35
DI0
:
DI15
WA0
:
WA6
RA0
:
RA6
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
2.5
N01
:
N16
N17
DO0
:
24.7
:
IN → OUT
MIN.
MAX.
RA0 to RA6
→DO0 to DO15 (HH)
(LH)
0.60
0.52
1.58
1.52
3.45
3.40
4.14
4.10
8.11
8.11
8.31
8.31
DO15
TOUT
24.7
26.0
(HL)
(LL)
RSB
(LH)
0.98
1.12
1.49
1.64
2.33
2.51
→DO0 to DO15 (HL)
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
1.82
1.99
3.53
3.82
6.32
6.80
Equivalent Cells
Power (mW/MHz)
12939
Rev.
1
146
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
8.31
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
8.31
2.21
2.34
2.51
1.12
0.98
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
8.22
5.56
5.56
2.34
0.32
3.17
0.51
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
9.44
Block Library A13071EJ4V0BL00
147
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9CF
256 words × 16 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H16
H17
DI15
WA0
DO15
RA0
N16
H25
H24
WA7
RA7
H32
H33
H34
WEB
WSB
RSB
H35
N17
H36
H37
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H16
H17
:
H24
H25
:
DI0
:
DI15
WA0
:
WA7
RA0
:
2.4
:
2.4
2.4
:
2.4
2.4
:
N01
:
N16
N17
DO0
:
23.7
:
IN → OUT
RA0 to RA7
→DO0 to DO15 (HH)
MIN.
MAX.
(LH)
2.20
2.19
2.90
2.90
4.80
4.79
5.31
5.31
9.04
9.04
9.24
9.24
DO15
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.71
0.84
1.13
1.24
1.81
1.90
→DO0 to DO15 (HL)
H32
H33
H34
H35
H36
H37
RA7
WEB
WSB
RSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
2.5
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
2.14
2.06
4.09
4.00
7.28
7.15
Equivalent Cells
20439
Power (mW/MHz)
Rev.
1
148
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
9.24
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
9.24
2.59
1.81
1.90
0.84
0.71
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
9.89
5.68
5.68
3.97
0.24
3.39
0.49
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
10.19
Block Library A13071EJ4V0BL00
149
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9CH
512 words × 16 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H16
H17
DI15
WA0
DO15
RA0
N16
H26
H25
WA8
RA8
H34
H35
H36
WEB
WSB
RSB
H37
N17
H38
H39
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H16
H17
:
H25
H26
:
H34
H35
H36
H37
H38
H39
DI0
:
DI15
WA0
:
WA8
RA0
:
RA8
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
2.5
N01
:
N16
N17
DO0
:
24.7
:
IN → OUT
MIN.
MAX.
RA0 to RA8
→DO0 to DO15 (HH)
(LH)
0.64
0.56
1.62
1.56
4.00
3.95
4.68
4.65
9.48
9.48
9.68
9.68
DO15
TOUT
24.7
26.0
(HL)
(LL)
RSB
(LH)
1.02
1.17
1.54
1.72
2.40
2.62
→DO0 to DO15 (HL)
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
2.34
2.37
4.38
4.45
7.71
7.85
Equivalent Cells
Power (mW/MHz)
40489
Rev.
1
150
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
9.68
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
9.68
2.60
2.48
2.62
1.17
1.02
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
10.14
5.83
5.83
3.98
0.33
3.37
0.63
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
10.77
Block Library A13071EJ4V0BL00
151
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9CM
1K words × 16 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H16
H17
DI15
WA0
DO15
RA0
N16
H27
H26
WA9
RA9
H36
H37
H38
WEB
WSB
RSB
H39
N17
H40
H41
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
MIN.
MAX.
H01
:
H16
H17
:
H26
H27
:
H36
H37
H38
H39
H40
H41
DI0
:
DI15
WA0
:
WA9
RA0
:
RA9
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N16
N17
DO0
:
23.7
:
RA0 to RA9
→DO0 to DO15 (HH)
(LH)
4.33
4.32
4.18
4.19
7.28
7.28
7.27
7.27
12.10
12.10
12.30
12.30
DO15
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.79
0.95
1.22
1.38
1.93
2.08
→DO0 to DO15 (HL)
DI0 to DI15
→DO0 to DO15 (LL)
(HH)
4.16
3.75
7.00
6.76
11.63
11.67
74160
Rev.
1
Equivalent Cells
Power (mW/MHz)
152
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
12.30
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
12.30
3.88
1.94
2.08
0.95
0.79
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
12.91
6.66
6.66
6.00
0.25
3.98
0.61
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
14.51
Block Library A13071EJ4V0BL00
153
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9EB
64 words × 20 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H20
H21
DI19
WA0
DO19
RA0
N20
H27
H26
WA5
RA5
H32
H33
H34
WEB
WSB
RSB
H35
N21
H36
H37
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H20
H21
:
H26
H27
:
H32
H33
H34
H35
H36
H37
DI0
:
DI19
WA0
:
WA5
RA0
:
RA5
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N20
N21
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA5
→DO0 to DO19 (HH)
(LH)
1.60
1.59
2.51
2.52
3.93
3.92
4.57
4.58
7.73
7.73
7.93
7.93
DO19
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.69
0.80
1.11
1.19
1.81
1.83
→DO0 to DO19 (HL)
DI0 to DI19
→DO0 to DO19 (LL)
(HH)
1.60
1.69
3.23
3.38
5.89
6.14
Equivalent Cells
Power (mW/MHz)
8125
Rev.
1
154
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
7.93
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
7.93
2.21
1.81
1.83
0.80
0.69
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
8.14
5.43
5.43
2.47
0.24
3.20
0.38
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.93
Block Library A13071EJ4V0BL00
155
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9ED
128 words × 20 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H20
H21
DI19
WA0
DO19
RA0
N20
H28
H27
WA6
RA6
H34
H35
H36
WEB
WSB
RSB
H37
N21
H38
H39
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H20
H21
:
H27
H28
:
H34
H35
H36
H37
H38
H39
DI0
:
DI19
WA0
:
WA6
RA0
:
RA6
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
2.5
N01
:
N20
N21
DO0
:
24.7
:
IN → OUT
MIN.
MAX.
RA0 to RA6
→DO0 to DO19 (HH)
(LH)
0.61
0.53
1.60
1.54
3.48
3.43
4.17
4.13
8.15
8.15
8.35
8.35
DO19
TOUT
24.7
26.0
(HL)
(LL)
RSB
(LH)
0.99
1.15
1.51
1.68
2.36
2.55
→DO0 to DO19 (HL)
DI0 to DI19
→DO0 to DO19 (LL)
(HH)
1.81
1.99
3.52
3.82
6.32
6.81
Equivalent Cells
Power (mW/MHz)
15878
Rev.
1
156
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
8.35
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
8.35
2.59
2.41
2.55
1.15
0.99
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
8.34
5.57
5.57
2.45
0.32
3.17
0.51
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
9.49
Block Library A13071EJ4V0BL00
157
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9EF
256 words × 20 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H20
H21
DI19
WA0
DO19
RA0
N20
H29
H28
WA7
RA7
H36
H37
H38
WEB
WSB
RSB
H39
N21
H40
H41
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H20
H21
:
H28
H29
:
H36
H37
H38
H39
H40
H41
DI0
:
DI19
WA0
:
WA7
RA0
:
RA7
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N20
N21
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA7
→DO0 to DO19 (HH)
(LH)
2.21
2.20
2.94
2.95
4.81
4.80
5.34
5.34
9.05
9.05
9.25
9.25
DO19
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.73
0.88
1.16
1.29
1.86
1.97
→DO0 to DO19 (HL)
DI0 to DI19
→DO0 to DO19 (LL)
(HH)
2.14
2.06
4.09
4.00
7.28
7.15
Equivalent Cells
Power (mW/MHz)
25290
Rev.
1
158
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
9.25
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
9.25
2.63
1.86
1.97
0.88
0.73
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
8.38
5.69
5.69
3.98
0.24
3.39
0.49
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
10.26
Block Library A13071EJ4V0BL00
159
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9EH
512 words × 20 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H20
H21
DI19
WA0
DO19
RA0
N20
H30
H29
WA8
RA8
H38
H39
H40
WEB
WSB
RSB
H41
N21
H42
H43
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
MIN.
MAX.
H01
:
H20
H21
:
H29
H30
:
H38
H39
H40
H41
H42
H43
DI0
:
DI19
WA0
:
WA8
RA0
:
RA8
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
2.5
N01
:
N20
N21
DO0
:
24.7
:
RA0 to RA8
→DO0 to DO19 (HH)
(LH)
0.65
0.58
1.66
1.59
4.01
3.97
4.72
4.67
9.50
9.50
9.70
9.70
DO19
TOUT
24.7
26.0
(HL)
(LL)
RSB
(LH)
1.04
1.21
1.58
1.77
2.46
2.70
→DO0 to DO19 (HL)
DI0 to DI19
→DO0 to DO19 (LL)
(HH)
2.34
2.37
4.38
4.45
7.71
7.85
Equivalent Cells
Power (mW/MHz)
50129
Rev.
1
160
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
9.70
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
9.70
2.63
2.56
2.70
1.21
1.04
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
10.17
5.84
5.84
3.99
0.34
3.37
0.64
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
10.84
Block Library A13071EJ4V0BL00
161
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9EM
1K words × 20 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H20
H21
DI19
WA0
DO19
RA0
N20
H31
H30
WA9
RA9
H40
H41
H42
WEB
WSB
RSB
H43
N21
H44
H45
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H20
H21
:
H30
H31
:
H40
H41
H42
H43
H44
H45
DI0
:
DI19
WA0
:
WA9
RA0
:
RA9
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N20
N21
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA9
→DO0 to DO19 (HH)
(LH)
4.44
4.43
4.22
4.22
7.35
7.35
7.29
7.29
12.11
12.11
12.31
12.31
DO19
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.84
0.99
1.28
1.44
2.01
2.17
→DO0 to DO19 (HL)
DI0 to DI19
→DO0 to DO19 (LL)
(HH)
4.16
3.75
7.00
6.76
11.64
11.67
Equivalent Cells
Power (mW/MHz)
92244
Rev.
1
162
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
12.31
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
12.31
3.92
2.04
2.18
0.99
0.84
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
13.25
6.90
6.90
6.10
0.25
3.78
0.61
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
14.52
Block Library A13071EJ4V0BL00
163
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9H7
16 words × 32 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H32
H33
DI31
WA0
DO31
RA0
N32
H37
H36
WA3
RA3
H40
H41
H42
WEB
WSB
RSB
H43
N33
H44
H45
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H32
H33
:
H36
H37
:
H40
H41
H42
H43
H44
H45
DI0
:
DI31
WA0
:
WA3
RA0
:
RA3
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N32
N33
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA3
→DO0 to DO31 (HH)
(LH)
1.48
1.43
2.35
2.40
3.76
3.73
4.37
4.40
7.47
7.47
7.67
7.67
DO31
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.80
0.90
1.23
1.31
1.94
1.99
→DO0 to DO31 (HL)
DI0 to DI31
→DO0 to DO31 (LL)
(HH)
1.48
1.57
2.99
3.14
5.45
5.70
Equivalent Cells
Power (mW/MHz)
5606
Rev.
1
164
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
7.67
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
7.67
2.04
1.94
2.00
0.90
0.80
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
9.12
5.54
5.54
3.23
0.35
3.01
0.76
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.82
Block Library A13071EJ4V0BL00
165
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9H9
32 words × 32 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H32
H33
DI31
WA0
DO31
RA0
N32
H38
H37
WA4
RA4
H42
H43
H44
WEB
WSB
RSB
H45
N33
H46
H47
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
MIN.
MAX.
H01
:
H32
H33
:
H37
H38
:
DI0
:
DI31
WA0
:
WA4
RA0
:
2.4
:
2.4
2.4
:
2.4
2.4
:
N01
:
N32
N33
DO0
:
23.7
:
RA0 to RA4
→DO0 to DO31 (HH)
(LH)
1.58
1.53
2.45
2.50
3.89
3.86
4.51
4.54
7.67
7.67
7.87
7.87
DO31
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.81
0.91
1.24
1.32
1.95
2.00
→DO0 to DO31 (HL)
H42
H43
H44
H45
H46
H47
RA4
WEB
WSB
RSB
TIN
TEB
2.4
2.4
1.0
1.0
2.4
2.5
DI0 to DI31
→DO0 to DO31 (LL)
(HH)
1.49
1.58
3.03
3.19
5.55
5.80
Equivalent Cells
Power (mW/MHz)
9852
Rev.
1
166
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
7.87
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
7.87
2.15
1.95
2.01
0.91
0.81
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
9.54
5.94
5.94
3.24
0.36
3.02
0.77
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.92
Block Library A13071EJ4V0BL00
167
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9HB
64 words × 32 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H32
H33
DI31
WA0
DO31
RA0
N32
H39
H38
WA5
RA5
H44
H45
H46
WEB
WSB
RSB
H47
N33
H48
H49
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H32
H33
:
H38
H39
:
H44
H45
H46
H47
H48
H49
DI0
:
DI31
WA0
:
WA5
RA0
:
RA5
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N32
N33
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA5
→DO0 to DO31 (HH)
(LH)
1.65
1.63
2.54
2.57
3.99
3.98
4.62
4.64
7.82
7.82
8.02
8.02
DO31
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.75
0.85
1.17
1.24
1.87
1.89
→DO0 to DO31 (HL)
DI0 to DI31
→DO0 to DO31 (LL)
(HH)
1.62
1.70
3.24
3.39
5.89
6.13
Equivalent Cells
Power (mW/MHz)
13026
Rev.
1
168
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
8.02
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
8.02
2.25
1.87
1.90
0.85
0.75
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
8.34
5.56
5.56
2.50
0.28
3.10
0.52
tDH
tWEC
9.05
Block Library A13071EJ4V0BL00
169
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9HD
128 words × 32 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H32
H33
DI31
WA0
DO31
RA0
N32
H40
H39
WA6
RA6
H46
H47
H48
WEB
WSB
RSB
H49
N33
H50
H51
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
RAn : B-port address (Read)
DIn : Input data
WEB : Write enable
RSB : B-port select
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H32
H33
:
H39
H40
:
H46
H47
H48
H49
H50
H51
DI0
:
DI31
WA0
:
WA6
RA0
:
RA6
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
2.5
N01
:
N32
N33
DO0
:
24.7
:
IN → OUT
MIN.
MAX.
RA0 to RA6
→DO0 to DO31 (HH)
(LH)
0.67
0.59
1.64
1.59
3.60
3.55
4.28
4.25
8.39
8.39
8.59
8.59
DO31
TOUT
24.7
26.0
(HL)
(LL)
RSB
(LH)
1.06
1.20
1.61
1.74
2.50
2.63
→DO0 to DO31 (HL)
DI0 to DI31
→DO0 to DO31 (LL)
(HH)
1.82
2.01
3.53
3.84
6.32
6.82
Equivalent Cells
Power (mW/MHz)
25605
Rev.
1
170
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
8.59
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
8.59
2.25
2.50
2.63
1.20
1.06
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
8.93
5.87
5.87
2.67
0.39
3.05
0.78
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
9.82
Block Library A13071EJ4V0BL00
171
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9HF
256 words × 32 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H32
H33
DI31
WA0
DO31
RA0
N32
H41
H40
WA7
RA7
H48
H49
H50
WEB
WSB
RSB
H51
N33
H52
H53
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H32
H33
:
H40
H41
:
H48
H49
H50
H51
H52
H53
DI0
:
DI31
WA0
:
WA7
RA0
:
RA7
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N32
N33
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA7
→DO0 to DO31 (HH)
(LH)
2.27
2.24
2.95
2.98
4.90
4.88
5.40
5.42
9.19
9.19
9.39
9.39
DO31
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.77
0.91
1.20
1.33
1.91
2.02
→DO0 to DO31 (HL)
DI0 to DI31
→DO0 to DO31 (LL)
(HH)
2.14
2.06
4.09
4.00
7.28
7.15
Equivalent Cells
Power (mW/MHz)
40559
Rev.
1
172
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
9.39
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
9.39
2.65
2.50
2.63
1.20
1.06
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
8.93
5.87
5.87
2.67
0.39
3.05
0.78
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
9.82
Block Library A13071EJ4V0BL00
173
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9HH
512 words × 32 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H32
H33
DI31
WA0
DO31
RA0
N32
H42
H41
WA8
RA8
H50
H51
H52
WEB
WSB
RSB
H53
N33
H54
H55
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H32
H33
:
H41
H42
:
DI0
:
DI31
WA0
:
WA8
RA0
:
2.4
:
2.4
2.4
:
2.4
2.4
:
N01
:
N32
N33
DO0
:
24.7
:
IN → OUT
MIN.
MAX.
RA0 to RA8
→DO0 to DO31 (HH)
(LH)
0.71
0.65
1.68
1.62
4.17
4.13
4.85
4.81
9.82
9.82
10.02
10.02
DO31
TOUT
24.7
26.0
(HL)
(LL)
RSB
(LH)
1.14
1.25
1.70
1.82
2.61
2.77
→DO0 to DO31 (HL)
H50
H51
H52
H53
H54
H55
RA8
WEB
WSB
RSB
TIN
TEB
2.4
2.4
2.4
2.4
2.4
5.0
DI0 to DI31
→DO0 to DO31 (LL)
(HH)
2.35
2.37
4.39
4.46
7.72
7.86
Equivalent Cells
80657
Power (mW/MHz)
Rev.
1
174
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
10.02
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
10.02
2.65
2.63
2.77
1.25
1.14
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
10.98
6.22
6.22
4.35
0.41
3.22
0.96
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
11.23
Block Library A13071EJ4V0BL00
175
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9KB
64 words × 40 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H40
H41
DI39
WA0
DO39
RA0
N40
H47
H46
WA5
RA5
H52
H53
H54
WEB
WSB
RSB
H55
N41
H56
H57
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
IN → OUT
MIN.
MAX.
H01
:
H40
H41
:
H46
H47
:
H52
H53
H54
H55
H56
H57
DI0
:
DI39
WA0
:
WA5
RA0
:
RA5
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N40
N41
DO0
:
23.7
:
RA0 to RA5
→DO0 to DO39 (HH)
(LH)
1.66
1.64
2.56
2.58
4.02
4.00
4.65
4.66
7.86
7.86
8.06
8.06
DO39
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.76
0.87
1.20
1.27
1.91
1.94
→DO0 to DO39 (HL)
DI0 to DI39
→DO0 to DO39 (LL)
(HH)
1.61
1.70
3.24
3.39
5.90
6.14
Equivalent Cells
Power (mW/MHz)
15994
Rev.
1
176
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
8.06
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
8.06
2.25
1.91
1.94
0.87
0.76
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
8.45
5.57
5.57
2.60
0.28
3.10
0.52
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
9.11
Block Library A13071EJ4V0BL00
177
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9KD
128 words × 40 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H40
H41
DI39
WA0
DO39
RA0
N40
H48
H47
WA6
RA6
H54
H55
H56
WEB
WSB
RSB
H57
N41
H58
H59
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H40
H41
:
H47
H48
:
H54
H55
H56
H57
H58
H59
DI0
:
DI39
WA0
:
WA6
RA0
:
RA6
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
2.5
N01
:
N40
N41
DO0
:
24.7
:
IN → OUT
MIN.
MAX.
RA0 to RA6
→DO0 to DO39 (HH)
(LH)
0.68
0.61
1.67
1.61
3.63
3.59
4.32
4.28
8.44
8.44
8.64
8.64
DO39
TOUT
24.7
26.0
(HL)
(LL)
RSB
(LH)
1.08
1.22
1.63
1.77
2.54
2.67
→DO0 to DO39 (HL)
DI0 to DI39
→DO0 to DO39 (LL)
(HH)
1.81
2.01
3.53
3.84
6.33
6.82
Equivalent Cells
Power (mW/MHz)
31469
Rev.
1
178
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
8.64
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
8.64
2.26
2.55
2.68
1.22
1.08
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
9.03
5.88
5.88
2.77
0.38
3.04
0.78
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
9.88
Block Library A13071EJ4V0BL00
179
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9KF
256 words × 40 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H40
H41
DI39
WA0
DO39
RA0
N40
H49
H48
WA7
RA7
H56
H57
H58
WEB
WSB
RSB
H59
N41
H60
H61
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
X
X
X
1
0
0
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H40
H41
:
H48
H49
:
H56
H57
H58
H59
H60
H61
DI0
:
DI39
WA0
:
WA7
RA0
:
RA7
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
1.0
1.0
2.4
2.5
N01
:
N40
N41
DO0
:
23.7
:
IN → OUT
MIN.
MAX.
RA0 to RA7
→DO0 to DO39 (HH)
(LH)
2.28
2.25
2.99
3.02
4.91
4.89
5.43
5.45
9.21
9.21
9.41
9.41
DO39
TOUT
23.7
26.0
(HL)
(LL)
RSB
(LH)
0.79
0.95
1.24
1.38
1.97
2.09
→DO0 to DO39 (HL)
DI0 to DI39
→DO0 to DO39 (LL)
(HH)
2.14
2.06
4.09
4.00
7.28
7.15
Equivalent Cells
Power (mW/MHz)
50227
Rev.
1
180
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
9.41
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
9.41
2.69
1.97
2.10
0.95
0.79
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
8.95
5.84
5.84
4.13
0.30
3.27
0.96
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
10.46
Block Library A13071EJ4V0BL00
181
HIGH DENSITY DUAL-PORT RAM BLOCK
Block Type
Function
SSI Family
R9KH
512 words × 40 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H40
H41
DI39
WA0
DO39
RA0
N40
H50
H49
WA8
RA8
H58
H59
H60
WEB
WSB
RSB
H61
N41
H62
H63
TIN
TOUT
TEB
Truth Table
TEB
TIN
X
X
X
X
X
X
DIn
X
X
DIn
X
X
WAn WSB WEB
DMn
Hold
Hold
DIn(WAn)
X
RAn
X
X
X
X
RSB
X
X
X
1
0
0
X
DOn
X
X
X
TOUT
X
X
X
X
X
X
1
1
1
1
1
1
0
X
X
1
0
0
X
1
0
X
X
1
0
X
1
0
X
WAn
X
0
X
DMn
DIn(WAn) RAn
RAn
DMn(RAn)
DMn(RAn)
X
DIn
X
WAn
X
CLOCK
X
X
RESULT
Caution WEB or WSB must be high during all address transition.
X
: Irrelevant
WSB : A-port select
WEB : Write enable
RAn : B-port address (Read)
RSB : B-port select
DIn : Input data
WAn : A-port address (Write) DMn : Memory data
DOn : Output data
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
t
(ns)
LD0
TYP.
H01
:
H40
H41
:
H49
H50
:
H58
H59
H60
H61
H62
H63
DI0
:
DI39
WA0
:
WA8
RA0
:
RA8
WEB
WSB
RSB
TIN
TEB
2.4
:
2.4
2.4
:
2.4
2.4
:
2.4
2.4
2.4
2.4
2.4
5.0
N01
:
N40
N41
DO0
:
24.7
:
IN → OUT
MIN.
MAX.
RA0 to RA8
→DO0 to DO39 (HH)
(LH)
0.75
0.68
1.71
1.66
4.21
4.16
4.88
4.85
9.85
9.85
10.05
10.05
DO39
TOUT
24.7
26.0
(HL)
(LL)
RSB
(LH)
1.17
1.29
1.74
1.88
2.67
2.84
→DO0 to DO39 (HL)
DI0 to DI39
→DO0 to DO39 (LL)
(HH)
2.36
2.37
4.40
4.46
7.72
7.86
Equivalent Cells
Power (mW/MHz)
99937
Rev.
1
182
Block Library A13071EJ4V0BL00
HIGH DENSITY DUAL-PORT RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
tRCA
tACA
tOH
tREC
tREL
tRLL
10.05
Address access time
Address output hold time
RSB access time
RSB output hold time
RSB output set time
10.05
2.69
2.71
2.85
1.29
1.17
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
11.01
6.23
6.23
4.36
0.42
3.23
0.98
Cycle time
WSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
11.32
Block Library A13071EJ4V0BL00
183
[MEMO]
184
Block Library A13071EJ4V0BL00
CHAPTER 3
ROM BLOCK
Block Library A13071EJ4V0BL00
185
ROM BLOCK
Block Type
Function
J14DK
128 words × 4 bits ROM
Logic Diagram
H01
H07
AD0
AD6
DO0
DO3
N01
N04
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H07
AD6
2.5
N04
DO3
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.207
0.444
0.207
0.444
1.272
1.541
1.272
1.541
3.164
3.491
3.164
3.491
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD6→DO0 to DO3
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
3.4907
0.2074
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
3.4907
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
1113 (53 × 21)
Equivalent Cells
0.018
186
Block Library A13071EJ4V0BL00
ROM BLOCK
Block Type
Function
J14FK
256 words × 4 bits ROM
Logic Diagram
H01
H08
AD0
AD7
DO0
DO3
N01
N04
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H08
AD7
2.5
N04
DO3
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.314
0.538
0.314
0.538
1.513
1.769
1.513
1.769
3.645
3.959
3.645
3.959
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD7→DO0 to DO3
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
3.9593
0.3135
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
3.9593
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
2035 (55 × 37)
Equivalent Cells
0.036
Block Library A13071EJ4V0BL00
187
ROM BLOCK
Block Type
Function
J14HK
512 words × 4 bits ROM
Logic Diagram
H01
H09
AD0
AD8
DO0
DO3
N01
N04
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H09
AD8
2.5
N04
DO3
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.314
0.538
0.314
0.538
1.551
1.835
1.551
1.835
3.752
4.142
3.752
4.142
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD8→DO0 to DO3
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
4.1422
0.3135
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
4.1422
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
3458 (91 × 38)
Equivalent Cells
0.072
188
Block Library A13071EJ4V0BL00
ROM BLOCK
Block Type
Function
J14MK
1024 words × 4 bits ROM
Logic Diagram
H01
H10
AD0
AD9
DO0
DO3
N01
N04
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H10
AD9
2.5
N04
DO3
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.417
0.636
0.417
0.636
1.828
1.963
1.828
1.963
4.336
4.323
4.336
4.323
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD9→DO0 to DO3
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
4.3363
0.4170
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
4.3363
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
6370 (91 × 70)
Equivalent Cells
0.144
Block Library A13071EJ4V0BL00
189
ROM BLOCK
Block Type
Function
J14SK
2048 words × 4 bits ROM
Logic Diagram
H01
H11
AD0
DO0
DO3
N01
N04
AD10
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H11
AD10
2.5
N04
DO3
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.417
0.638
0.417
0.638
2.198
2.220
2.198
2.220
5.364
5.034
5.364
5.034
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD10→DO0 to DO3
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
5.3642
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
5.3642
tAOH
0.4170
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
12194 (91 × 134)
Equivalent Cells
0.288
190
Block Library A13071EJ4V0BL00
ROM BLOCK
Block Type
Function
J18DK
128 words × 8 bits ROM
Logic Diagram
H01
H07
AD0
AD6
DO0
DO7
N01
N08
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H07
AD6
2.5
N08
DO7
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.207
0.444
0.207
0.444
1.348
1.593
1.348
1.593
3.376
3.636
3.376
3.636
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD6→DO0 to DO7
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
3.6364
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
3.6364
tAOH
0.2074
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
1785 (85 × 21)
Equivalent Cells
0.036
Block Library A13071EJ4V0BL00
191
ROM BLOCK
Block Type
Function
J18FK
256 words × 8 bits ROM
Logic Diagram
H01
H08
AD0
AD7
DO0
DO7
N01
N08
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H08
AD7
2.5
N08
DO7
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.314
0.538
0.314
0.538
1.551
1.835
1.551
1.835
3.752
4.142
3.752
4.142
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD7→DO0 to DO7
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
4.1422
0.3135
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
4.1422
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
3219 (87 × 37)
Equivalent Cells
0.055
192
Block Library A13071EJ4V0BL00
ROM BLOCK
Block Type
Function
J18HK
512 words × 8 bits ROM
Logic Diagram
H01
H09
AD0
AD8
DO0
DO7
N01
N08
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H09
AD8
2.5
N08
DO7
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.314
0.538
0.314
0.538
1.666
1.899
1.666
1.899
4.069
4.321
4.069
4.321
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD8→DO0 to DO7
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
4.3205
0.3135
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
4.3205
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
5890 (155 × 38)
Equivalent Cells
0.110
Block Library A13071EJ4V0BL00
193
ROM BLOCK
Block Type
Function
J18MK
1024 words × 8 bits ROM
Logic Diagram
H01
H10
AD0
AD9
DO0
DO7
N01
N08
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H10
AD9
2.5
N08
DO7
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.417
0.636
0.417
0.636
2.019
2.201
2.019
2.201
4.866
4.981
4.866
4.981
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD9→DO0 to DO7
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
4.9813
0.4170
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
4.9813
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
10850 (155 × 70)
Equivalent Cells
0.068
194
Block Library A13071EJ4V0BL00
ROM BLOCK
Block Type
Function
J18SK
2048 words × 8 bits ROM
Logic Diagram
H01
H11
AD0
DO0
DO7
N01
N08
AD10
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H11
AD10
2.5
N08
DO7
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.417
0.638
0.417
0.638
2.351
2.317
2.351
2.317
5.788
5.303
5.788
5.303
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD10→DO0 to DO7
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
5.7882
0.4170
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
5.7882
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
20770 (155 × 134)
Equivalent Cells
0.136
Block Library A13071EJ4V0BL00
195
ROM BLOCK
Block Type
Function
J1CDK
128 words × 16 bits ROM
Logic Diagram
H01
H07
AD0
AD6
DO0
N01
N16
DO15
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H07
AD6
2.5
N16
DO15
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.207
0.444
0.207
0.444
1.460
1.702
1.460
1.702
3.686
3.938
3.686
3.938
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD6→DO0 to DO15
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
3.9381
0.2074
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
3.9381
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
3129 (149 × 21)
Equivalent Cells
0.072
196
Block Library A13071EJ4V0BL00
ROM BLOCK
Block Type
Function
J1CFK
256 words × 16 bits ROM
Logic Diagram
H01
H08
AD0
AD7
DO0
N01
N16
DO15
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H08
AD7
2.5
N16
DO15
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.314
0.538
0.314
0.538
1.666
1.899
1.666
1.899
4.069
4.321
4.069
4.321
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD07→DO0 to DO15
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
4.3205
0.3135
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
4.3205
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
5587 (151 × 37)
Equivalent Cells
0.110
Block Library A13071EJ4V0BL00
197
ROM BLOCK
Block Type
Function
J1CHK
512 words × 16 bits ROM
Logic Diagram
H01
H09
AD0
AD8
DO0
N01
N16
DO15
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H09
AD8
2.5
N16
DO15
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.314
0.538
0.314
0.538
1.959
2.021
1.959
2.021
4.884
4.659
4.884
4.659
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD8→DO0 to DO15
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
4.8836
0.3135
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
4.8836
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
10754 (283 × 38)
Equivalent Cells
0.220
198
Block Library A13071EJ4V0BL00
ROM BLOCK
Block Type
Function
J1CMK
1024 words × 16 bits ROM
Logic Diagram
H01
H10
AD0
AD9
DO0
N01
N16
DO15
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H10
AD9
2.5
N16
DO15
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.417
0.636
0.417
0.636
2.279
2.329
2.279
2.329
5.590
5.338
5.590
5.338
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD09→DO0 to DO15
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
5.5897
0.4170
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
5.5897
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
19810 (283 × 70)
Equivalent Cells
0.136
Block Library A13071EJ4V0BL00
199
ROM BLOCK
Block Type
Function
J1CSK
2048 words × 16 bits ROM
Logic Diagram
H01
H11
AD0
DO0
N01
N16
AD10
DO15
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H11
AD10
2.5
N16
DO15
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.417
0.638
0.417
0.638
2.558
2.615
2.558
2.615
6.365
6.130
6.365
6.130
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD10→DO0 to DO15
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
6.3649
0.4170
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
6.3649
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
37922 (283 × 134)
Equivalent Cells
0.272
200
Block Library A13071EJ4V0BL00
ROM BLOCK
Block Type
Function
J1HFK
256 words × 32 bits ROM
Logic Diagram
H01
H08
AD0
AD7
DO0
N01
N32
DO31
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H08
AD7
2.5
N32
DO31
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.314
0.538
0.314
0.538
1.959
2.021
1.959
2.021
4.884
4.659
4.884
4.659
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD7→DO0 to DO31
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
4.8836
0.3135
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
4.8836
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
10323 (279 × 37)
Equivalent Cells
0.220
Block Library A13071EJ4V0BL00
201
ROM BLOCK
Block Type
Function
J1HHK
512 words × 32 bits ROM
Logic Diagram
H01
H09
AD0
AD8
DO0
N01
N32
DO31
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H09
AD8
2.5
N32
DO31
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.314
0.538
0.314
0.538
2.343
2.443
2.343
2.443
5.951
5.829
5.951
5.829
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD8→DO0 to DO31
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
5.9505
0.3135
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
5.9505
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
20482 (539 × 38)
Equivalent Cells
0.440
202
Block Library A13071EJ4V0BL00
ROM BLOCK
Block Type
Function
J1HMK
1024 words × 32 bits ROM
Logic Diagram
H01
H10
AD0
AD9
DO0
N01
N32
DO31
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H10
AD9
2.5
N32
DO31
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.417
0.636
0.417
0.636
2.803
2.595
2.803
2.595
7.046
6.076
7.046
6.076
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD9→DO0 to DO31
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
7.0459
0.4170
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
7.0459
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
37730 (539 × 70)
Equivalent Cells
0.272
Block Library A13071EJ4V0BL00
203
ROM BLOCK
Block Type
Function
J1HSK
2048 words × 32 bits ROM
Logic Diagram
H01
H11
AD0
DO0
N01
N32
AD10
DO31
Input
Name Symbol Fan-in
Output
Truth Table
Name Symbol Fan-out
H01
:
AD0
:
2.5
:
N01
:
DO0
:
53
:
ADn
ADn
DOn
DOn
Operation
H11
AD10
2.5
N32
DO31
53
Read
ADn :Read address
DOn :Read data
Switching speed
(ns)
Path
t
t
1
LD0
IN → OUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.417
0.638
0.417
0.638
2.816
2.907
2.816
2.907
7.081
6.940
7.081
6.940
0.541
0.359
0.541
0.359
1.212
1.055
1.212
1.055
1.212
1.055
1.212
1.055
(HH)
AD0 to AD10→DO0 to DO31
(HL)
(LH)
(LL)
Read cycle timingNote
MIN.
Caution This ROM block is under
development in EA-9HD
family.
TYP.
MAX.
7.0812
0.4170
Cycle time
tCYCLE
tACC
Note Values of power consumption
and cycle timing are
Address access time
Address-output hold time
7.0812
tAOH
preliminary values.
Write cycle
Read cycle
Power (mW/MHz)Note
73968 (552 × 134)
Equivalent Cells
0.544
204
Block Library A13071EJ4V0BL00
APPENDIX
BASIC RAM BLOCK
Block Library A13071EJ4V0BL00
205
BASIC RAM BLOCK
Block Type
Function
SSI Family
K147
16 words × 4 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO3
N01
N04
H04
H05
DI3
AD0
H08
AD3
H09
H10
H11
WEB
REB
CSB
Truth Table
DIn ADn CSB WEB REB DOn
Operation
Write
DIn ADn
DIn ADn
0
0
0
1
X
0
0
1
X
1
1
0
0
X
1
0
DIn Write , Read
DOn Read
X
X
X
ADn
X
X
0
0
Hold
Hold
X
: Irrelevant
DOn : Output data
WEB : Write enable
REB : Read enable
DIn : Input data
ADn : Address data
CSB : Chip select
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
AD0 to AD3
→DO0 to DO3
t
(ns)
LD0
TYP.
H01
:
H04
H05
:
DI0
:
DI3
AD0
:
1.0
:
1.0
1.0
:
N01
:
N04
DO0
:
26.0
:
MIN.
MAX.
(LH)
1.597
1.597
1.427
1.427
2.966
2.966
2.658
2.658
5.199
5.199
4.667
4.667
DO3
26.0
(HH)
(HL)
(LL)
H08
H09
H10
H11
AD3
WEB
REB
CSB
1.0
1.0
1.0
1.0
CSB
(LL)
(LH)
(HL)
1.413
1.413
0.444
2.619
2.619
0.810
4.587
4.587
1.408
→DO0 to DO3
REB
→DO0 to DO3
(LH)
(HL)
0.405
0.254
0.696
0.474
1.170
0.832
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
1.260
1.092
2.365
1.995
4.166
3.468
Read cycle
Write cycle
0.014
0.018
Equivalent Cells
Power (mW/MHz)
Rev.
48 x 9 = 432
1
206
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
5.199
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
5.199
1.427
4.587
1.408
0.444
1.413
1.170
0.832
REB output hold time
REB output set time
0.254
0.405
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
3.500
2.400
2.400
0.900
0.200
2.400
0.000
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
2.856
Block Library A13071EJ4V0BL00
207
BASIC RAM BLOCK
Block Type
Function
SSI Family
K149
32 words × 4 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO3
N01
N04
H04
H05
DI3
AD0
H09
AD4
H10
H11
H12
WEB
REB
CSB
Truth Table
DIn ADn CSB WEB REB DOn
Operation
Write
DIn ADn
DIn ADn
0
0
0
1
X
0
0
1
X
1
1
0
0
X
1
0
DIn Write , Read
DOn Read
X
X
X
ADn
X
X
0
0
Hold
Hold
X
: Irrelevant
DOn : Output data
WEB : Write enable
REB : Read enable
DIn : Input data
ADn : Address data
CSB : Chip select
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
H01
:
H04
H05
:
DI0
:
DI3
AD0
:
1.0
:
1.0
1.0
:
N01
:
N04
DO0
:
26.0
:
MIN.
MAX.
AD0 to AD4
→DO0 to DO3
(LH)
1.867
1.867
1.784
1.784
3.482
3.482
3.358
3.358
6.119
6.119
5.925
5.925
DO3
26.0
(HH)
(HL)
(LL)
H09
H10
H11
H12
AD4
WEB
REB
CSB
1.0
1.0
1.0
1.0
CSB
(LL)
(LH)
(HL)
1.691
1.691
0.471
3.165
3.165
0.843
5.570
5.570
1.452
→DO0 to DO3
REB
→DO0 to DO3
(LH)
(HL)
0.416
0.264
0.716
0.489
1.207
0.856
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
1.274
1.174
2.398
2.151
4.233
3.745
Read cycle
Write cycle
0.015
0.019
Equivalent Cells
Power (mW/MHz)
Rev.
50 x 13 = 650
1
208
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
6.119
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
6.119
1.784
5.570
1.452
0.471
1.691
1.207
0.856
REB output hold time
REB output set time
0.264
0.416
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
4.300
3.200
3.200
1.100
0.000
2.400
0.000
3.109
Block Library A13071EJ4V0BL00
209
BASIC RAM BLOCK
Block Type
Function
SSI Family
K14D
128 words × 4 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO3
N01
N04
H04
H05
DI3
AD0
H11
AD6
H12
H13
H14
WEB
REB
CSB
Truth Table
DIn ADn CSB WEB REB DOn
Operation
Write
DIn ADn
DIn ADn
0
0
0
1
X
0
0
1
X
1
1
0
0
X
1
0
DIn Write , Read
DOn Read
X
X
X
ADn
X
X
0
0
Hold
Hold
X
: Irrelevant
DOn : Output data
WEB : Write enable
REB : Read enable
DIn : Input data
ADn : Address data
CSB : Chip select
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
H01
:
H04
H05
:
DI0
:
DI3
AD0
:
1.0
:
1.0
1.0
:
N01
:
N04
DO0
:
26.0
:
MIN.
MAX.
AD0 to AD6
→DO0 to DO3
(LH)
2.102
2.102
2.053
2.053
3.880
3.880
3.784
3.784
6.781
6.781
6.609
6.609
DO3
26.0
(HH)
(HL)
(LL)
H11
H12
H13
H14
AD6
WEB
REB
CSB
1.0
1.0
1.0
1.0
CSB
(LL)
(LH)
(HL)
2.001
2.001
0.503
3.725
3.725
0.910
6.537
6.537
1.574
→DO0 to DO3
REB
→DO0 to DO3
(LH)
(HL)
0.422
0.331
0.774
0.574
1.349
0.970
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
1.380
1.259
2.576
2.325
4.528
4.065
Read cycle
Write cycle
0.018
0.023
Equivalent Cells
Power (mW/MHz)
Rev.
82 x 21 = 1722
1
210
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
6.781
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
6.781
2.053
6.537
1.574
0.503
2.001
1.349
0.970
REB output hold time
REB output set time
0.331
0.422
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
4.300
3.300
3.300
1.000
0.000
2.100
0.000
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
3.967
Block Library A13071EJ4V0BL00
211
BASIC RAM BLOCK
Block Type
Function
SSI Family
K18B
64 words × 8 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO7
N01
N08
H08
H09
DI7
AD0
H14
AD5
H15
H16
H17
WEB
REB
CSB
Truth Table
DIn ADn CSB WEB REB DOn
Operation
Write
DIn ADn
DIn ADn
0
0
0
1
X
0
0
1
X
1
1
0
0
X
1
0
DIn Write , Read
DOn Read
X
X
X
ADn
X
X
0
0
Hold
Hold
X
: Irrelevant
DOn : Output data
WEB : Write enable
REB : Read enable
DIn : Input data
ADn : Address data
CSB : Chip select
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
H01
:
H08
H09
:
DI0
:
DI7
AD0
:
1.0
:
1.0
1.0
:
N01
:
N08
DO0
:
26.0
:
MIN.
MAX.
AD0 to AD5
→DO0 to DO7
(LH)
2.027
2.027
2.006
2.006
3.777
3.777
3.707
3.707
6.632
6.632
6.481
6.481
DO7
26.0
(HH)
(HL)
(LL)
H14
H15
H16
H17
AD5
WEB
REB
CSB
1.0
1.0
1.0
1.0
CSB
(LL)
(LH)
(HL)
1.916
1.916
0.526
3.562
3.562
0.974
6.246
6.246
1.706
→DO0 to DO7
REB
→DO0 to DO7
(LH)
(HL)
0.491
0.369
0.860
0.664
1.461
1.145
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
1.345
1.245
2.534
2.287
4.472
3.987
Read cycle
Write cycle
0.023
0.032
Equivalent Cells
Power (mW/MHz)
Rev.
94 x 21 = 1974
1
212
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
6.632
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
6.632
2.006
6.246
1.706
0.526
1.916
1.461
1.145
REB output hold time
REB output set time
0.369
0.491
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
4.500
3.200
3.200
1.300
0.000
2.000
0.000
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
3.994
Block Library A13071EJ4V0BL00
213
BASIC RAM BLOCK
Block Type
Function
SSI Family
K18F
256 words × 8 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO7
N01
N08
H08
H09
DI7
AD0
H16
AD7
H17
H18
H19
WEB
REB
CSB
Truth Table
DIn ADn CSB WEB REB DOn
Operation
Write
DIn ADn
DIn ADn
0
0
0
1
X
0
0
1
X
1
1
0
0
X
1
0
DIn Write , Read
DOn Read
X
X
X
ADn
X
X
0
0
Hold
Hold
X
: Irrelevant
DOn : Output data
WEB : Write enable
REB : Read enable
DIn : Input data
ADn : Address data
CSB : Chip select
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
AD0 to AD7
→DO0 to DO7
t
(ns)
LD0
TYP.
H01
:
H08
H09
:
DI0
:
DI7
AD0
:
1.0
:
1.0
1.0
:
N01
:
N08
DO0
:
26.0
:
MIN.
MAX.
(LH)
2.323
2.323
2.329
2.329
4.236
4.236
4.282
4.282
7.357
7.357
7.470
7.470
DO7
26.0
(HH)
(HL)
(LL)
H16
H17
H18
H19
AD7
WEB
REB
CSB
1.0
1.0
1.0
1.0
CSB
(LL)
(LH)
(HL)
2.241
2.241
0.591
4.054
4.054
1.096
7.012
7.012
1.920
→DO0 to DO7
REB
→DO0 to DO7
(LH)
(HL)
0.538
0.420
0.968
0.797
1.669
1.413
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
2.267
2.193
4.190
4.045
7.327
7.066
Read cycle
Write cycle
0.055
0.069
Equivalent Cells
Power (mW/MHz)
Rev.
160 x 37 = 5920
1
214
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
7.470
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
7.470
2.006
7.012
1.920
0.591
2.241
1.669
1.413
REB output hold time
REB output set time
0.420
0.538
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
5.000
3.400
3.400
1.600
0.000
3.600
0.000
5.454
Block Library A13071EJ4V0BL00
215
BASIC RAM BLOCK
Block Type
Function
SSI Family
K18M
1024 words × 8 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO7
N01
N08
H08
H09
DI7
AD0
H18
AD9
H19
H20
H21
WEB
REB
CSB
Truth Table
DIn ADn CSB WEB REB DOn
Operation
Write
DIn ADn
DIn ADn
0
0
0
1
X
0
0
1
X
1
1
0
0
X
1
0
DIn Write , Read
DOn Read
X
X
X
ADn
X
X
0
0
Hold
Hold
X
: Irrelevant
DOn : Output data
WEB : Write enable
REB : Read enable
DIn : Input data
ADn : Address data
CSB : Chip select
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
H01
:
H08
H09
:
DI0
:
DI7
AD0
:
1.0
:
1.0
1.0
:
N01
:
N08
DO0
:
26.0
:
MIN.
MAX.
AD0 to AD9
→DO0 to DO7
(LH)
2.914
2.914
3.023
3.023
5.247
5.247
5.586
5.586
9.052
9.052
9.769
9.769
DO7
26.0
(HH)
(HL)
(LL)
H18
H19
H20
H21
AD9
WEB
REB
CSB
1.0
1.0
1.0
1.0
CSB
(LL)
(LH)
(HL)
2.733
2.733
0.755
5.056
5.056
1.393
8.845
8.845
2.434
→DO0 to DO7
REB
→DO0 to DO7
(LH)
(HL)
0.670
0.559
1.169
1.064
1.982
1.887
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
2.830
2.786
5.244
5.127
9.183
8.946
Read cycle
Write cycle
0.068
0.097
Equivalent Cells
Power (mW/MHz)
Rev.
316 x 69 = 21804
1
216
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
9.769
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
9.769
2.006
8.845
2.434
0.755
2.733
1.982
1.887
REB output hold time
REB output set time
0.559
0.670
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
5.600
4.400
4.400
1.200
0.000
4.600
0.000
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.037
Block Library A13071EJ4V0BL00
217
BASIC RAM BLOCK
Block Type
Function
SSI Family
K1AB
64 words × 10 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO9
N01
N10
H10
H11
DI9
AD0
H16
AD5
H17
H18
H19
WEB
REB
CSB
Truth Table
DIn ADn CSB WEB REB DOn
Operation
Write
DIn ADn
DIn ADn
0
0
0
1
X
0
0
1
X
1
1
0
0
X
1
0
DIn Write , Read
DOn Read
X
X
X
ADn
X
X
0
0
Hold
Hold
X
: Irrelevant
DOn : Output data
WEB : Write enable
REB : Read enable
DIn : Input data
ADn : Address data
CSB : Chip select
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
AD0 to AD5
→DO0 to DO9
t
(ns)
LD0
TYP.
H01
:
H10
H11
:
DI0
:
DI9
AD0
:
1.0
:
1.0
1.0
:
N01
:
N10
DO0
:
26.0
:
MIN.
MAX.
(LH)
2.097
2.097
2.027
2.027
3.877
3.877
3.773
3.773
6.782
6.782
6.620
6.620
DO9
26.0
(HH)
(HL)
(LL)
H16
H17
H18
H19
AD5
WEB
REB
CSB
1.0
1.0
1.0
1.0
CSB
(LL)
(LH)
(HL)
1.936
1.936
0.588
3.576
3.576
1.052
6.252
6.252
1.810
→DO0 to DO9
REB
→DO0 to DO9
(LH)
(HL)
0.505
0.399
0.886
0.710
1.508
1.216
DI0 to DI9
→DO0 to DO9
(HH)
(LL)
1.347
1.252
2.529
2.299
4.457
4.008
Read cycle
Write cycle
0.029
0.040
Equivalent Cells
Power (mW/MHz)
Rev.
116 x 21 = 2436
1
218
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
6.782
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
6.782
2.027
6.252
1.810
0.588
1.936
1.508
1.216
REB output hold time
REB output set time
0.399
0.505
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
4.600
3.300
3.300
1.300
0.000
2.000
0.000
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
4.073
Block Library A13071EJ4V0BL00
219
BASIC RAM BLOCK
Block Type
Function
SSI Family
K1AF
256 words × 10 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO9
N01
N10
H10
H11
DI9
AD0
H18
AD7
H19
H20
H21
WEB
REB
CSB
Truth Table
DIn ADn CSB WEB REB DOn
Operation
Write
DIn ADn
DIn ADn
0
0
0
1
X
0
0
1
X
1
1
0
0
X
1
0
DIn Write , Read
DOn Read
X
X
X
ADn
X
X
0
0
Hold
Hold
X
: Irrelevant
DOn : Output data
WEB : Write enable
REB : Read enable
DIn : Input data
ADn : Address data
CSB : Chip select
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
H01
:
H10
H11
:
DI0
:
DI9
AD0
:
1.0
:
1.0
1.0
:
N01
:
N10
DO0
:
26.0
:
MIN.
MAX.
AD0 to AD7
→DO0 to DO9
(LH)
2.353
2.353
2.370
2.370
4.389
4.389
4.370
4.370
7.711
7.711
7.632
7.632
DO9
26.0
(HH)
(HL)
(LL)
H18
H19
H20
H21
AD7
WEB
REB
CSB
1.0
1.0
1.0
1.0
CSB
(LL)
(LH)
(HL)
2.335
2.335
0.669
4.237
4.237
1.203
7.341
7.341
2.075
→DO0 to DO9
REB
→DO0 to DO9
(LH)
(HL)
0.560
0.442
1.021
0.866
1.773
1.557
DI0 to DI9
→DO0 to DO9
(HH)
(LL)
2.268
2.244
4.202
4.095
7.359
7.114
Read cycle
Write cycle
0.067
0.097
Equivalent Cells
Power (mW/MHz)
Rev.
198 x 37 = 7326
1
220
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
7.711
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
7.711
2.027
7.341
2.075
0.669
2.335
1.773
1.557
REB output hold time
REB output set time
0.442
0.560
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
5.000
3.400
3.400
1.600
0.000
3.600
0.000
5.593
Block Library A13071EJ4V0BL00
221
BASIC RAM BLOCK
Block Type
Function
SSI Family
K1AM
1024 words × 10 bits Single-port RAM
Logic Diagram
H01
DI0
DO0
DO9
N01
N10
H10
H11
DI9
AD0
H20
AD9
H21
H22
H23
WEB
REB
CSB
Truth Table
DIn ADn CSB WEB REB DOn
Operation
Write
DIn ADn
DIn ADn
0
0
0
1
X
0
0
1
X
1
1
0
0
X
1
0
DIn Write , Read
DOn Read
X
X
X
ADn
X
X
0
0
Hold
Hold
X
: Irrelevant
DOn : Output data
WEB : Write enable
REB : Read enable
DIn : Input data
ADn : Address data
CSB : Chip select
Caution WEB or CSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
H01
:
H10
H11
:
DI0
:
DI9
AD0
:
1.0
:
1.0
1.0
:
N01
:
N10
DO0
:
26.0
:
MIN.
MAX.
AD0 to AD9
→DO0 to DO9
(LH)
2.975
2.975
3.128
3.128
5.388
5.388
5.783
5.783
9.325
9.325
10.110
10.110
DO9
26.0
(HH)
(HL)
(LL)
H20
H21
H22
H23
AD9
WEB
REB
CSB
1.0
1.0
1.0
1.0
CSB
(LL)
(LH)
(HL)
2.907
2.907
0.838
5.229
5.229
1.533
9.017
9.017
2.669
→DO0 to DO9
REB
→DO0 to DO9
(LH)
(HL)
0.766
0.638
1.313
1.172
2.205
2.042
DI0 to DI9
→DO0 to DO9
(HH)
(LL)
2.831
2.776
5.226
5.150
9.134
9.023
Read cycle
Write cycle
0.082
0.118
Equivalent Cells
Power (mW/MHz)
Rev.
392 x 69 = 27048
1
222
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tCSC
tCSL
tCLL
tREC
tREL
tRLL
MIN.
TYP.
MAX.
Cycle time
10.110
Address access time
Address output hold time
CSB access time
CSB output hold time
CSB output set time
REB access time
10.110
2.027
9.017
2.669
0.838
2.907
2.205
2.042
REB output hold time
REB output set time
0.638
0.766
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
6.000
4.400
4.400
1.400
0.000
4.600
0.000
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.269
Block Library A13071EJ4V0BL00
223
BASIC RAM BLOCK
Block Type
Function
SSI Family
K247
16words × 4 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H04
H05
DI3
DO3
RA0
N04
H09
WA0
H08
WA3
RA3
RSB
H12
H15
H13
H14
WEB
WSB
Truth Table
DIn WAn WSB WEB
DMn
RAn RSB
DOn
X
X
X
X
1
0
0
X
1
0
X
1
0
X
1
0
Hold
Hold
DIn(WAn)
X
DMn
DIn(WAn) RAn
X
X
X
X
RAn
X
X
X
1
0
0
X
X
X
0
DIn WAn
X
X
X
X
DMn(RAn)
DMn(RAn)
DIn WAn
X
: Irrelevant
DIn
: Input data
WAn
: A-port address (Write)
WSB : A-port select
WEB : Write enable
RAn
DOn
DMn
RSB
: Memory data
: B-port select
: B-port address (Read)
: Output data
Caution WEB or WSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
MIN.
MAX.
H01
:
H04
H05
:
DI0
:
DI3
WA0
:
1.0
:
1.0
1.0
:
N01
:
N04
DO0
:
26.0
:
RA0 to RA3
→DO0 to DO3
(LH)
0.980
0.980
0.982
0.982
1.645
1.645
1.796
1.796
2.728
2.728
3.125
3.125
DO3
26.0
(HH)
(HL)
(LL)
H08
H09
:
WA3
RA0
:
1.0
1.0
:
RSB
→DO0 to DO3
(LH)
(HL)
0.275
0.219
0.460
0.369
0.762
0.613
H12
H13
H14
H15
RA3
WEB
WSB
RSB
1.0
1.0
1.0
1.0
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
1.394
1.183
2.338
2.168
3.880
3.776
Read cycle
Write cycle
0.016
0.023
Equivalent Cells
Power (mW/MHz)
Rev.
58 x 11 = 638
1
224
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tREC
tREL
MIN.
TYP.
MAX.
Cycle time
3.125
Address access time
Address output hold time
REB access time
REB output hold time
REB output set time
3.125
0.980
0.762
0.613
0.219
0.275
tRLL
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
4.000
2.200
2.200
1.800
0.000
1.600
0.100
4.562
Block Library A13071EJ4V0BL00
225
BASIC RAM BLOCK
Block Type
Function
SSI Family
K249
32 words × 4 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H04
H05
DI3
DO3
RA0
N04
H10
WA0
H09
WA4
RA4
RSB
H14
H17
H15
H16
WEB
WSB
Truth Table
DIn WAn WSB WEB
DMn
RAn RSB
DOn
X
X
X
X
1
0
0
X
1
0
X
1
0
X
1
0
Hold
Hold
DIn(WAn)
X
DMn
DIn(WAn) RAn
X
X
X
X
RAn
X
X
X
1
0
0
X
X
X
0
DIn WAn
X
X
X
X
DMn(RAn)
DMn(RAn)
DIn WAn
X
: Irrelevant
DIn
: Input data
WAn
: A-port address (Write)
WSB : A-port select
WEB : Write enable
RAn
DOn
DMn
RSB
: Memory data
: B-port select
: B-port address (Read)
: Output data
Caution WEB or WSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
MIN.
MAX.
H01
:
H04
H05
:
DI0
:
DI3
WA0
:
1.0
:
1.0
1.0
:
N01
:
N04
DO0
:
26.0
:
RA0 to RA4
→DO0 to DO3
(LH)
1.051
1.051
1.053
1.053
1.753
1.753
1.985
1.985
2.899
2.899
3.506
3.506
DO3
26.0
(HH)
(HL)
(LL)
H09
H10
:
WA4
RA0
:
1.0
1.0
:
RSB
→DO0 to DO3
(LH)
(HL)
0.281
0.235
0.479
0.411
0.801
0.698
H14
H15
H16
H17
RA4
WEB
WSB
RSB
1.0
1.0
1.0
1.0
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
1.194
1.095
2.050
2.056
3.446
3.624
Read cycle
Write cycle
0.020
0.030
Equivalent Cells
Power (mW/MHz)
Rev.
106 x 11 = 1166
1
226
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tREC
tREL
MIN.
TYP.
MAX.
Cycle time
3.506
Address access time
Address output hold time
REB access time
REB output hold time
REB output set time
3.506
1.051
0.801
0.698
0.235
0.281
tRLL
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
4.600
2.600
2.600
2.000
0.000
2.600
0.000
4.881
Block Library A13071EJ4V0BL00
227
BASIC RAM BLOCK
Block Type
Function
SSI Family
K24D
128 words × 4 bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H04
H05
DI3
DO3
RA0
N04
H12
WA0
H11
WA6
RA6
RSB
H18
H21
H19
H20
WEB
WSB
Truth Table
DIn WAn WSB WEB
DMn
RAn RSB
DOn
X
X
X
X
1
0
0
X
1
0
X
1
0
X
1
0
Hold
Hold
DIn(WAn)
X
DMn
DIn(WAn) RAn
X
X
X
X
RAn
X
X
X
1
0
0
X
X
X
0
DIn WAn
X
X
X
X
DMn(RAn)
DMn(RAn)
DIn WAn
X
: Irrelevant
DIn
: Input data
WAn
: A-port address (Write)
WSB : A-port select
WEB : Write enable
RAn
DOn
DMn
RSB
: Memory data
: B-port select
: B-port address (Read)
: Output data
Caution WEB or WSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
MIN.
MAX.
H01
:
H04
H05
:
DI0
:
DI3
WA0
:
1.0
:
1.0
1.0
:
N01
:
N04
DO0
:
26.0
:
RA0 to RA6
→DO0 to DO3
(LH)
1.287
1.287
1.301
1.301
2.197
2.197
2.432
2.432
3.680
3.680
4.277
4.277
DO3
26.0
(HH)
(HL)
(LL)
H11
H12
:
WA6
RA0
:
1.0
1.0
:
RSB
→DO0 to DO3
(LH)
(HL)
0.283
0.315
0.505
0.485
0.866
0.764
H18
H19
H20
H21
RA6
WEB
WSB
RSB
1.0
1.0
1.0
1.0
DI0 to DI3
→DO0 to DO3
(HH)
(LL)
1.717
1.541
2.913
2.814
4.864
4.892
Read cycle
Write cycle
0.028
0.040
Equivalent Cells
Power (mW/MHz)
Rev.
208 x 18 = 3744
1
228
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tREC
tREL
MIN.
TYP.
MAX.
Cycle time
4.277
Address access time
Address output hold time
REB access time
REB output hold time
REB output set time
4.277
1.287
0.866
0.764
0.315
0.283
tRLL
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
5.400
2.800
2.800
2.600
0.000
2.700
0.000
5.463
Block Library A13071EJ4V0BL00
229
BASIC RAM BLOCK
Block Type
Function
SSI Family
K28B
64 words × 8bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H08
H09
DI7
DO7
RA0
N08
H15
WA0
H14
WA5
RA5
RSB
H20
H23
H21
H22
WEB
WSB
Truth Table
DIn WAn WSB WEB
DMn
RAn RSB
DOn
X
X
X
X
1
0
0
X
1
0
X
1
0
X
1
0
Hold
Hold
DIn(WAn)
X
DMn
DIn(WAn) RAn
X
X
X
X
RAn
X
X
X
1
0
0
X
X
X
0
DIn WAn
X
X
X
X
DMn(RAn)
DMn(RAn)
DIn WAn
X
: Irrelevant
DIn
: Input data
WAn
: A-port address (Write)
WSB : A-port select
WEB : Write enable
RAn
DOn
DMn
RSB
: Memory data
: B-port select
: B-port address (Read)
: Output data
Caution WEB or WSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
MIN.
MAX.
H01
:
H08
H09
:
DI0
:
DI7
WA0
:
1.0
:
1.0
1.0
:
N01
:
N08
DO0
:
26.0
:
RA0 to RA5
→DO0 to DO7
(LH)
1.278
1.278
1.233
1.233
2.156
2.156
2.366
2.366
3.589
3.589
4.213
4.213
DO7
26.0
(HH)
(HL)
(LL)
H14
H15
:
WA5
RA0
:
1.0
1.0
:
RSB
→DO0 to DO7
(LH)
(HL)
0.370
0.324
0.603
0.552
0.983
0.925
H20
H21
H22
H23
RA5
WEB
WSB
RSB
1.0
1.0
1.0
1.0
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
1.695
1.498
2.825
2.743
4.668
4.774
Read cycle
Write cycle
0.041
0.054
Equivalent Cells
Power (mW/MHz)
Rev.
208 x 15 = 3120
1
230
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tREC
tREL
MIN.
TYP.
MAX.
Cycle time
4.213
Address access time
Address output hold time
REB access time
REB output hold time
REB output set time
4.213
1.233
0.983
0.925
0.324
0.370
tRLL
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
5.500
2.800
2.800
2.700
0.000
2.400
0.000
5.450
Block Library A13071EJ4V0BL00
231
BASIC RAM BLOCK
Block Type
Function
SSI Family
K28F
256 words × 8bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H08
H09
DI7
DO7
RA0
N08
H17
WA0
H16
WA7
RA7
RSB
H24
H27
H25
H26
WEB
WSB
Truth Table
DIn WAn WSB WEB
DMn
RAn RSB
DOn
X
X
X
X
1
0
0
X
1
0
X
1
0
X
1
0
Hold
Hold
DIn(WAn)
X
DMn
DIn(WAn) RAn
X
X
X
X
RAn
X
X
X
1
0
0
X
X
X
0
DIn WAn
X
X
X
X
DMn(RAn)
DMn(RAn)
DIn WAn
X
: Irrelevant
DIn
: Input data
WAn
: A-port address (Write)
WSB : A-port select
WEB : Write enable
RAn
DOn
DMn
RSB
: Memory data
: B-port select
: B-port address (Read)
: Output data
Caution WEB or WSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
MIN.
MAX.
H01
:
H08
H09
:
DI0
:
DI7
WA0
:
1.0
:
1.0
1.0
:
N01
:
N08
DO0
:
26.0
:
RA0 to RA7
→DO0 to DO7
(LH)
1.774
1.774
1.880
1.880
3.014
3.014
3.400
3.400
5.036
5.036
5.879
5.879
DO7
26.0
(HH)
(HL)
(LL)
H16
H17
:
WA7
RA0
:
1.0
1.0
:
RSB
→DO0 to DO7
(LH)
(HL)
0.392
0.416
0.687
0.678
1.169
1.105
H24
H25
H26
H27
RA7
WEB
WSB
RSB
1.0
1.0
1.0
1.0
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
1.801
1.609
3.060
2.960
5.114
5.163
Read cycle
Write cycle
0.091
0.124
Equivalent Cells
Power (mW/MHz)
Rev.
400 x25 = 10000
1
232
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tREC
tREL
MIN.
TYP.
MAX.
Cycle time
5.879
Address access time
Address output hold time
REB access time
REB output hold time
REB output set time
5.879
1.774
1.169
1.105
0.416
0.392
tRLL
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.000
3.400
3.400
2.600
0.000
2.200
0.000
6.644
Block Library A13071EJ4V0BL00
233
BASIC RAM BLOCK
Block Type
Function
SSI Family
K28M
1024 words × 8bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H08
H09
DI7
DO7
RA0
N08
H19
WA0
H18
WA9
RA9
RSB
H28
H31
H29
H30
WEB
WSB
Truth Table
DIn WAn WSB WEB
DMn
RAn RSB
DOn
X
X
X
X
1
0
0
X
1
0
X
1
0
X
1
0
Hold
Hold
DIn(WAn)
X
DMn
DIn(WAn) RAn
X
X
X
X
RAn
X
X
X
1
0
0
X
X
X
0
DIn WAn
X
X
X
X
DMn(RAn)
DMn(RAn)
DIn WAn
X
: Irrelevant
DIn
: Input data
WAn
: A-port address (Write)
WSB : A-port select
WEB : Write enable
RAn
DOn
DMn
RSB
: Memory data
: B-port select
: B-port address (Read)
: Output data
Caution WEB or WSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
H01
:
H08
H09
:
DI0
:
DI7
WA0
:
1.0
:
1.0
1.0
:
N01
:
N08
DO0
:
26.0
:
MIN.
MAX.
RA0 to RA9
→DO0 to DO7
(LH)
2.481
2.481
2.685
2.685
4.142
4.142
4.941
4.941
6.852
6.852
8.621
8.621
DO7
26.0
(HH)
(HL)
(LL)
H18
H19
:
WA9
RA0
:
1.0
1.0
:
RSB
→DO0 to DO7
(LH)
(HL)
0.479
0.430
0.785
0.724
1.285
1.205
H28
H29
H30
H31
RA9
WEB
WSB
RSB
1.0
1.0
1.0
1.0
DI0 to DI7
→DO0 to DO7
(HH)
(LL)
2.175
1.876
3.676
3.484
6.127
6.107
Read cycle
Write cycle
0.105
0.159
Equivalent Cells
Power (mW/MHz)
Rev.
784 x 47 = 36848
1
234
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tREC
tREL
MIN.
TYP.
MAX.
Cycle time
8.621
Address access time
Address output hold time
REB access time
REB output hold time
REB output set time
8.621
2.480
1.285
1.205
0.430
0.479
tRLL
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
7.400
4.800
4.800
2.600
0.000
2.600
0.000
9.006
Block Library A13071EJ4V0BL00
235
BASIC RAM BLOCK
Block Type
Function
SSI Family
K2AB
64 words × 10bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H10
H11
DI9
DO9
RA0
N10
H17
WA0
H16
WA5
RA5
RSB
H22
H25
H23
H24
WEB
WSB
Truth Table
DIn WAn WSB WEB
DMn
RAn RSB
DOn
X
X
X
X
1
0
0
X
1
0
X
1
0
X
1
0
Hold
Hold
DIn(WAn)
X
DMn
DIn(WAn) RAn
X
X
X
X
RAn
X
X
X
1
0
0
X
X
X
0
DIn WAn
X
X
X
X
DMn(RAn)
DMn(RAn)
DIn WAn
X
: Irrelevant
DIn
: Input data
WAn
: A-port address (Write)
WSB : A-port select
WEB : Write enable
RAn
DOn
DMn
RSB
: Memory data
: B-port select
: B-port address (Read)
: Output data
Caution WEB or WSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
MIN.
MAX.
H01
:
H10
H11
:
DI0
:
DI9
WA0
:
1.0
:
1.0
1.0
:
N01
:
N10
DO0
:
26.0
:
RA0 to RA5
→DO0 to DO9
(LH)
1.296
1.296
1.316
1.316
2.189
2.189
2.495
2.495
3.645
3.645
4.419
4.419
DO9
26.0
(HH)
(HL)
(LL)
H16
H17
:
WA5
RA0
:
1.0
1.0
:
RSB
→DO0 to DO9
(LH)
(HL)
0.380
0.363
0.636
0.613
1.053
1.022
H22
H23
H24
H25
RA5
WEB
WSB
RSB
1.0
1.0
1.0
1.0
DI0 to DI9
→DO0 to DO9
(HH)
(LL)
1.695
1.498
2.825
2.743
4.669
4.773
Read cycle
Write cycle
0.050
0.065
Equivalent Cells
Power (mW/MHz)
Rev.
256x 15 = 3840
1
236
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tREC
tREL
MIN.
TYP.
MAX.
Cycle time
4.419
Address access time
Address output hold time
REB access time
REB output hold time
REB output set time
4.419
1.498
1.053
1.022
0.363
0.380
tRLL
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
5.700
2.900
2.900
2.800
0.000
2.300
0.000
5.841
Block Library A13071EJ4V0BL00
237
BASIC RAM BLOCK
Block Type
Function
SSI Family
K2AF
256words × 10bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H10
H11
DI9
DO9
RA0
N10
H19
WA0
H18
WA7
RA7
RSB
H26
H29
H27
H28
WEB
WSB
Truth Table
DIn WAn WSB WEB
DMn
RAn RSB
DOn
X
X
X
X
1
0
0
X
1
0
X
1
0
X
1
0
Hold
Hold
DIn(WAn)
X
DMn
DIn(WAn) RAn
X
X
X
X
RAn
X
X
X
1
0
0
X
X
X
0
DIn WAn
X
X
X
X
DMn(RAn)
DMn(RAn)
DIn WAn
X
: Irrelevant
DIn
: Input data
WAn
: A-port address (Write)
WSB : A-port select
WEB : Write enable
RAn
DOn
DMn
RSB
: Memory data
: B-port select
: B-port address (Read)
: Output data
Caution WEB or WSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
MIN.
MAX.
H01
:
H10
H11
:
DI0
:
DI9
WA0
:
1.0
:
1.0
1.0
:
N01
:
N10
DO0
:
26.0
:
RA0 to RA7
→DO0 to DO9
(LH)
1.840
1.840
1.985
1.985
3.074
3.074
3.629
3.629
5.087
5.087
6.311
6.311
DO9
26.0
(HH)
(HL)
(LL)
H18
H19
:
WA7
RA0
:
1.0
1.0
:
RSB
→DO0 to DO9
(LH)
(HL)
0.474
0.493
0.790
0.771
1.305
1.226
H26
H27
H28
H29
RA7
WEB
WSB
RSB
1.0
1.0
1.0
1.0
DI0 to DI9
→DO0 to DO9
(HH)
(LL)
1.793
1.614
3.052
2.963
5.105
5.163
Read cycle
Write cycle
0.109
0.147
Equivalent Cells
Power (mW/MHz)
Rev.
496x 25 = 12400
1
238
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tREC
tREL
MIN.
TYP.
MAX.
Cycle time
6.311
Address access time
Address output hold time
REB access time
REB output hold time
REB output set time
6.311
1.839
1.305
1.226
0.493
0.474
tRLL
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
6.800
3.800
3.800
3.000
0.000
2.200
0.000
7.229
Block Library A13071EJ4V0BL00
239
BASIC RAM BLOCK
Block Type
Function
SSI Family
K2AM
1024words × 10bits Dual-port RAM
Logic Diagram
H01
DI0
DO0
N01
H10
H11
DI9
DO9
RA0
N10
H21
WA0
H20
WA9
RA9
RSB
H30
H33
H31
H32
WEB
WSB
Truth Table
DIn WAn WSB WEB
DMn
RAn RSB
DOn
X
X
X
X
1
0
0
X
1
0
X
1
0
X
1
0
Hold
Hold
DIn(WAn)
X
DMn
DIn(WAn) RAn
X
X
X
X
RAn
X
X
X
1
0
0
X
X
X
0
DIn WAn
X
X
X
X
DMn(RAn)
DMn(RAn)
DIn WAn
X
: Irrelevant
DIn
: Input data
WAn
: A-port address (Write)
WSB : A-port select
WEB : Write enable
RAn
DOn
DMn
RSB
: Memory data
: B-port select
: B-port address (Read)
: Output data
Caution WEB or WSB must be high during all address transition.
Input
Output
Switching speed
Name
Symbol
Fan-in
Name
Symbol Fan-out
Path
IN → OUT
t
(ns)
LD0
TYP.
MIN.
MAX.
H01
:
H10
H11
:
DI0
:
DI9
WA0
:
1.0
:
1.0
1.0
:
N01
:
N10
DO0
:
26.0
:
RA0 to RA9
→DO0 to DO9
(LH)
2.589
2.589
2.894
2.894
4.386
4.386
5.337
5.337
7.317
7.317
9.324
9.324
DO9
26.0
(HH)
(HL)
(LL)
H20
H21
:
WA9
RA0
:
1.0
1.0
:
RSB
→DO0 to DO9
(LH)
(HL)
0.484
0.509
0.832
0.833
1.401
1.363
H30
H31
H32
H33
RA9
WEB
WSB
RSB
1.0
1.0
1.0
1.0
DI0 to DI9
→DO0 to DO9
(HH)
(LL)
2.174
1.876
3.678
3.484
6.131
6.107
Read cycle
Write cycle
0.123
0.194
Equivalent Cells
Power (mW/MHz)
Rev.
976x 47 = 45872
1
240
Block Library A13071EJ4V0BL00
BASIC RAM BLOCK
Read Cycle Timing (ns)
Parameters
Symbols
tRCA
tACA
tOH
tREC
tREL
MIN.
TYP.
MAX.
Cycle time
9.324
Address access time
Address output hold time
REB access time
REB output hold time
REB output set time
9.324
2.589
1.401
1.363
0.509
0.484
tRLL
Write Cycle Timing (ns)
Parameters
Symbols
MIN.
TYP.
MAX.
Cycle time
CSB-WEB reset time
Write pulse width
Address setup time
Address hold time
Input data setup time
Input data hold time
WEB access time
tWC
tCWR
tWP
tAS
tAH
tDS
tDH
tWEC
8.400
5.600
5.600
2.800
0.000
3.200
0.100
9.778
Block Library A13071EJ4V0BL00
241
[MEMO]
242
Block Library A13071EJ4V0BL00
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