UC3825L [ETC]
Analog IC ; 模拟IC\n
ETC 
UC1825
UC2825
UC3825
High Speed PWM Controller
FEATURES
DESCRIPTION
•
Compatible with Voltage or Current Mode
Topologies
The UC1825 family of PWM control ICs is optimized for high fre-
quency switched mode power supply applications. Particular care
was given to minimizing propagation delays through the comparators
and logic circuitry while maximizing bandwidth and slew rate of the
error amplifier. This controller is designed for use in either current-
mode or voltage mode systems with the capability for input voltage
feed-forward.
•
Practical Operation Switching Frequencies
to 1MHz
•
•
50ns Propagation Delay to Output
High Current Dual Totem Pole Outputs
(1.5A Peak)
Protection circuitry includes a current limit comparator with a 1V
threshold, a TTL compatible shutdown port, and a soft start pin which
will double as a maximum duty cycle clamp. The logic is fully latched
to provide jitter free operation and prohibit multiple pulses at an out-
put. An under-voltage lockout section with 800mV of hysteresis as-
sures low start up current. During under-voltage lockout, the outputs
are high impedance.
•
•
Wide Bandwidth Error Amplifier
Fully Latched Logic with Double Pulse
Suppression
•
•
•
•
•
Pulse-by-Pulse Current Limiting
Soft Start / Max. Duty Cycle Control
Under-Voltage Lockout with Hysteresis
Low Start Up Current (1.1mA)
These devices feature totem pole outputs designed to source and
sink high peak currents from capacitive loads, such as the gate of a
power MOSFET. The on state is designed as a high level.
±
Trimmed Bandgap Reference (5.1V 1%)
BLOCK DIAGRAM
UDG-92030-2
3/97
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UC1825
UC2825
UC3825
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Pins 13, 15) . . . . . . . . . . . . . . . . . . . . . . . . 30V
Output Current, Source or Sink (Pins 11, 14)
DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A
Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A
Analog Inputs
CONNECTION DIAGRAMS
DIL-16 (Top View)
J Or N Package
(Pins 1, 2, 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
(Pin 8, 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Clock Output Current (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . -5mA
Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA
Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA
Oscillator Charging Current (Pin 5) . . . . . . . . . . . . . . . . . . -5mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300°C
Note 1: All voltages are with respect to GND (Pin 10); all cur-
rents are positive into, negative out of part; pin numbers refer to
DIL-16 package.
Note 3: Consult Unitrode Integrated Circuit Databook for ther-
mal limitations and considerations of package.
PACKAGE PIN FUNCTION
FUNCTION
PIN
PLCC-20 & LCC-20
(Top View)
Q & L Packages
N/C
1
INV
2
SOIC-16 (Top View)
DW Package
NI
3
E/A Out
Clock
N/C
4
5
6
RT
7
CT
8
Ramp
Soft Start
N/C
ILIM/SD
Gnd
Out A
Pwr Gnd
N/C
9
10
11
12
13
14
15
16
17
18
19
20
VC
Out B
VCC
VREF 5.1V
Unless otherwise stated,these specifications apply for , RT = 3.65k, CT = 1nF, VCC
= 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the UC2825, and
0°C<TA<70°C for the UC3825, TA=TJ.
ELECTRICAL CHARACTERISTICS:
UC1825
UC3825
PARAMETERS
TEST CONDITIONS
UC2825
TYP
MIN
MAX
MIN
TYP
MAX UNITS
Reference Section
Output Voltage
Line Regulation
TJ = 25°C, IO = 1mA
5.05
5.10
2
5.15
20
5.00
5.10
2
5.20
20
V
10V < VCC < 30V
1mA < IO < 10mA
TMIN < TA < TMAX
Line, Load, Temperature
10Hz < f < 10kHz
TJ = 125°C, 1000hrs.
VREF = 0V
mV
mV
Load Regulation
5
20
5
20
Temperature Stability*
Total Output Variation*
Output Noise Voltage*
Long Term Stability*
Short Circuit Current
Oscillator Section
Initial Accuracy*
0.2
0.4
0.2
0.4 mV/°C
5.00
5.20
4.95
5.25
V
50
5
50
5
µV
mV
mA
25
25
-15
-50
-100
-15
-50
-100
TJ = 25°C
360
400
0.2
5
440
2
360
400
0.2
5
440
2
kHz
%
Voltage Stability*
10V < VCC < 30V
TMIN < TA < TMAX
Line, Temperature
Temperature Stability*
Total Variation*
%
340
460
340
460
kHz
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UC1825
UC2825
UC3825
Unless otherwise stated,these specifications apply for , RT = 3.65k, CT
= 1nF, VCC = 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the
UC2825, and 0°C<TA<70°C for the UC3825, TA=TJ.
ELECTRICAL CHARACTERISTICS
(cont.)
UC1825
UC3825
PARAMETERS
TEST CONDITIONS
UC2825
MIN
TYP
MAX
MIN
TYP
MAX UNITS
Oscillator Section (cont.)
Clock Out High
3.9
4.5
2.3
2.8
1.0
1.8
3.9
4.5
2.3
2.8
1.0
1.8
V
Clock Out Low
2.9
3.0
2.9
3.0
V
V
V
V
Ramp Peak*
2.6
0.7
1.6
2.6
0.7
1.6
Ramp Valley*
1.25
2.0
1.25
2.0
Ramp Valley to Peak*
Error Amplifier Section
Input Offset Voltage
Input Bias Current
Input Offset Current
Open Loop Gain
10
3
15
3
mV
µA
µA
dB
0.6
0.1
95
0.6
0.1
95
1
1
1V < VO < 4V
1.5V < VCM < 5.5V
10V < VCC < 30V
VPIN 3 = 1V
60
75
85
1
60
75
85
1
CMRR
95
95
dB
PSRR
110
2.5
-1.3
4.7
0 .5
5.5
12
110
2.5
-1.3
4.7
0.5
5.5
12
dB
Output Sink Current
Output Source Current
Output High Voltage
Output Low Voltage
Unity Gain Bandwidth*
Slew Rate*
mA
mA
V
VPIN 3 = 4V
-0.5
4.0
0
-0.5
4.0
0
IPIN 3 = -0.5mA
IPIN 3 = 1mA
5.0
1.0
5.0
1.0
V
3
3
MHz
V/µs
6
6
PWM Comparator Section
Pin 7 Bias Current
Duty Cycle Range
Pin 3 Zero DC Threshold
Delay to Output*
VPIN 7 = 0V
VPIN 7 = 0V
-1
-5
-1
-5
µA
%
V
0
80
0
85
1.1
1.25
50
1.1
1.25
50
80
20
80
20
ns
Soft-Start Section
Charge Current
VPIN 8 = 0.5V
VPIN 8 = 1V
3
1
9
3
1
9
µA
Discharge Current
mA
Current Limit / Shutdown Section
Pin 9 Bias Current
Current Limit Threshold
Shutdown Threshold
Delay to Output
0 < VPIN 9 < 4V
15
1.1
1.55
80
10
1.1
1.55
80
µA
V
0.9
1.0
1.40
50
0.9
1.0
1.40
50
1.25
1.25
V
ns
Output Section
Output Low Level
IOUT = 20mA
IOUT = 200mA
IOUT = -20mA
IOUT = -200mA
VC = 30V
0.25
1.2
0.40
2.2
0.25
1.2
0.40
2.2
V
V
Output High Level
13.0
12.0
13.5
13.0
100
30
13.0
12.0
13.5
13.0
10
V
V
Collector Leakage
500
60
500
60
µA
ns
Rise/Fall Time*
CL = 1nF
30
Under-Voltage Lockout Section
Start Threshold
8.8
0.4
9.2
0.8
9.6
1.2
8.8
0.4
9.2
0.8
9.6
1.2
V
V
UVLO Hysteresis
Supply Current Section
Start Up Current
ICC
VCC = 8V
VPIN 1, VPIN 7, VPIN 9 = 0V; VPIN 2 = 1V
1.1
22
2.5
33
1.1
22
2.5
33
mA
mA
* This parameter not 100% tested in production but guaranteed by design.
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UC1825
UC2825
UC3825
Printed Circuit Board Layout Considerations
High speed circuits demand careful attention to layout Schottky diode at the output pin will serve this purpose. 3)
and component placement. To assure proper performance
of the UC1825 follow these rules: 1) Use a ground plane.
2) Damp or clamp parasitic inductive kick energy from the
gate of driven MOSFETs. Do not allow the output pins to
ring below ground. A series gate resistor or a shunt 1 Amp
Bypass VCC, VC, and VREF. Use 0.1µF monolithic ceramic
capacitors with low equivalent series inductance. Allow
less than 1 cm of total lead length for each capacitor be-
tween the bypassed pin and the ground plane. 4) Treat
the timing capacitor, CT, like a bypass capacitor.
Error Amplifier Circuit
Simplified Schematic
Open Loop Frequency Response
Unity Gain Slew Rate
PWM Applications
Conventional (Voltage Mode)
Current-Mode
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UC1825
UC2825
UC3825
Oscillator Circuit
Deadtime vs CT (3k ≤ RT ≤ 100k)
Deadtime vs Frequency
Timing Resistance vs Frequency
160
140
1.0nF
120
100
80
470pF
10k
100k
1M
FREQ (Hz)
Synchronized Operation
Two Units in Close Proximity
Generalized Synchronization
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UC1825
UC2825
UC3825
Forward Technique for Off-Line Voltage Mode Application
Constant Volt-Second Clamp Circuit
The circuit shown here will achieve a constant volt-sec-
ond product clamp over varying input voltages. The
ramp generator components, RT and CR are chosen so
that the ramp at Pin 9 crosses the 1V threshold at the
same time the desired maximum volt-second product
is reached. The delay through the functional nor block
must be such that the ramp capacitor can be com-
pletely discharged during the minimum deadtime.
Output Section
Simplified Schematic
Rise/Fall Time (CL=1nF)
Rise/Fall Time (CL=10nF)
Saturation Curves
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UC1825
UC2825
UC3825
Open Loop Laboratory Test Fixture
UDG-92032-2
This test fixture is useful for exercising many of the As with any wideband circuit, careful grounding and by-
UC1825’s functions and measuring their specifications.
pass procedures should be followed. The use of a
ground plane is highly recommended.
Design Example: 50W, 48V to 5V DC to DC Converter - 1.5MHz Clock Frequency
UDG-92033-3
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
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