TMS664164DGE-8A [ETC]
SDRAM|4X1MX16|CMOS|TSOP|54PIN|PLASTIC ;
| 型号： | TMS664164DGE-8A |
| 厂家： | 
ETC |
| 描述： | SDRAM|4X1MX16|CMOS|TSOP|54PIN|PLASTIC 动态存储器 |
| 文件： | 总56页 (文件大小：956K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
Organization . . .
Pipeline Architecture (Single-Cycle
1048576 x 16 Bits x 4 Banks
2097152 x 8 Bits x 4 Banks
4194304 x 4 Bits x 4 Banks
Architecture)
Single Write/Read Burst
Self-Refresh Capability (Every 16 s)
3.3-V Power Supply (±10% Tolerance)
Low-Noise, Low-Voltage
Transistor-Transistor Logic (LVTTL)
Interface
Four Banks for On-Chip Interleaving for
x8/x16 (Gapless Access) Depending on
Organizations
Power-Down Mode
High Bandwidth – Up to 125-MHz Data
Rates
Compatible With JEDEC Standards
16K RAS-Only Refresh (Total for All Banks)
4K Auto Refresh (Total for All Banks)/64 ms
Burst Length Programmable to 1, 2, 4, 8
Programmable Output Sequence – Serial or
Interleave
Automatic Precharge and Controlled
Precharge
Chip-Select and Clock-Enable for
Enhanced-System Interfacing
Burst Interruptions Supported:
– Read Interruption
– Write Interruption
Cycle-by-Cycle DQ Bus Mask Capability
Only x16 SDRAM Configuration Supports
Upper-/Lower-Byte Masking Control
– Precharge Interruption
Support Clock-Suspend Operation (Hold
Command)
Programmable CAS Latency From Column
Address
Intel PC100 Compliant (-8 and -8A parts)
Performance Ranges:
SYNCHRONOUS
CLOCK CYLE
TIME
ACCESS TIME
CLOCK TO
OUTPUT
REFRESH
INTERVAL
t
t
t
t
t
REF
CK3
CK2
AC3
AC2
’664xx4-8
’664xx4-8A
’664xx4-10
8 ns
8 ns
10 ns
15 ns
15 ns
6 ns
6 ns
6 ns
64 ms
64 ms
64 ms
7.5 ns
7.5 ns
10 ns
7.5 ns
description
The TMS664xx4 series are 67108864-bit synchronous dynamic random-access memory (SDRAM) devices
which are organized as follow:
Four banks of 1 048 576 words with 16 bits per word
Four banks of 2097152 words with 8 bits per word
Four banks of 4194304 words with 4 bits per word
All inputs and outputs of the TMS664xx4 series are compatible with the LVTTL interface.
The SDRAM employs state-of-the-art technology for high-performance, reliability, and low power. All inputs and
outputs are synchronized with the CLK input to simplify system design and to enhance use with high-speed
microprocessors and caches.
The TMS664xx4 SDRAM is available in a 400-mil, 54-pin surface-mount thin small-outline package (TSOP)
(DGE suffix).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
TMS664xx4 (LVTTL)
DGE PACKAGE
(TOP VIEW)
4M x 16
8M x 8
16M x 4
V
V
V
CC
1
2
54
53
V
V
V
CC
CC
SS
SS
SS
ROW
ADDR
COL
ADDR
DQ0
DQ0
NC
NC
DQ7
DQ15
V
V
V
3
4
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
V
V
SSQ
x4
x8
A0–A13
A0–A13
A0–A13
A0–A9
A0–A8
A0–A7
CCQ
DQ1
CCQ
NC
CCQ
NC
SSQ
NC
SSQ
NC
DQ14
DQ13
DQ2
DQ1
DQ0
5
DQ3
DQ6
x16
V
SSQ
DQ3
V
V
6
V
CCQ
NC
V
CCQ
NC
V
CCQ
SSQ
NC
SSQ
NC
7
DQ12
DQ11
A10
Auto Precharge
DQ4
DQ2
NC
8
NC
DQ5
V
CCQ
DQ5
V
CCQ
NC
V
CCQ
NC
9
V
SSQ
NC
V
SSQ
NC
V
SSQ
BANK-SELECT
ADDRESS
BANKS
10
11
12
13
14
15
16
17
18
19
DQ10
DQ9
DQ6
DQ3
DQ1
54-Pin
Plastic
DQ2
DQ4
4
A13–A12
V
SSQ
DQ7
V
V
V
V
CCQ
NC
V
CCQ
DQ8
SSQ
NC
SSQ
NC
CCQ
NC
TSOP–II
V
V
V
(Pitch = 0.8 mm)
V
SS
NC
V
V
SS
CC
CC
NC
CC
NC
SS
NC
DQML
W
NC
DQMU
CLK
CKE
NC
W
W
DQM
CLK
CKE
NC
A11
A9
DQM
CLK
CKE
NC
A11
A9
CAS
RAS
CS
CAS
RAS
CS
CAS
RAS
CS
A13, BS0 A13, BS0 A13, BS0 20
A12, BS1 A12, BS1 A12, BS1 21
A11
A9
A10, AP
A0
A10, AP
A0
A10, AP
A0
22
23
24
25
26
27
A8
A8
A8
A7
A7
A7
A1
A1
A1
A6
A6
A6
A2
A2
A2
A5
A5
A5
A3
A3
A3
A4
A4
A4
V
V
V
V
V
V
SS
CC
CC
CC
SS
SS
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
PIN NOMENCLATURE
A[0:13]
Address Inputs
Four Banks
Column
A0 –A9 Column Addr (x4)
A0 –A8 Column Addr (x8)
A0 –A7 Column Addr (x16)
A10 Auto Precharge
A12 – A13 Bank-Select
Row
A0 – A11 Row Addrs
A12 – A13 Bank-Select
W
Write Enable
RAS
Row-Address Strobe
CAS
CKE
Column-Address Strobe
Clock-Enable
CLK
System Clock
CS
Chip-Select
DQ[0:3]
DQ[0:7]
DQ[0:15]
SDRAM Data Input/Data Output (x4)
SDRAM Data Input/Data Output (x8)
SDRAM Data Input/Data Output (x16)
DQMU/DQML
DQM
NC
Data/Output Mask Enables for x16
Data/Output Mask Enables for x8/x4
No External Connect
V
V
V
V
Power Supply (3.3 V Typical)
Power Supply for Output Drivers (3.3 V Typical)
Ground
CC
CCQ
SS
Ground for Output Drivers
SSQ
functional block diagram (four banks)
Array Bank 0
Array Bank 1
Array Bank 2
Array Bank 3
CLK
AND
CKE
CS
DQ
Buffer
DQ0–DQ15 (x16)
or
(DQM) DQMx
Control
16
8
RAS
CAS
W
DQ0–DQ7 (x8)
or
4
DQ0–DQ3 (x4)
A0–A13
14
Mode Register
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
device numbering conventions (SDRAM family nomenclature)
64
TMS
6
xx
4 –xx
Prefix:
TMS = Commercial / MOS
Product Family:
Synchronous Dynamic Random-Access Memory
6
=
Density, Refresh, Interface:
64 64M 4K Auto-Refresh LVTTL
Organization/Special Architecture:
=
41
81
16
=
=
=
x 4 Pipeline
x 8 Pipeline
x 16 Pipeline
Number of Banks:
4
= Four Banks
Speed:
8 t
8A t
10 t
CK3
=
=
=
8 ns
8 ns
10 ns
CK3
CK3
operation
All inputs to the ’664xx4 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs
(DQ0–DQ3 for x4, DQ0–DQ7 for x8, and DQ0–DQ15 for x16) are also referenced to the rising edge of CLK.
The ’664xx4 has four banks that are accessed independently. A bank must be activated before it can be
accessed (read from or written to). Refresh cycles refresh all banks alternately.
Five basic commands or functions control most operations of the ’664xx4:
Bank activate/row-address entry
Column-address entry/write operation
Column-address entry/read operation
Bank deactivate
Auto-refresh/self-refresh entry
Additionally, operations can be controlled by three methods: using chip select (CS) to select/deselect the
devices, using DQMx to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or
gate) the CLK input. The device contains a mode register that must be programmed for proper operation.
Table 1 through Table 3 show the various operations that are available on the ’664xx4. These truth tables
identify the command and/or operations and their respective mnemonics. Each truth table is followed by a
legend that explains the abbreviated symbols. An access operation refers to any READ (READ-P) or WRT
(WRT-P) command in progress at cycle n. Access operations include the cycle upon which the READ (READ-P)
or WRT (WRT-P) command is entered and all subsequent cycles through the completion of the access burst.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
operation (continued)
Automatic
MRS
Mode
Register
Set
SLFR
SLFR Exit
Self
Refresh
IDLE
CKE↓PDE
REFR
CKE↑
Automatic
Auto
Refresh
Power
Down
ACT
Active
Power
Down
CKE↑
CKE↓
CLK
Row
Active
Suspend
CKE↓(HOLD)
Read
WRT
CKE↓(HOLD)
CLK
Suspend
WRITE
READ
Read P
CKE↑(HOLD Exit)
Read
Write
CKE↑(HOLD Exit)
Read-P
Write- P
Write P
Read-P
Write- P
Automatic
Read P
CKE↑(HOLD Exit)
Precharge
Automatic
CKE↑(HOLD Exit)
CKE↓(HOLD)
CLK
Suspend
CKE↓(HOLD)
Power On
CLK
Suspend
Automatic
Figure 1. State Diagram
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
operation (continued)
†‡
Table 1. Basic Command Truth Table
STATE OF
BANK(S)
COMMAND
Mode register set
CS RAS
CAS
W
A13 A12 A11 A10
A9–A0
MNEMONIC
All Banks =
deac
A9 = V, A8 = 0,
A7 = 0, A6 – A0 = V
L
L
L
L
X
X
X
X
MRS
Bank deactivate (precharge)
Deactivate all banks
X
X
L
L
L
L
H
H
L
L
BS
X
BS
X
X
X
L
X
X
DEAC
DCAB
H
Bank activate/row-address
entry
SB = deac
L
L
H
H
BS
BS
V
V
L
V
ACTV
A0 – A7 = V,
A8 – A9 = X, for x16
Column-address entry/write
operation
SB = actv
L
H
L
L
BS
BS
X
WRT
A0 – A8 = V,
A9 = X, for x8
A0 – A9 = V, for x4
A0 – A7 = V,
A8 – A9 = X, for x16
Column-address entry/write
operation with auto-deactivate
SB = actv
SB = actv
SB = actv
L
L
L
H
H
H
L
L
L
L
H
H
BS
BS
BS
BS
BS
BS
X
X
X
H
L
WRT-P
READ
A0 – A8 = V,
A9 = X, for x8
A0 – A9 = V, for x4
A0 – A7 = V,
A8 – A9 = X, for x16
Column-address entry/read
operation
A0 – A8 = V,
A9 = X, for x8
A0 – A9 = V, for x4
A0 – A7 = V,
A8 – A9 = X, for x16
Column-address entry/read
operation with auto-deactivate
H
READ-P
A0 – A8 = V,
A9 = X, for x8
A0 – A9 = V, for x4
No operation
X
X
L
H
X
H
X
H
X
X
X
X
X
X
X
X
X
X
NOOP
DESL
Control-input inhibit/no
operation
H
X
All banks=
deac
§
Auto refresh
L
L
L
H
X
X
X
X
X
REFR
†
For execution of these commands on cycle n, CKE must satisfy requirements for one of the following:
— CKE (n–1) must be high
— t
from power-down exit (PDE)
from clock-suspend (HOLD) exit
from self-refresh (SLFR) exit.
CESP
— t and n
IS CLE
CESP
DQMx (n) is a don’t care
— t
and t
RC
‡
§
Auto-refresh or self-refresh entry requires that all banks be deactivated or be in an idle state prior to the command entry. An REFR command
turns on four rows (one from each bank; therefore, 4096 REFR commands fully refresh the memory).
Legend:
n
L
=
=
CLK cycle number
Logic low
actv
deac
BS
=
=
=
Activated
Deactivated
Logic:
(A12 = 0, A13 = 0) select bank 0
(A12 = 1, A13 = 0) select bank 1
(A12 = 0, A13 = 1) select bank 2
(A12 = 1, A13 = 1) select bank 3
Select bank by A12 – A13 at cycle n
H
=
Logic high
X
V
=
=
Don’t care (either logic high or logic low)
Valid
SB
=
6
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TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
operation (continued)
†
Table 2. Clock-Enable (CKE) Command Truth Table
CKE
(n–1)
CKE
(n)
CS
(n)
RAS
(n)
CAS
(n)
W
(n)
COMMAND
STATE OF BANK(S)
MNEMONIC
SLFR
Self-refresh entry
All banks = deac
All banks = no
H
H
L
L
L
L
L
H
X
‡
Power-down entry at n + 1
X
X
X
PDE
§
access operation
L
L
H
H
L
H
X
H
X
H
X
—
—
All banks =
self-refresh
Self-refresh exit
H
All banks =
power down
¶
Power-down exit
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
—
HOLD
—
All banks = access
CLK suspend at n+1
§
operation
All banks = access
CLK suspend exit at n+1
H
§
operation
†
‡
§
For execution of these commands, A0–A13 (n) and DQMx (n) are don’t care entries.
On cycle n, the device executes the respective command (listed in Table 1). On cycle (n+1), the device enters the power-down mode.
A bank is no longer in an access operation one cycle after the last data-out cycle of a READ (READ-P) operation, and two cycles after the last
data-incycle of a WRT (WRT-P) operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the lastdata-in
cycle of a WRT (WRT-P) operation.
¶
If setup time from CKE high to the next CLK high satisfies t
, the device executes the respective command (listed in Table 1). Otherwise,
CESP
either the DESL or NOOP command must be applied before any other command.
Legend:
n
L
H
X
=
=
=
=
=
CLK cycle number
Logic low
Logic high
Don’t care (either logic high or logic low)
Deactivated
deac
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
operation (continued)
†‡
Table 3. Data/Output Mask Enable (DQM) Command Truth Table
D0–D3 (x4)
D0–D7 (x8)
D0–D15 (x16)
(n)
Q0–Q3 (x4)
Q0–Q7 (x8)
Q0–Q15 (x16)
(n+2)
DQM
(DQML/DQMU)
(n)
§
COMMAND
STATE OF BANK(S)
MNEMONIC
—
—
Any bank = deac
X
X
N/A
Hi-Z
—
—
Any bank = actv
(no access operation)
N/A
Hi-Z
¶
Data-in enable
Data-in mask
Any bank = write
Any bank = write
Any bank = read
Any bank = read
L
H
L
V
N/A
N/A
V
ENBL
MASK
ENBL
MASK
M
Data-out enable
Data-out mask
N/A
N/A
H
Hi-Z
†
For execution of these commands on cycle n, one of the following must be true:
— CKE (n–1) must be high
— t
— n
from power-down exit (PDE)
from clock-suspend (HOLD) exit
CESP
CLE
— t
and t
from self-refresh (SLFR) exit
CESP
RC
‡
§
CS (n), RAS (n), CAS (n), W (n), and A0–A13 (n) are don’t care entries.
DQM is used for x4/x8 (no byte control). DQM (n) operations correspond to D0–D7 and Q0–Q7 events. DQML/DQMU are used for x16 (for
byte-control). DQML (n) operations correspond to D0–D7 and Q0–Q7 events, while DQMU (n) operations correspond to D8–D15 and Q8–Q15
events.
A bank is no longer in an access operation one cycle after the last data-out cycle of a READ (READ-P) operation, and two cycles after the last
data-incycle of a WRT (WRT-P) operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the lastdata-in
cycle of a WRT (WRT-P) operation.
¶
Legend:
n
L
=
CLK cycle number
Logic low
actv
deac
write
read
=
=
=
=
Activated
=
=
=
=
=
=
=
Deactivated
H
Logic high
Activated and accepting data in on cycle n
Activated and delivering data out on cycle n + 2
X
Don’t care (either logic high or logic low)
Valid
V
M
Masked input data
Not applicable
N/A
Hi-Z
High impedance
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
burst sequence
All data for the ’664xx4 is written or read in a burst fashion, that is, a single starting address is entered into the
device and then the ’664xx4 internally accesses a sequence of locations based on that starting address. Some
of the subsequent accesses after the first one can be at preceding, as well as succeeding, column addresses
depending on the starting address entered. This sequence can be programmed to follow either a serial burst
or an interleave burst (see Table 4 through Table 6). The length of the burst sequence can be user-programmed
to be 1, 2, 4, or 8. After a read burst is completed (as determined by the programmed burst length), the outputs
are in the high-impedance state until the next read access is initiated.
Table 4. 2-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A0
DECIMAL
BINARY
START
2ND
START
2ND
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
Serial
Interleave
Table 5. 4-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A1–A0
DECIMAL BINARY
START
2ND
3RD
2
4TH
3
START
00
2ND
3RD
10
11
4TH
11
0
1
2
3
0
1
2
3
1
2
3
0
1
0
3
2
01
10
11
00
01
00
11
10
3
0
01
00
01
10
11
Serial
0
1
10
00
01
10
11
1
2
11
2
3
00
3
2
01
10
01
00
Interleave
0
1
10
00
01
1
0
11
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
burst sequence (continued)
Table 6. 8-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A2–A0
DECIMAL
BINARY
START 2ND 3RD 4TH 5TH 6TH 7TH 8TH START 2ND 3RD 4TH 5TH 6TH 7TH 8TH
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
001
010
011
100
101
110
111
000
001
000
011
010
101
100
111
110
010 011 100 101 110 111
011 100 101 110 111 000
100 101 110 111 000 001
101 110 111 000 001 010
Serial
110
111
111 000 001 010 011
000 001 010 011 100
000 001 010 011 100 101
001 010 011 100 101 110
010 011 100 101 110 111
011 010 101 100 111 110
000 001 110 111 100 101
001 000 111 110 101 100
Interleave
110
111
111 000 001 010 011
110 001 000 011 010
100 101 010 011 000 001
101 100 011 010 001 000
latency
The beginning data-output cycle of a read burst can be programmed to occur two or three CLK cycles after the
READ command (see Figure 2 on how to set the mode register.) This feature allows adjustment of the ’664xx4
to operate in accordance with the system’s capability to latch the data output from the ’664xx4. The delay
between the READ command and the beginning of the output burst is known as CAS latency (also known as
read latency). After the initial output cycle begins, the data burst occurs at the CLK frequency without any
intervening gaps. Use of minimum CAS latencies is restricted, based on the particular maximum frequency
rating of the ’664xx4. Once the mode register has been set (see the section on setting the mode register),
subsequent changes to the CAS latency are prohibited.
There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same
rising edge of CLK as the WRT command. The write latency is fixed and is not determined by the mode-register
contents.
four-bank operation
The ’664xx4 contains four independent banks that can be accessed individually or in an interleaved fashion.
Eachbank must be activated with a row address before it can be accessed. Each bank then must be deactivated
before it can be activated again with a new row address. The bank-activate/row-address-entry command
(ACTV) is entered by holding RAS low, CAS high, W high, and A12–A13 valid on the rising edge of CLK. A bank
can be deactivated either automatically during a READ (READ-P) or a WRT (WRT-P) command, or by using
thebank-deactivate(DEAC)command. AllbankscanbedeactivatedatoncebyusingtheDCABcommand(see
Table 1 for a description of the bank-deactivation, and Figure 25 and Figure 26 for examples of the operation).
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four-bank row-access operation
One of the features of the four-bank operation is access to information on random rows at a higher rate of
operation than is possible with a standard DRAM. This is accomplished by activating one of the banks with a
row address and, while the data stream is being accessed to/from that bank, activating one of the other banks
with other row addresses. When the data stream to/from the first activated bank is complete, the data stream
to/from the second activated bank can begin without interruption. After the second bank is activated, the first
bank can be deactivated to allow the entry of a new row address for the next round of accesses or the entry of
new row addresses for other banks which currently are deactivated. In this manner, operation can continue in
an interleaved fashion. Figure 29A is an example of four-bank, row-interleaving, read bursts with automatic
deactivate with a CAS latency of 3 and a burst length of 8. Figure 29B is an example of four-bank,
row-interleaving, read bursts with automatic deactivate with a CAS latency of 3 and a burst length of 4.
four-bank column-access operation
The availability of four banks allows the access of data from random starting columns between banks at a higher
rate of operation. After activating each bank with a row address (ACTV command), A12–A13 for the four-bank
column-access operation can be used to alternate READ or WRT commands between the banks to provide
gapless accesses at the CLK frequency, provided all specified timing requirements are met. Figure 30 is an
example of four-bank, column-interleaving, read bursts with a CAS latency of 3 and a burst length of 2.
bank deactivation (precharge)
All banks can be deactivated simultaneously (placed in precharge) by using the DCAB command. A single bank
can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB
command except that A10 must be low and A12–A13 select the bank to be precharged (see Table 1; Figure 27
and Figure 31 provide examples). A bank can also be deactivated automatically by using A10 during a READ
or WRT command. If A10 is held high during the entry of a READ or WRT command, the accessed bank,
selected by A12–A13, is automatically deactivated upon completion of the access burst. If A10 is held low
during READ- or WRT-command entry, that bank remains active following the burst. The READ and WRT
commands with automatic deactivation are denoted as READ-P and WRT-P. See Figure 29A and Figure 29B
for examples.
chip-select
CS (chip-select) can be used to select or deselect the ’664xx4 for command entries, which might be required
for multiple-memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device
does not respond to RAS, CAS, or W until the device is selected again by holding CS low on the rising edge
of CLK. Any other valid command can be entered simultaneously on the same rising CLK edge of the select
operation. The device can be selected/deselected on a cycle-by-cycle basis (see Table 1 and Table 2). Using
CS does not affect an access burst that is in progress; the DESL command can restrict only RAS, CAS, and
W inputs to the ’664xx4.
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data/output mask
Masking of individual data cycles within a burst sequence can be accomplished by using the MASK command
(see Table 3). If DQM (or DQML/DQMU of x16) is held high on the rising edge of CLK during a write burst, the
incident data word (referenced to the same rising edge of CLK) on DQ0–DQ7 [or (DQ0–DQ7)/(DQ8–DQ15)
of x16] is ignored. If DQM (or DQML/DQMU of x16) is held high on the rising edge of CLK for a read burst,
DQ0–DQ7 [or (DQ0–DQ7)/(DQ8–DQ15) of x16], referenced to the second rising edge of CLK, are in the
high-impedance state. The application of DQM (DQML/DQMU) to data-output cycles (READ burst) involves a
latencyoftwoCLKcycles, buttheapplicationofDQMtodata-incycles(WRITEburst)hasnolatency. TheMASK
command (or itsopposite, theENBLcommand)isperformedonacycle-by-cyclebasis, allowingtheusertogate
any individual data cycle or cycles within either a read-burst or a write-burst sequence. Figure 14, Figure 38 and
Figure 39 show examples of data/output masking.
CLK-suspend/power-down mode
For normal device operation, CKE should be held high to enable CLK. If CKE goes low during the execution
of a READ (READ-P) or WRT (WRT-P) operation, the state of the DQ bus occurring at the immediate next rising
edge of CLK is frozen at its current state and no further inputs are accepted until CKE is returned high. This is
known as a CLK-suspend operation and its execution is denoted as a HOLD command. The device resumes
operation from the point at which it was placed in suspension, beginning with the second rising edge of CLK
after CKE is returned high. See Figure 42 and Figure 43 for examples.
If CKE is brought low when no READ (READ-P) or WRT (WRT-P) command is in progress, the device enters
power-down mode. If all banks are deactivated when power-down mode is entered, power consumption is
reduced to the minimum. Power-down mode can be used during row-active or auto-refresh periods to reduce
input-buffer power. After power-down mode has been entered, no further inputs are accepted until CKE returns
high. To ensure that data in the device remains valid during the power-down mode, the self-refresh command
(SLRF) must be executed concurrently with the power-down entry (PDE) command. When exiting power-down
mode, new commands can be entered on the first CLK edge after CKE returns high, provided that the setup
time (t
) is satisfied. Table 2 shows the command configuration for a CLK-suspend/power-down operation;
CESP
Figure 18 and Figure 19 show examples of the procedure.
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setting the mode register
The ’664xx4 contains a mode register that must be user-programmed with the CAS latency, the burst type, and
the burst length. This is accomplished by executing an MRS command with the information entered on address
lines A0–A9. A logic 0 must be entered on A7 and A8, but A10–A13 are “don’t care” entries for the ’664xx4.
When A9 = 1, the write burst length is always 1. When A9 = 0, the write burst length is defined by A2–A0.
Figure 2 shows the valid combinations for a successful MRS command. Only valid addresses allow the mode
register to be changed. If the addresses are not valid, the previous contents of the mode register remain
unaffected. The MRS command is executed by holding RAS, CAS, and W low and the input-mode word valid
on A0–A9 on the rising edge of CLK (see Table 1). The MRS command can be executed only when all banks
are deactivated and may not be executed while a burst is active. See Figure 24 and Figure 35 for examples.
A13
A12
A11
A10
A9
A8
0
A7
0
A6
A5
A4
A3
A2
A1
A0
Reserved
0 = Serial
1 = Interleave
(burst type)
REGISTER
BITS
REGISTER
BITS
†
†
WRITE
BURST
LENGTH
REGISTER
BIT A9
CAS
LATENCY
BURST LENGTH
‡§
A6
A5
A4
A2
A1
A0
0
0
0
0
0
0
1
1
0
1
0
1
1
2
4
8
0
1
A2–A0
1
0
0
1
1
0
1
2
3
†
‡
§
All other combinations are reserved.
Refer to timing requirements for minimum valid read latencies based on maximum frequency rating.
Once the mode register has been set, subsequent changes to the CAS latency is prohibited.
Figure 2. Mode-Register Programming
refresh
The ’664xx4 must be refreshed at intervals not exceeding t
(see timing requirements) or data cannot be
REF
retained. Refresh is accomplished by performing one of the following:
An ACTV command (RAS-only refresh) to every row in all banks
4096 auto-refresh (REFR) commands
Putting the device in self-refresh mode
Regardless of the method used, refresh must be accomplished before t
example.
has expired. See Figure 34 for an
REF
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auto refresh
Before performing an auto refresh, all banks must be deactivated (placed in precharge). To enter a REFR
command, RAS and CAS must be low and W must be high during the rising edge of CLK (see Table 1). The
refresh address is generated internally such that after 4096 REFR commands, all banks of the ’664xx4 are
refreshed. The external address and bank-select A12–A13 are ignored. The execution of a REFR command
automatically deactivates all banks upon completion of the internal auto-refresh cycle. This allows consecutive
REFR-only commands to be executed, if desired, without any intervening DEAC commands. The REFR
commands do not necessarily have to be consecutive, but all 4096 must be completed before t
expires.
REF
self-refresh mode
To enter self-refresh mode, all banks of the ’664xx4 must be deactivated first and an SLFR command must be
executed (see Table 2). The SLFR command is identical to the REFR command except that CKE is low. For
proper entry of the SLFR command, CKE is brought low for the same rising edge of CLK when RAS and CAS
are low and W is high. CKE must be held low to stay in self-refresh mode. In the self-refresh mode, refreshing
signals are generated internally for all banks with all external signals (except CKE) being ignored. Data can be
retained by the device automatically for an indefinite period when power is maintained (consumption is reduced
to a minimum). To exit self-refresh mode, CKE must be brought high. New commands are issued after t
has
RC
expired. If CLK is made inactive during self-refresh, it must be returned to an active and stable condition before
CKE is brought high to exit self-refresh mode (see Figure 19).
Prior to entering and upon exiting self-refresh mode, 4096 REFR commands are recommended before
continuing with normal device operations. This ensures that the SDRAM is fully refreshed.
interrupted bursts
Areadorwritecanbeinterruptedbeforetheburstsequenceiscompletewithnoadverseeffectstotheoperation.
This is accomplished by entering certain superseding commands as listed in Table 7 and Table 8, provided that
all timing requirements are met. The interruption of READ-P and WRT-P operations is not supported.
Table 7. Read-Burst Interruption
INTERRUPTING COMMAND
EFFECT OR NOTE ON USE DURING READ BURST
Current output cycles continue until the programmed latency from the superseding READ (READ-P)
command is met and new output cycles begin (see Figure 3).
READ, READ-P
The WRT (WRT-P) command immediately supersedes the read burst in progress. To avoid data contention,
WRT, WRT-P
DEAC, DCAB
DQMxmustbehighbeforetheWRT (WRT-P)commandtomaskoutputofthereadburstoncycles(n –1),
CCD
CCD
n
, and (n
+1), assuming there is any output on these cycles (see Figure 4).
CCD
The DQ bus is in the high-impedance state when n
burst, whichever occurs first (see Figure 5 and Figure 22).
cycles are satisfied or upon completion of the read
HZP
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interrupted bursts (continued)
n
CCD
= 2
CLK
Interrupting
READ Command
at Column Address C1
(see Note A)
READ Command
at Column Address C0
(see Note A)
DQ
C0
C0 + 1
C1
C1 + 1
C1 + 2
First Output Cycle for New
READ Command Begins Here
a) INTERRUPTED ON EVEN CYCLES
= 3
n
CCD
CLK
Interrupting
READ Command
at Column Address C1
(see Note A)
READ Command
at Column Address C0
(see Note A)
C0
C0 + 1
C0 + 2
C1
C1 + 1
DQ
First Output Cycle for New
READ Command Begins Here
b) INTERRUPTED ON ODD CYCLES
NOTE A: For this example, assume CAS latency = 2 and burst length > 2.
Figure 3. Read Burst Interrupted by Read Command
n
CCD
+ 1
n
CCD
– 1
n
CCD
= 4
CLK
Interrupting
WRT Command
at Column Address C1
(see Note A)
READ Command
at Column Address C0
(see Note A)
DQ
C0
C1
C1 + 1
C1 + 2
First Input Cycle for New WRT
Command Begins Here
See Note B
DQMx
NOTES: A. For this example, read latency = 2 and burst length > 2.
B. DQMx must be high to mask output of the read burst on cycles (n
–1), (n
CCD
), and (n +1).
CCD
CCD
Figure 4. Read Burst Interrupted by Write Command
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interrupted bursts (continued)
n
CCD
= 2
CLK
n
HZP3
Interrupting
DEAC/DCAB
Command
READ Command
at Column Address C0
(see Note A)
DQ
NOTE A: For this example, assume CAS latency = 3 and burst length > 2.
C0
C0 + 1
Figure 5. Read Burst Interrupted by DEAC Command
Table 8. Write-Burst Interruption
INTERRUPTING COMMAND
EFFECT OR NOTE ON USE DURING WRITE BURST
READ, READ-P
Data that was input on the previous cycle is written and no further data inputs are accepted (see Figure 6).
The new WRT (WRT-P) command and data-in immediately supersede the write burst in progress
(see Figure 7).
WRT, WRT-P
The DEAC/DCAB command immediately supersedes the write burst in progress. DQMx must be used to
DEAC, DCAB
mask the DQ bus such that the write recovery specification (n
interrupt (see Figure 8).
) is not violated by the
WR
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interrupted bursts (continued)
n
CCD
= 2
CLK
WRT Command
(see Note A)
READ Command
(see Note A)
DQ
D
D
a) INTERRUPTED ON EVEN CYCLES
Q
Q
n
CCD
= 1
CLK
WRT
READ
Command
(see Note A)
Command
(see Note A)
DQ
D
Q
Q
Q
b) INTERRUPTED ON ODD CYCLES
NOTE A: For this example, assume CAS latency = 2, burst length > 2.
Figure 6. Write Burst Interrupted by Read Command
n
CCD
= 2
CLK
Interrupting
WRT-P Command
WRT Command
at Column Address C0
(see Note A)
DQ
C0
C0 + 1
C1
C1 + 1
C1 + 2
C1 + 3
NOTE A: For this example, burst length > 2.
Figure 7. Write Burst Interrupted by Write Command
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interrupted bursts (continued)
n
CCD
= 2
CLK
WRT Command
(see Note A)
DEAC or DCAB Command
(see Note A)
DQ
D
D
Ignored
n
WR
DQMx
NOTE A: For the purposes of this example, CAS latency = 2 and burst length > 2.
Figure 8. Write Burst Interrupted by DEAC/DCAB Command
power up
Device initialization should be performed after a power up to the full V
level. After power is established, a
CC
200-µs interval is required (with no inputs other than CLK). After this interval, all banks of the device must be
deactivated. Eight REFR commands must be performed, and the mode register must be set to complete the
device initialization. See Figure 24.
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†
absolute maximum ratings over operating ambient temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range for output drivers, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
CCQ
Voltage range on any input pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range on any output pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V + 0.5 V
CC
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN
3
NOM
3.3
3.3
0
MAX
3.6
UNIT
V
V
V
V
V
V
V
Supply voltage
CC
CCQ
SS
‡
Supply voltage for output drivers
3
3.6
V
Supply voltage
V
Supply voltage for output drivers
High-level input voltage
Low-level input voltage
Operating ambient temperature
0
V
SSQ
IH
2
– 0.3
0
V
+ 0.3
V
CC
0.8
70
V
IL
T
A
°C
‡
V
CCQ
V
0.3 V
CC
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electrical characteristics over recommended ranges of supply voltage and operating ambient
temperature (unless otherwise noted) (see Note 2)
- 8 (x8/x4)
- 8 (x16)
- 8A (x8/x4)
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
= –2 mA
= 2 mA
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
0.4
0.4
0.4
OL
OL
Input current
(leakage)
0 V ≤ V ≤ V
All other pins = 0 V to V
+ 0.3 V,
I
CC
I
I
±10
±10
±10
µA
I
CC
Output current
(leakage)
0 V ≤ V ≤ V
O CCQ
Output disabled
±10
115
125
1
±10
125
135
1
±10
95
µA
mA
mA
mA
O
Burst length = 1,
CAS latency = 2
CAS latency = 3
Operating
current
t
I
t
MIN
= 0 mA
I
CC1
/I
OH OL
125
1
(see Notes 3, 4, and 5)
CKE MAX, t
(see Note 6)
V
= 15 ns
CK
IL
Precharge
I
I
CC2P
standby current
in power-down
mode
CKE and CLK
(see Note 7)
V
MAX, t
= ∞
CK
IL
1
1
1
mA
mA
CC2PS
Precharge
standby current
in
CKE
(see Note 6)
V
MIN, t
= 15 ns
IH
CK
I
40
40
40
CC2N
non-power-down
mode
I
I
I
I
I
t
=
(see Note 7)
MAX, t
5
8
5
8
5
8
mA
mA
mA
mA
mA
CC2NS
CK
CKE
V
= 15 ns
IL
CK
Active standby
current in
power-down
mode
CC3P
(see Notes 3 and 6)
CKE and CLK
(see Notes 3 and 7)
CKE MIN, t
(see Notes 3 and 6)
CKE MIN, CLK
(see Notes 3 and 7)
Page burst, I /I
V
MAX, t
= ∞
IL
CK
8
8
8
CC3PS
CC3N
V
= 15 ns
IH
CK
Active standby
current in
non-power-down
mode
50
15
55
15
50
15
V
V
MAX, t
= ∞
CK
IH
IL
CC3NS
= 0 mA
CAS latency = 2
CAS latency = 3
165
225
165
245
120
165
mA
mA
OH OL
All banks activated,
(see Notes 8, 9, and 10)
I
Burst current
CC4
CAS latency = 2
CAS latency = 3
150
150
150
150
150
150
mA
mA
Auto-refresh
current
t
t
MIN
RC
RC
(see Notes 4 and 7)
I
I
CC5
Self-refresh
current
CKE
V
MAX
1
1
1
mA
CC6
IL
NOTES: 2. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
3. Only one bank is activated.
4.
t
t
MIN
RC
RC
5. Control, DQ, and address inputs change state twice during t
.
RC
6. Control, DQ, and address inputs change state once every 30 ns.
7. Control, DQ, and address inputs do not change state (stable).
8. 4-bank ping-pong, burst length = 4, n
CCD
= 4 cycles, data pattern 0011.
9. Column address and bank address increment every 4 cycles.
10. A t of 10 ns is used to obtain I for CL3 of the -8A speed grade.
CK
CC4
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electrical characteristics over recommended ranges of supply voltage and operating ambient
temperature (unless otherwise noted) (see Note 2) (continued)
– 8A (x16)
– 10 (x8/x4)
– 10 (x16)
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
= –2 mA
= 2 mA
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
0.4
0.4
0.4
OL
OL
Input current
(leakage)
0 V ≤ V ≤ V
All other pins = 0 V to V
+ 0.3 V,
I
CC
I
I
±10
±10
±10
µA
I
CC
Output current
(leakage)
0 V ≤ V ≤ V
O CCQ
Output disabled
±10
105
135
1
±10
95
±10
105
115
1
µA
mA
mA
mA
O
Burst length = 1,
CAS latency = 2
CAS latency = 3
Operating
current
t
I
t
MIN
= 0 mA
I
CC1
/I
OH OL
105
1
(see Notes 3, 4, and 5)
CKE MAX, t
(see Note 6)
V
= 15 ns
CK
IL
Precharge
I
I
CC2P
standby current
in power-down
mode
CKE and CLK
(see Note 7)
V
MAX, t
= ∞
CK
IL
1
1
1
mA
mA
CC2PS
Precharge
standby current
in
CKE
(see Note 6)
V
MIN, t
= 15 ns
IH
CK
I
40
40
40
CC2N
non-power-down
mode
I
I
I
I
I
t
=
(see Note 7)
MAX, t
5
8
5
8
5
8
mA
mA
mA
mA
mA
CC2NS
CK
CKE
V
= 15 ns
IL
CK
Active standby
current in
power-down
mode
CC3P
(see Notes 3 and 6)
CKE and CLK
(see Notes 3 and 7)
CKE MIN, t
(see Notes 3 and 6)
CKE MIN, CLK
(see Notes 3 and 7)
Page burst, I /I
V
MAX, t
= ∞
IL
CK
8
8
8
CC3PS
CC3N
V
= 15 ns
IH
CK
Active standby
current in
non-power-down
mode
55
15
55
15
60
15
V
V
MAX, t
= ∞
CK
IH
IL
CC3NS
= 0 mA
CAS latency = 2
CAS latency = 3
140
165
120
175
140
200
mA
mA
OH OL
All banks activated,
(see Notes 8, 9, and 10)
I
Burst current
CC4
CAS latency = 2
CAS latency = 3
150
150
150
150
150
150
mA
mA
Auto-refresh
current
t
t
MIN
RC
RC
(see Notes 4 and 7)
I
I
CC5
Self-refresh
current
CKE
V
MAX
1
2
2
mA
CC6
IL
NOTES: 2. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
3. Only one bank is activated.
4.
t
t
MIN
RC
RC
5. Control, DQ, and address inputs change state twice during t
.
RC
6. Control, DQ, and address inputs change state once every 30 ns.
7. Control, DQ, and address inputs do not change state (stable).
8. 4-bank ping-pong, burst length = 4, n
CCD
= 4 cycles, data pattern 0011.
9. Column address and bank address increment every 4 cycles.
10. A t of 10 ns is used to obtain I for CL3 of the -8A speed grade.
CK
CC4
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capacitance over recommended ranges of supply voltage and operating ambient temperature
f = 1 MHz (see Note 11)
PARAMETER
MIN
2.5
MAX
4
UNIT
pF
C
C
C
C
Input capacitance, CLK input
i(S)
i(AC)
i(E)
o
Input capacitance, address and control inputs: A0–A13, CS, DQMx, RAS, CAS, W
Input capacitance, CKE input
2.5
5
pF
5
pF
Output capacitance
4
6.5
pF
NOTE 11: V
CC
= 3.3 ± 0.3 V and bias on pins under test is 0 V.
†‡
ac timing requirements
’664xx4-8
’664xx4-8A
’664xx4-10
UNIT
MIN MAX
MIN MAX
MIN MAX
t
t
t
t
Cycle time, CLK
CAS latency = 2
CAS latency = 3
10
8
15
8
15
10
3
ns
ns
ns
ns
CK2
CK3
CH
Cycle time, CLK
Pulse duration, CLK high
Pulse duration, CLK low
3
3
3
3
3
CL
Access time, CLK high to data out
(see Note 12)
t
t
t
CAS latency = 2
CAS latency = 3
CAS latency = 2
CAS latency = 3
6
7.5
7.5
ns
ns
ns
AC2
AC3
OH2
Access time, CLK high to data out
(see Note 12)
6
6
7.5
Hold time, CLK high to data out with 50-pF
load
3
3
3
Hold time, CLK high to data out with 50-pF
load
t
t
t
3
1
8
3
1
8
3
ns
ns
ns
OH3
Delay time, CLK high to DQ in low-impedance state (see Note 13)
2
LZ
Delay time, CLK high to DQ in high-impedance state
(see Note 14)
10
HZ
t
t
t
t
Setup time, address, control, and data input
Hold time, address, control, and data input
2
2
2
ns
ns
ns
ns
IS
1
1
1
IH
Power down/self-refresh exit time (see Note 15)
Delay time, ACTV command to DEAC or DCAB command
8
8
10
CESP
RAS
48 100000
48 100000
50 100000
Delay time, ACTV, REFR, or SLFR command to ACTV, MRS,
REFR, or SLFR command
t
t
t
t
t
68
20
20
16
16
68
20
20
16
16
80
30
30
20
20
ns
ns
ns
ns
ns
RC
Delay time, ACTV command to READ, READ-P, WRT, or
WRT-P command (see Note 16)
RCD
RP
Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or
SLFR command
Delay time, ACTV command in one bank to ACTV command in
the other bank
RRD
RSA
Delay time, MRS command to ACTV, MRS, REFR, or SLFR
command
†
‡
See Parameter Measurement Information for load circuits (see Figure 9).
All references are made to the rising transition of CLK, unless otherwise noted.
NOTES: 12. t
is referenced from the rising transition of CLK that precedes the data-out cycle. For example, the first data-out t
is referenced
AC
AC
from the rising transition of CLK that is CAS latency – one cycle after the READ command. An access time is measured at output
reference level 1.5 V.
13.
14.
t
is measured from the rising transition of CLK that is CAS latency – one cycle after the READ command.
MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
LZ
t
HZ
15. See Figure 18 and Figure 19.
16. For read or write operations with automatic deactivate, t
must be set to satisfy minimum t .
RAS
RCD
22
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†‡
ac timing requirements (continued)
’664xx4-8
’664xx4-8A
’664xx4-10
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR
command
t
t
t
– (CL –1) t
* CK
ns
ns
APR
RP
Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR
command
t
+ 1 t
CK
APW
RP
t
t
Transition time
Refresh interval
1
1
5
1
5
1
1
5
ns
T
64
64
64
ms
REF
Delay time, final data in of WRT operation to DEAC or DCAB
command
n
1
cycle
WR
n
CCD
n
CDD
n
CLE
Delay time, READ or WRT command to an interrupting command
Delay time, CS low or high to input enabled or inhibited
Delay time, CKE high or low to CLK enabled or disabled
1
0
1
1
0
1
1
0
1
cycle
cycle
cycle
0
1
0
1
0
1
Delay time, final data in of WRT command to READ, READ-P, WRT, or
WRT-P command
n
CWL
1
1
1
cycle
n
n
Delay time, ENBL or MASK command to enabled or masked data in
Delay time, ENBL or MASK command to enabled or masked data out
0
2
0
2
0
2
0
2
0
2
0
2
cycle
cycle
DID
DOD
Delay time, DEAC or DCAB command to DQ in
CAS latency = 2
n
2
2
2
cycle
HZP2
high-impedance state
Delay time, DEAC or DCAB command to DQ in
CAS latency = 3
n
n
3
0
3
0
3
0
cycle
cycle
HZP3
high-impedance state
Delay time, WRT command to first data in
0
0
0
WCD
†
‡
See Parameter Measurement Information for load circuits (see Figure 9).
All references are made to the rising transition of CLK, unless otherwise noted.
23
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
general information for ac timing measurements
The ac timing measurements are based on signal rise and fall times equal to 1 ns (t = 1 ns) and a midpoint
T
reference level of 1.5 V (INPUT = 2.8 V, 0 V) for LVTTL. For signal rise and fall times greater than 1 ns, the
reference level should be changed to V MIN and V MAX instead of the midpoint level. All specifications
IH
IL
referring to READ commands are valid for READ-P commands unless otherwise noted. All specifications
referring to WRT commands are also valid for WRT-P commands unless otherwise noted. All specifications
referring to consecutive commands are specified as consecutive commands for the same bank unless
otherwise noted.
Z = 50Ω
Output
Under
Test
C
= 50 pF
L
Figure 9. ac Load Circuit
24
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
t
CK
t
CH
CLK
t
CL
t
T
t
T
t
IS
t
IH
DQ0–DQ15 (x16), DQ0–DQ7 (x8),
DQ0–DQ3 (x4), A0–A13, CS, RAS,
CAS, W, DQMx, CKE
t
T
t
, t
IS CESP
t
IH
DQ0–DQ15 (x16), DQ0–DQ7 (x8),
DQ0–DQ3 (x4), A0–A13, CS, RAS,
CAS, W, DQMx, CKE
t
T
Figure 10. Input-Attribute Parameters
25
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PARAMETER MEASUREMENT INFORMATION
CAS Latency
CLK
t
ACTV
READ
AC
Command
Command
t
HZ
, t
t
LZ
t
OH2 OH3
DQ
Figure 11. Output Parameters
ACTV
ACTV
DEAC, DCAB
t
RAS
READ, WRT
t
RCD
t
DEAC, DCAB
REFR
ACTV, MRS, REFR, SLFR
ACTV, MRS, REFR, SLFR
ACTV, MRS, REFR, SLFR
ACTV, MRS, REFR, SLFR
ACTV (of a different bank)
ACTV, REFR, SLFR, MRS
STOP, READ, WRT, DEAC, DCAB
RP
t
t
t
RC
RC
RC
ACTV
SELF-REFRESH EXIT
ACTV
t
RRD
(see Note A)
MRS
t
RSA
CCD
READ, WRT
DESL
n
n
CDD
Command
Disable
CLK
NOTE A: t
RRD
is specified for command execution in one bank to command execution in another bank.
Figure 12. Command-to-Command Parameters
26
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
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PARAMETER MEASUREMENT INFORMATION
n
HZP3
CLK
DQ
DEAC/DCAB
Command
t
HZ
(For CL = 3)
Final Output of
Burst
n
HZP2
DQ
(For CL = 2)
Final Output of
Burst
NOTE A: For this example, assume CAS latency = 2, 3 and burst length > 1.
Figure 13. Final Data Output to DEAC or DCAB Command for CAS Latency = 2, 3
CAS Latency = 2
(see Note A)
n
WR
n
DOD
(for ENBL)
CLK
n
READ Command
ENBL Command
DEAC/DCAB
Command
DOD
(for MASK)
WRT Command
t
IH
t
IS
DQ
Q
D
Ignored
MASK
Command
MASK
DQMx
Command
NOTE A: For this example, assume CAS latency = 2 and burst length = 2.
Figure 14. DQ Masking
27
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PARAMETER MEASUREMENT INFORMATION
CAS Latency = 2
(see Note A)
t
APR
CLK
READ-P Command
ACTV Command
DQ
Q
Q
NOTE A: For this example, assume CAS latency = 2 and burst length = 2.
Figure 15. Read Automatic-Deactivate (Autoprecharge)
t
APW
CLK
WRT-P Command
ACTV Command
D
DQ
D
NOTE A: For this example, the burst length = 2.
Figure 16. Write Automatic-Deactivate (Autoprecharge)
n
CLE
n
CLE
CLK
DQ
t
IH
Q
Q
Q
Q
(Assume Final Data Output of Burst)
t
IH
t
t
IS
IS
CKE
Figure 17. CLK-Suspend Operation (Assume Burst Length = 4)
28
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SMOS695A – APRIL 1998 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
CLK
CLK Is Don’t Care, But Must Be
Stable Before CKE High
Exit Power-Down
Mode If t Is
Last Data-In
WRT (WRT-P)
Operation
CESP
Satisfied
(New Command)
Last Data-out
READ (READ-P)
Operation
Enter
Power-down
Mode
CKE
t
t
CESP
IH
t
IS
CLK
DESL or NOOP
Command Only If
CLK Is Don’t Care, But Must Be
Stable Before CKE High
Last Data-In
WRT (WRT-P)
Operation
t
IsNotSatisfied
CESP
Last Data-Out
READ (READ-P)
Operation
Exit Power-Down
Mode
(New Command)
Enter
Power-Down
Mode
CKE
t
CESP
t
IH
t
IS
Figure 18. Power-Down Operation
29
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PARAMETER MEASUREMENT INFORMATION
CLK
Exit SLFR If t
CESP
ACTV, MRS,
or REFR
Command
CLK Is Don’t Care, But Must
Be Stable Before CKE High
Is Satisfied
SLFR
Command
DESL or NOOP Only
Until t Is Satisfied
Both Banks
Deactivated
RC
t
IS
CKE
CLK
t
RC
t
IH
t
CESP
Exit SLFR
ACTV, MRS,
or REFR
Command
t
Not
CLK Is Don’t Care, But Must
Be Stable Before CKE High
CESP
Yet Satisfied
SLFR
Command
DESL or NOOP Only
Until t Is Satisfied
Both Banks
Deactivated
RC
t
IS
CKE
t
RC
t
IH
t
CESP
NOTES: A. Assume both banks are deactivated before the execution of SLFR.
B. Before/after self-refresh mode, 4K burst auto-refresh cycles are recommended to ensure that the SDRAM is fully refreshed.
Figure 19. Self-Refresh Entry/Exit
30
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PARAMETER MEASUREMENT INFORMATION
CLK
DEAC/DCAB
Command
READ
Command
(CL = 2)
Final Input of
Write Burst
n
HZP2
(CL = 2) DQ
D
D
Q
Q
Q
Q
Final Input of
Write Burst
READ
Command
(CL = 3)
n
HZP3
(CL = 3) DQ
D
Q
Q
Q
Q
Q
NOTE A: Assume burst length = 8.
Figure 20. Write Burst Followed by DEAC/DCAB-Interrupted Read
n
CWL
n
WR
CLK
WRT
Command
WRT
Command
DEAC/DCAB
Command
D
D
DQ
NOTE A: For this example, assume burst length = 1.
Figure 21. Write Followed by Deactivate
31
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
n
HZP3
CLK
READ Command
DEAC or DCAB Command
t
HZ
Q
Q
Q
DQ
NOTE A: For this example, assume CAS latency = 3, and burst length = 4.
Figure 22. Read Followed by Deactivate
t
APR
CLK
ACTV, MRS, REFR, or SLFR Command
READ-P Command
Final Data Out
Q
DQ
NOTE A: For this example, assume CAS latency = 3, and burst length = 1.
Figure 23. Read With Auto-Deactivate
32
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DCAB
Command
REFR #1
Command
REFR #8
Command
MRS
Command
New Command
Can Start Entering Here
CLK
t
CK
t
RC
200 µs
t
RSA
V
CCQ
CC
V
t
IS
RAS
CAS
W
t
IH
A10
A11–A13
A0–A9
Mode
A9 = V
A7, A8 = V
A0–A6 = V
(see Note A)
Hi–Z
DQ
DQMx
CS
CKE
Time Lapse
NOTE A: Refer to the section titled “Setting the Mode Register”.
Time Lapse
Time Lapse
Figure 24. Power-Up Sequence
TMS664414, TMS664814, TMS664164
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
ACTV_0
READ_0
DEAC_0
CLK
t
RCD
a
c
DQ
DQMx
RAS
CAS
W
b
d
A13
A12
R0
R0
R0
A11
A10
C0
A0–A9
CS
CKE
BURST
TYPE
BANK
ROW
BURST CYCLE
(D/Q)
(0–3)
ADDR
a
b
c
d
†
C0
Q
0
R0
C0 + 1
C0 + 2
C0 + 3
†
Column-address sequence depends on programmed burst type and starting address C0 (see Table 5).
NOTE A: This example illustrates minimum t for the ’664xx4 at 125 MHz.
RCD
Figure 25. Read Burst (CAS latency = 3, burst length = 4)
34
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
ACTV_3
WRT_3
DEAC_3
CLK
t
RCD
n
WR
g
a
c
e
DQ
DQMx
RAS
CAS
W
b
d
f
h
A13
A12
R0
R0
R0
A11
A10
C0
A0–A9
CS
CKE
BURST
TYPE
BANK ROW
(0–3) ADDR
BURST CYCLE
(D/Q)
a
b
c
d
e
f
g
h
†
C0
D
3
R0
C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7
†
Column-address sequence depends on programmed burst type and starting address C0 (see Table 6).
and n for the ’664xx4 at 125 MHz.
NOTE A: This example illustrates minimum t
RCD
WR
Figure 26. Write Burst (burst length = 8)
35
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SMOS695A – APRIL 1998 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
ACTV_1
WRT_1
READ_1
DEAC_1
CLK
t
RCD
a
c
DQ
DQMx
RAS
CAS
W
b
d
A13
A12
R0
R0
R0
A11
A10
C0
C1
A0–A9
CS
CKE
BURST
TYPE
BANK ROW
(0–3) ADDR
BURST CYCLE
(D/Q)
D
a
b
c
d
†
1
1
R0
R0
C0
C0+1
Q
C1
C1+1
†
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 4).
NOTE A: This example illustrates minimum t for the ’664xx4 at 125 MHz.
RCD
Figure 27. Write-Read Burst (CAS latency = 3, burst length = 2)
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ACTV_2
READ_2
WRT-P_2
CLK
DQ
t
RCD
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
DQMx
RAS
CAS
W
A13
A12
R0
R0
R0
A11
A10
C1
C0
A0–A9
CS
CKE
BURST
TYPE
BANK ROW
BURST CYCLE
(D/Q)
Q
(0–3) ADDR
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
†
C0
2
2
R0
R0
C0+1 C0+2
C0+3 C0+4 C0+5 C0+6 C0+7
D
C1
C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7
†
Column-address sequence depends on programmed burst type and starting address C0 (see Table 6).
NOTE A: This example illustrates minimum t for the ’664xx4 at 125 MHz.
RCD
Figure 28. Read-Write Burst With Automatic Deactivate (CAS latency = 3, burst length = 8)
ACTV_0
READ-P_0
ACTV_1
READ-P_1
ACTV_2
READ-P_2
ACTV_3
CLK
DQ
t
t
t
RCD
RCD
RCD
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
DQMx
RAS
CAS
W
A13
A12
R0
R0
R0
R1
R1
R1
R2
R2
R2
R3
R3
R3
A11
A10
C0
C1
C2
A0–A9
CS
CKE
BURST
TYPE
BANK
ROW
BURST CYCLE
(D/Q)
Q
(0–3) ADDR
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
. . .
†
0
1
2
R0
R1
R2
C0
C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7
Q
C1 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7
Q
C2 C2+1 C2+2 . . .
†
Column-address sequence depends on programmed burst type and starting addresses C0, C1, and C2 (see Table 6).
NOTE A: This example illustrates minimum t for the ’664xx4 at 125 MHz.
RCD
Figure 29. [A] Four-Bank Row-Interleaving Burst Length of 8 With Automatic Deactivate (CAS latency = 3, burst length = 8)
READ-P_0
ACTV_1
READ-P_1
ACTV_2
READ-P_2
ACTV_3
READ-P_3
ACTV_0
READ-P_0
ACTV_1
READ-P_1
ACTV_0
CLK
DQ
t
t
t
t
t
t
RCD
RCD
RCD
RCD
RCD
RCD
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
DQMx
RAS
CAS
W
A13
A12
A11
R0
R0
R0
R1
R1
R2
R2
R3
R3
R4
R4
R5
R5
A10
A0–A9
C0 R1
C1 R2
C2 R3
C3 R4
C4 R5
C5
CS
CKE
BURST
TYPE
BANK
ROW
BURST CYCLE
(D/Q)
Q
(0–3) ADDR
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
. . .
†
0
1
2
3
0
R0
R1
R2
R3
R4
C0
C0+1 C0+2 C0+3
Q
C1 C1+1 C1+2 C1+3
Q
C2 C2+1 C2+2 C2+3
Q
C3 C3+1 C3+2 C3+3
Q
C4 C4+1 C4+2 . . .
†
Column-address sequence depends on programmed burst type and starting addresses C0, C1, and C2 (see Table 5).
NOTE A: This example illustrates minimum t for the ’664xx4 at 125 MHz.
RCD
Figure 29. [B] Four-Bank Row-Interleaving Burst Length of 4 With Automatic Deactivate (CAS latency = 3, burst length = 4) (Cont’d)
TMS664414, TMS664814, TMS664164
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
ACTV_0
ACTV_1
ACTV_2
ACTV_3 READ_0
READ_1
READ_2
READ_3
READ_0
CLK
DQ
a
c
e
b
d
f
DQMx
RAS
CAS
W
A13
A12
R0
R0
R0
R1
R1
R1
R2
R2
R2
R3
R3
A11
A10
R3
C0
C1
C2
C3
C4
A0–A9
CS
CKE
BURST
TYPE
BANK
ROW
BURST CYCLE
(D/Q)
Q
(0–3)
ADDR
R0
a
b
c
d
e
f
g
h
. . .
. . .
†
0
1
C0
C0+1
Q
R1
C1
C1+1
Q
2
R2
C2
C2+1
Q
3
R3
C3
C3+1
. . .
. . .
. . .
. . .
. . .
†
Column-address sequence depends on programmed burst type and starting addresses C0, C1, and C2 (see Table 4).
Figure 30. Four-Bank Column-Interleaving Read Bursts (CAS latency = 3, burst length = 2)
40
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PARAMETER MEASUREMENT INFORMATION
READ_0
ACTV_0
ACTV_2
DEAC_0
WRT_2
DEAC_2
CLK
DQ
t
RCD
a
b
c
d
e
f
g
h
DQMx
RAS
CAS
W
A13
A12
R0
R0
R0
R1
R1
R1
A11
A10
A0–A9
C0
C1
CS
CKE
BURST
TYPE
BANK ROW
(0–3) ADDR
BURST CYCLE
(D/Q)
Q
a
b
c
d
e
f
g
h
†
0
2
R0
R1
C0
C0+1 C0+2 C0+3
D
C1
C1+1 C1+2 C1+3
†
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum t for the ’664xx4 at 125 MHz.
RCD
Figure 31. Read-Burst Bank 0, Write-Burst Bank 1 (CAS latency = 3, burst length = 4)
41
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PARAMETER MEASUREMENT INFORMATION
ACTV_3
ACTV_0 WRT-P_3
READ-P_0
CLK
t
RRD
n
CWL
g
a
c
e
DQ
DQMx
RAS
CAS
W
b
d
f
t
RCD
A13
A12
R0
R0
R0
R1
R1
R1
A11
A10
C0
C1
A0–A9
CS
CKE
BURST
TYPE
BANK ROW
(0–3) ADDR
BURST CYCLE
(D/Q)
D
a
b
c
d
e
f
g
h
†
3
0
R0
R1
C0
C0+1 C0+2 C0+3
Q
C1
C1+1 C1+2 C1+3
†
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum n and t for the ’664xx4 at 125 MHz.
t
CWL, RRD,
RCD
Figure 32. Write-Burst Bank 3, Read-Burst Bank 0 With Automatic Deactivate
(CAS latency = 3, burst length = 4)
42
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PARAMETER MEASUREMENT INFORMATION
READ_1
ACTV_1
ACTV_0
WRT_0
e
DCAB
CLK
DQ
g
t
RCD
b
a
c
d
f
h
n
DOD
DQMx
RAS
CAS
W
A13
A12
R0
R0
R0
R1
R1
R1
A11
A10
C0
C1
A0–A9
CS
CKE
BURST
TYPE
BANK ROW
(0–3) ADDR
BURST CYCLE
(D/Q)
Q
a
b
c
d
e
f
g
h
†
1
0
R0
R1
C0
C0+1 C0+2 C0+3
D
C1
C1+1 C1+2 C1+3
†
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum t for the ’664xx4 at 100 MHz.
RCD
Figure 33. Use of DQM for Output and Data-In Cycle Masking (Read-Burst Bank 1, Write-Burst Bank 0,
Deactivate All Banks) (CAS latency = 2, burst length = 4)
43
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REFR
REFR
ACTV_3
READ_3
DEAC_3
REFR
CLK
t
t
RCD
RC
t
RP
t
RC
a
b
c
d
e
f
g
h
DQ
DQMx
RAS
CAS
W
A13
A12
R0
R0
R0
A11
A10
C0
A0–A9
CS
CKE
BURST
TYPE
BANK ROW
(0–3) ADDR
BURST CYCLE
(D/Q)
a
b
c
d
e
f
g
h
†
C0
Q
3
R0
C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7
†
Column-address sequence depends on programmed burst type and starting address C0 (see Table 6).
NOTE A: This example illustrates minimum t , t , and t for the ’664xx4 at 100 MHz.
RC RCD
RP
Figure 34. Refresh Cycles (Refreshes Followed by Read Burst, Followed by Refresh)
(CAS latency = 2, burst length = 8)
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PARAMETER MEASUREMENT INFORMATION
DCAB
MRS
ACTV_0
WRT-P_0
CLK
DQ
t
RCD
t
RSA
a
b
c
d
DQMx
RAS
CAS
W
See Note A
See Note A
See Note A
See Note A
See Note A
A13
A12
R0
R0
R0
A11
A10
C0
A0–A9
CS
CKE
BURST
TYPE
BANK ROW
(0–3) ADDR
BURST CYCLE
(D/Q)
a
b
c
d
†
C0
D
0
R0
C0+1 C0+2 C0+3
†
Column-address sequence depends on programmed burst type and starting address C0 (see Table 5).
NOTES: A. Refer to Figure 2 (for setting mode registers)
B. This example illustrates minimum t and t
for the ’664xx4 at 125 MHz.
RSA
RCD
Figure 35. Mode-Register Programming
(Deactivate All, Mode Program, Write Burst With Automatic Deactivate)
(CAS latency = 3, burst length = 4)
45
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
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PARAMETER MEASUREMENT INFORMATION
ACTV_3 READ-P_3
HOLD
ACTV_0
WRT-P_0
CLK
DQ
n
CLE
t
RCD
a
b
c
d
e
f
g
h
DQMx
RAS
CAS
W
A13
A12
R0
R0
R1
R1
R1
A11
A10
R0
C0
C1
A0–A9
CS
CKE
BURST
TYPE
BANK ROW
(0–3) ADDR
BURST CYCLE
(D/Q)
Q
a
b
c
d
e
f
g
h
†
3
0
R0
R1
C0
C0+1 C0+2 C0+3
†
C1
D
C1+1 C1+2 C1+3
†
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5).
NOTES: A. This example illustrates minimum t and t for the ’664xx4 at 100 MHz.
RCD
APW
B. If entering the PDE command with violation of short t
banks are deactivated (still in power-down mode).
, the device is still entering the power-down mode and then both
APW
Figure 36. Use of CKE for Clock Gating (Hold) and Standby Mode
(Read-Burst Bank 3 With Hold, Write-Burst Bank 0, Standby Mode)
(CAS latency = 2, burst length = 4)
46
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PARAMETER MEASUREMENT INFORMATION
READ_0
ACTV_0
ACTV_1
DEAC_0
WRT_1
DEAC_1
CLK
t
n
RCD
WR
n
HZP3
DQ0–DQ7
e
f
g
h
DQ8–DQ15
a
b
c
d
DQMU
DQML
RAS
CAS
W
A13
A12
R0
R0
R0
R1
R1
R1
A11
A10
C0
C1
A0–A9
CS
CKE
BURST
TYPE
BANK ROW
(0–3) ADDR
BURST CYCLE
(D/Q)
Q
a
b
c
d
e
f
g
h
†
0
1
R0
R1
C0
C0+1 C0+2 C0+3
†
C1
D
C1+1 C1+2 C1+3
†
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum t
125 MHz.
read burst, and a minimum n write burst for the ’664xx4 at
WR
RCD
Figure 37. Read-Burst Bank 0, Write-Burst Bank 1 (With Lower Bytes Masked Out During the READ
Cycles and Upper Bytes Masked Out During the WRITE Cycles) (Only for x16)
(CAS latency = 3, burst length = 4)
47
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
READ_1
ACTV_1
ACTV_0
WRT_0
DCAB
CLK
n
WR
t
RCD
b
a
a
c
c
d
d
f
f
h
h
DQ0–DQ7
DQML
DQ8–DQ15
DQMU
RAS
b
e
g
CAS
W
A13
A12
R0
R0
R0
R1
R1
R1
A11
A10
C0
C1
A0–A9
CS
CKE
BURST
TYPE
BANK ROW
(0–3) ADDR
BURST CYCLE
(D/Q)
Q
a
b
c
d
e
f
g
h
†
1
0
R0
R1
C0
C0+1 C0+2 C0+3
†
C1
D
C1+1 C1+2 C1+3
†
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum t and a minimum n write burst for the ’664xx4 at 100 MHz.
RCD
WR
Figure 38. Use of DQM for Output and Data-In Cycle Masking (Read-Burst Bank 1, Write-Burst Bank 0,
Deactivate All Banks) [Only Masked Out the Lower Bytes (Random Bits)] for x16
(CAS latency = 2, burst length = 4)
48
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PARAMETER MEASUREMENT INFORMATION
ACTV_0
ACTV_2
ACTV_3
ACT1
READ_0 READ_2
READ_3
READ_1
READ_0
CLK
DQ0–DQ7
DQ8–DQ15
DQMU
DQML
RAS
t
RCD
a
c
e
b
d
f
h
t
RRD
Hi-Z
CAS
W
A13
A12
R0
R0
R0
R2
R2
R2
R3
R3
R3
R1
R1
R1
A11
A10
A0–A9
CS
C0
C2
C3
C1
C4
CKE
BURST
TYPE
BANK ROW
(0–3) ADDR
BURST CYCLE
(D/Q)
Q
a
b
c
d
e
f
g
h
†
0
2
3
1
R0
R2
R3
R1
C0
C0+1
Q
C2
C2+1
Q
C3
C3+1
Q
C1
C1+1
†
Column-address sequence depends on programmed burst type and starting addresses C0, C1, C2, and C3 (see Table 4).
NOTE A: This example illustrates minimum t and minimum t for the ’664xx4 at 125 MHz.
RCD
RRD
Figure 39. Four-Bank Column-Interleaving Read Bursts (With Upper Bytes to be Masked) (Only for x16)
(CAS latency = 3, burst length = 2)
49
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ACTV_1
READ_1
WRT-P_1
i
CLK
DQ
t
RCD
a
c
e
g
b
d
f
h
DQMx
RAS
CAS
W
A13
A12
R0
R0
R0
A11
A10
C0
C1
A0–A9
CS
CKE
BURST
TYPE
BANK ROW
(0–3) ADDR
BURST CYCLE
(D/Q)
Q
a
b
c
d
e
f
g
h
i
†
1
1
R0
R0
C0
C0+1 C0+2
C0+3 C0+4 C0+5 C0+6 C0+7
D
C1
†
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 6).
NOTE A: This example illustrates minimum t for the ’664xx4 at 125 MHz.
RCD
Figure 40. Read Burst — Single Write With Automatic Deactivate (CAS latency = 3, burst length = 8)
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PARAMETER MEASUREMENT INFORMATION
ACTV_0
READ-P_0
CLK
DQ
t
RCD
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
DQMx
RAS
CAS
W
A13
A12
R0
R0
R0
A11
A10
C0
A0–A9
CS
CKE
BURST
TYPE
BANK ROW
BURST CYCLE
(D/Q)
(0–3) ADDR
R0
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
†
Q
0
C0
C0+1 C0+2
C0+3 C0+4 C0+5 C0+6 C0+7
†
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 6).
NOTE A: This example illustrates minimum t for the ’664xx4 at 125 MHz.
RCD
Figure 41. Read Bursts With Automatic Deactivate (read latency = 3, burst length = 8) (for x16)
51
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PARAMETER MEASUREMENT INFORMATION
ACTV_1 READ-P_1
HOLD
b
ACTV_0
WRT-P_0
CLK
DQ
t
RCD
a
c
d
e
f
g
h
DQMx
RAS
CAS
W
See Note A
A13
A12
R0
R0
R0
R0
R1
R1
R1
R1
A11
A10
A0–A9
CS
C0
C1
CKE
BURST BANK
ROW
BURST CYCLE
TYPE
(D/Q)
Q
(0–1)
ADDR
a
b
c
d
e
f
g
h
†
1
0
R0
C0
C0 + 1
C0 + 2
C0 + 3
D
R1
C1
C1 + 1
C1 + 2
C1 + 3
†
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5).
NOTES: A. These rising clocks during output “c” with DQMx = Hi do not mask out the output “d” due to CKE inserted low to suspend
those rising clocks at cycle DQMx = Hi.
B. This example illustrates minimum t
for the ’664xx4 at 100 MHz.
RCD
Figure 42. Use of CKE for Clock Gating (Hold/Suspend) and DQM = Hi Showed No Effect
(CAS latency = 2, burst length = 4, two banks)
52
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PARAMETER MEASUREMENT INFORMATION
ACTV_1
READ-P_1
HOLD
CLK
DQ
t
RCD
a
b
d
c
DQMx
RAS
CAS
See Note A
W
A13
A12
A11
R0
R0
R0
R0
A10
A0–A9
CS
C0
CKE
BURST BANK
ROW
BURST CYCLE
TYPE
(D/Q)
Q
(0–1)
ADDR
a
b
c
d
†
1
R0
C0
C0 + 1
C0 + 2
C0 + 3
†
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5).
NOTES: A. This example illustrates that the DQM mask is also delayed when a HOLD/Suspend is in progress.
B. This example illustrates minimum t for the ’664xx4 at 100 MHz.
RCD
Figure 43. DQMx Mask Delay As the Hold/Suspend In Progress
(CAS latency = 2, burst length = 4)
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A– APRIL 1998 – REVISED JULY 1998
device symbolization
TI
-SS
Speed Code (-8, -8A, -10)
Package Code
TMS664xx4 DGE
W
B
Y
M
LLLL
P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
54
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A– APRIL 1998 – REVISED JULY 1998
MECHANICAL DATA
DGE (R-PDSO-G54)
PLASTIC SMALL-OUTLINE PACKAGE
0.018 (0,45)
0.031 (0,80)
54
0.006 (0,16)
M
0.012 (0,30)
28
0.471 (11,96)
0.455 (11,56)
0.404 (10,26)
0.396 (10,06)
1
27
0.006 (0,15) NOM
0.879 (22,32)
0.871 (22,12)
Gage Plane
0.010 (0,25)
0°–5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.047 (1,20) MAX
0.000 (0,00) MIN
4040070-6/C 12/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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