TMS320VC5502-300_技术文档

TMS320VC5502 Fixed-Point

Digital Signal Processor

Data Manual

Literature Number: SPRS166D

April 2001 – Revised June 2003

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Revision History

REVISION HISTORY

This data sheet revision history highlights the technical changes made to the SPRS166C device-specific data

sheet to make it an SPRS166D revision.

Scope: Added new sections, etc.

PAGE(S)

ADDITIONS/CHANGES/DELETIONS

NO.

Global changes:

–

Replaced “MP/MC” with “MPNMC”

Corrected address of the External Bus Control Register from “0x6C01” to “0x8800”

Replaced “HPI.A[15:0]” with “HPI.HA[15:0]”

Replaced “HPI.D[15:0]” with “HPI.HD[15:0]”

Removed references to TMS320C55x DSP Functional Overview (literature number SPRU312)

Removed references to TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317)

Added references to:

–

TMS320VC5501/5502 DSP Instruction Cache Reference Guide (literature number SPRU630)

TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618)

TMS320VC5501/5502/5509 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU146)

TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)

TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (literature number SPRU613)

TMS320VC5501/5502/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide

(literature number SPRU592)

–

TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide (literature number SPRU621)

TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) Reference Guide

(literature number SPRU597)

4

6

Table 2–1, 176-Terminal GGW Ball Grid Array Ball Assignments:

revised footnote

–

Table 2–2, 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments:

revised footnote

–

iii

April 2001 – Revised June 2003

SPRS166D

Revision History

PAGE(S)

NO.

ADDITIONS/CHANGES/DELETIONS

Updated descriptions of the following signals in Table 2–3, Signal Descriptions:

7

–

Parallel Port – Address Bus:

PGPIO[3:0], HPI.HA[15:0], EMIF.A[17:2]

Parallel Port – Data Bus:

PGPIO[19:4], EMIF.D[31:16], HPI.HD[15:0], EMIF.D[15:0]

Parallel Port – Control Pins:

PGPIO35 – PGPIO20, EMIF.HOLDA

EMIF – Clock Pins:

ECLKIN, ECLKOUT1, ECLKOUT2, EMIFCLKS

Host Port – Data Pins:

PGPIO[43:36], HPI.HD[7:0]

Host Port – Control Pins:

PGPIO44, HPI.HAS, PGPIO45, HPI.HBIL

HPI Pins:

HCNTL1 and HCNTL0, HCS, HR/W, HDS2 and HDS1, HPIENA (updated “Other” entry also)

Interrupt and Reset Pins:

IACK

General-Purpose I/O Pins:

GPIO[7:0], GPIO4, XF

Oscillator/Clock Pins:

CLKOUT

Multichannel Buffered Serial Port Pins (McBSP0 and McBSP1):

CLKR0, FSR0, CLKX0, DX0, FSX0, CLKR1, FSR1, DX1, CLKX1, FSX1

Serial Port 2 (McBSP2/UART) Pins:

DX2, GPIO3, CLKX2, CLKR2, GPIO5, FSX2, FSR2

Timer Pins:

TIM0, TIM1

Supply Pins:

PSENSE

23

Figure 3–1, Block Diagram of the TMS320VC5502:

–

added “Instruction Cache” block

“HPI Module” block:

–

replaced “A[15:0]” with “HA[15:0]”

†

replaced “D[15:0]” with “HD[15:0] ”

added footnote about HD[15:8]

deleted “HD[7:0]”

24

26

Revised Section 3.1.1, On-Chip ROM

Updated Table 3–1, On-Chip ROM Layout

Figure 3–2, TMS320VC5502 Memory Map:

–

changed “MP/MC” to “MPNMC”

29

30

42

Table 3–4, TMS320VC5502 Routing of Parallel Port Mux Signals:

–

changed column header from “PARALLEL PORT MUX MODE = 0 (HPI NON-MULTIPLEX)” to

“PARALLEL/HOST PORT MUX MODE = 0 (HPI NON-MULTIPLEX)”

changed column header from “PARALLEL PORT MUX MODE = 1 (FULL EMIF)” to

“PARALLEL/HOST PORT MUX MODE = 1 (FULL EMIF)”

Table 3–5, TMS320VC5502 Routing of Host Port Mux Signals:

–

changed column header from “HOST PORT MUX MODE = 0 (PGPIO)” to

“PARALLEL/HOST PORT MUX MODE = 0 (PGPIO)”

–

changed column header from “HOST PORT MUX MODE = 1 (8-BIT HPI MULTIPLEXED)” to

“PARALLEL/HOST PORT MUX MODE = 1 (8-BIT HPI MULTIPLEXED)”

Revised Section 3.9, System Clock Generator

iv

SPRS166D

April 2001 – Revised June 2003

Revision History

PAGE(S)

NO.

ADDITIONS/CHANGES/DELETIONS

Updated Figure 3–10, System Clock Generator

42

43

44

45

46

47

48

50

Revised Section 3.9.1, Input Clock Source

Revised Section 3.9.1.1, Internal System Oscillator With External Crystal

Updated Table 3–10, Recommended Crystal Parameters

Revised Section 3.9.1.3, Clock Generation With PLL Enabled (PLL Mode)

Added Section 3.9.1.4, Frequency Ranges for Internal Clocks

Added Table 3–11, Internal Clocks Frequency Ranges

Revised Section 3.9.2.1, C55x Subsystem Clock Group

Revised Section 3.9.3, EMIF Input Clock Selection

Changed “OSCIN” to “OSCOUT” in Figure 3–12, Clock Generator Registers

Revised Section 3.9.4.4, External Memory Interface Clock Group

Updated descriptions of the following bits in Table 3–13, PLL Control/Status Register Bit Field Description:

–

STABLE

OSCPWRDN

57

58

Table 3–21, CLKOUT3 Select Register Bit Field Description:

Added footnote about the different options of the CLKOUT3 signal

–

Updated description of the CLKMD0 bit in Table 3–23, Clock Mode Control Register Bit Field Description:

CLKMD0 = 0: changed “OSCIN” to “OSCOUT”

–

Section 3.9.6, Reset Sequence:

–

revised GPIO4 bulleted item

deleted paragraph about the reset pin at power up

62

75

Revised Table 3–25, Peripheral Behavior at Entering IDLE State

Section 3.11.2, Parallel Port General-Purpose I/O (PGPIO):

–

Revised first paragraph

76

77

78

79

Table 3–37, Parallel GPIO Enable Register 0 Bit Field Description:

Revised bit description

–

Table 3–38, Parallel GPIO Direction Register 0 Bit Field Description:

Revised bit description

–

Table 3–39, Parallel GPIO Data Register 0 Bit Field Description:

Revised bit description

–

Table 3–40, Parallel GPIO Enable Register 1 Bit Field Description:

Revised bit description

–

Table 3–41, Parallel GPIO Direction Register 1 Bit Field Description:

Revised bit description

–

Table 3–42, Parallel GPIO Data Register 1 Bit Field Description:

Revised bit description

–

v

April 2001 – Revised June 2003

SPRS166D

Revision History

PAGE(S)

NO.

ADDITIONS/CHANGES/DELETIONS

80

81

82

Table 3–43, Parallel GPIO Enable Register 2 Bit Field Description:

Revised bit description of IOxEN bit

–

Table 3–44, Parallel GPIO Direction Register 2 Bit Field Description:

Revised bit description IOxDIR bit

–

Table 3–45, Parallel GPIO Data Register 2 Bit Field Description:

Revised bit description of IOxDAT bit

–

Table 3–46, Pins With Pullups, Pulldowns, and Bus Holders:

–

associated the TEST bit with the TCK, TDI, TMS, and TRST pins

associated the EMU bit with the EMU1/OFF and EMU0 pins

83

86

90

94

Figure 3–41, External Bus Control Register Layout (0x8800):

corrected address of register from 0x6C01 to 0x8800

–

Figure 3–43, XPORT Bus Error Register Layout (0x0102):

changed Reset Value of Bit 15 (INTERR)

–

Table 3–50, XPORT Bus Error Register Bit Field Description:

changed Reset Value of Bit 15 (INTERR)

–

Figure 3–47, System Configuration Register Layout (0x07FD):

changed Reset Value of Bits 15–6 (Reserved)

–

Table 3–54, System Configuration Register Bit Field Description:

changed Reset Value of Bits 15–6 (Reserved)

–

Changed Reset Value of the following registers in Table 3–57, Peripheral Bus Controller Configuration Registers:

–

XPORT Bus Error Register (XERR)

System Configuration Register (CONFIG)

95

Changed Reset Value of the following registers in Table 3–58, External Memory Interface Registers:

–

EMIF Global Control Register 1 (EGCR1)

EMIF CE1 Space Control Register 1 (CE1_1)

EMIF CE0 Space Control Register 1 (CE0_1)

EMIF CE0 Space Control Register 2 (CE0_2)

EMIF SDRAM Control Register 2 (SDC2)

EMIF SDRAM Extension Register 1 (SDX1)

EMIF SDRAM Extension Register 2 (SDX2)

96

Changed Reset Value of the following registers in Table 3–59, DMA Configuration Registers:

–

DMA Channel 0 Interrupt Control register [DMA_CICR0(5:0)]

DMA Channel 1 Interrupt Control register [DMA_CICR1(5:0)]

DMA Channel 2 Interrupt Control register [DMA_CICR2(5:0)]

DMA Channel 3 Interrupt Control register [DMA_CICR3(5:0)]

DMA Channel 4 Interrupt Control register [DMA_CICR4(5:0)]

DMA Channel 5 Interrupt Control register [DMA_CICR5(5:0)]

99

Changed Reset Value of the following registers in Table 3–63, Timers:

–

Timer Clock Speed Register, Timer #0 (GPTCLK_0)

Timer Control Register 2, Timer #0 (GPTCTL2_0)

Timer Clock Speed Register, Timer #1 (GPTCLK_1)

Timer Control Register 2, Timer #1 (GPTCTL2_1)

101

Changed Reset Value of the following registers in Table 3–64, Multichannel Serial Port #0:

–

Sample Rate Generator Register 1, McBSP #0 (SRGR1_0)

Sample Rate Generator Register 2, McBSP #0 (SRGR2_0)

vi

SPRS166D

April 2001 – Revised June 2003

Revision History

PAGE(S)

NO.

ADDITIONS/CHANGES/DELETIONS

102

103

104

Changed Reset Value of the following registers in Table 3–65, Multichannel Serial Port #1:

–

Sample Rate Generator Register 1, McBSP #1 (SRGR1_1)

Sample Rate Generator Register 2, McBSP #1 (SRGR2_1)

Changed Reset Value of the following registers in Table 3–66, Multichannel Serial Port #2:

–

Sample Rate Generator Register 1, McBSP #2 (SRGR1_2)

Sample Rate Generator Register 2, McBSP #2 (SRGR2_2)

Table 3–67, HPI:

–

changed Reset Value of PID [15:0] (PID LSW)

changed Reset Value of PID [31:16] (PID MSW)

added HPWREMU (0xA002)

added HGPIOINT1 ()xA004)

added HGPIOINT2 (0xA005)

added HGPIOEN (0xA006)

added HGPIODIR1 (0xA008)

added HGPIODAT1 (0xA00A)

added HGPIODIR2 (0xA00C)

added HGPIODAT2 (0xA00E)

added HGPIODIR3 (0xA010)

addedHGPIODAT3 (0xA012)

104

105

Changed Reset Value of the following register in Table 3–68, GPIO:

General-purpose I/O Direction Register (IODIR)

–

2

Table 3–70, I C:

2

added footnote to I2COAR (I C Own Address Register)

changed Reset Value of the I C Status Register (I2CSTR)

–

2

106

107

Table 3–72, External Bus Selection:

changed Word Address of the External Bus Control Register (XBCR) from “0x6C01” to “0x8800”

–

Changed Reset Value of the following registers in Table 3–75, Clock Controller Registers:

–

PLL Divider 1 Register (PLLDIV1)

PLL Divider 2 Register (PLLDIV2)

PLL Divider 3 Register (PLLDIV3)

107

Changed Reset Value of the following registers in Table 3–76, IDLE Control Registers:

–

Peripheral IDLE Status Register (PISTR)

Master IDLE Status Register (MISR)

110

Section 3.16.2, Interrupt Timing:

added paragraph about using TIM0, TIM1, WDTOUT, and HPI.HAS to generate interrupts to the CPU.

–

Added Section 3.16.3, Interrupt Acknowledge

vii

April 2001 – Revised June 2003

SPRS166D

Revision History

PAGE(S)

NO.

ADDITIONS/CHANGES/DELETIONS

111

Section 4, Documentation Support:

–

Removed:

–

TMS320C55x DSP Functional Overview (literature number SPRU312)

TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317)

–

Added:

–

TMS320VC5501/5502 DSP Instruction Cache Reference Guide (literature number SPRU630)

TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618)

TMS320VC5501/5502/5509 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU146)

TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)

TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (literature number SPRU613)

TMS320VC5501/5502/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide

(literature number SPRU592)

–

TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide (literature number SPRU621)

TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) Reference Guide

(literature number SPRU597)

113

Section 6.3, Recommended Operating Conditions:

–

changed MIN DV

changed MIN PV

from 2.7 V to 3.0 V

DD

V

–

V

–

:

IH

Hysteresis inputs: changed “DV

= 2.7 – 3.6 V” to “DV

DD

= 3.0 – 3.6 V” to “All other inputs”

= 3.0 – 3.6 V”

DD

Added “DV

:

Hysteresis inputs: changed “DV

Added “DV

DD

–

IL

= 2.7 – 3.6 V” to “DV

DD

= 3.0 – 3.6 V” to “All other inputs”

DD

114

Section 6.4, Electrical Characteristics Over Recommended Operating Case Temperature Range:

: deleted TEST CONDITION “DV = 2.7 – 3.0 V, I = MAX”

–

V

OH

DD

OH

115

116

117

118

Revised Figure 6–1, 3.3-V Test Load Circuit

Revised Section 6.5, Package Thermal Resistance Characteristics

Added Section 6.7.1, Internal System Oscillator With External Crystal

Updated Table 6–3, Recommended Crystal Parameters

Added Section 6.7.2, Layout Considerations

Table 6–4, CLKIN in Bypass Mode Timing Requirements:

–

Parameter C7 [t

–

]:

c(CI)

added “APLL Synthesis Disabled”

associated new footnote about using external crystal

] and C11 [t

added Parameters C10 [t

]

w(CIH)

w(CIL)

118

119

Table 6–5, CLKOUT in Bypass Mode Switching Characteristics:

removed footnote about using lock mode clocking option

–

Section 6.7.4:

–

renamed section from “Clock Generation in PLL Mode” to “Clock Generation in Lock Mode (APLL Synthesis Enabled)”

revised section

changed “Valid values for M are (multiply by) 1 to 16.” to “Valid values for M are (multiply by) 2 to 15.”

viii

SPRS166D

April 2001 – Revised June 2003

Revision History

PAGE(S)

NO.

ADDITIONS/CHANGES/DELETIONS

119

Table 6–6, CLKIN in Lock Mode Timing Requirements:

Parameter C7 [t ]:

–

c(CI)

associated new footnote about using external crystal

–

deleted “Oscillator enabled” row

deleted “Oscillator disabled”

changed MIN value from 40 ns to 10 ns

changed MAX value from 400 ns to 88.3 ns

122

134

135

Section 6.8, Memory Timings:

added “EMIF.” to signal names

–

Section 6.9, HOLD/HOLDA Timings:

– added “EMIF.” to signal names

Table 6–20, Reset Switching Characteristics:

–

deleted Parameter R5 [t

deleted Parameter R6 [t

renumbered parameters

]

d(RSL-LOWIV)

d(RSH-LOWV)

added Parameter R8 [t

added Parameter R9 [t

]

d(RSL-IOIM)

d(RSL-TGLD)

]

redefined signal groups in footnotes

deleted Low Group from footnotes

136

Figure 6–22, Reset Timings:

–

revised “EMIF Group” waveform

deleted Low Group waveform

added Input/Output Group waveform

added Toggle Group waveform

renumbered parameters according to Table 6–20, Reset Switching Characteristics

added footnotes which define signal groups

137

139

Table 6–22, External Interrupt and Interrupt Acknowledge Switching Characteristics:

Parameter I3 [t ]: changed MAX value from 3 ns to 6 ns

–

d(COH-IACKV)

Table 6–25:

–

renamed table from “GPIO Pins Configured as Inputs Switching Characteristics” to “GPIO Pins Configured as Outputs

Switching Characteristics”

–

Parameter G1 [t

]: changed MAX value from 3 ns to 8 ns

d(COH–GPIO)

140

141

Added Section 6.14, Parallel General-Purpose Input/Output (PGPIOx) Timings

Renumbered section titled “TIM0/TIM1/WDTOUT Timings” as Section 6.15

Added Section 6.15.1, TIM0/TIM1/WDTOUT Timer Pin Timings

Table 6–28:

–

renamed table from “TIM0/TIM1/WDTOUT Pins Configured as Inputs Timing Requirements” to “TIM0/TIM1/WDTOUT

Pins Configured as Timer Input Pins Timing Requirements”

141

Table 6–29:

–

renamed table from “TIM0/TIM1/WDTOUT Pins Configured as Outputs Switching Characteristics” to

“TIM0/TIM1/WDTOUT Pins Configured as Timer Output Pins Switching Characteristics”

–

Parameter T1 [t

Parameter T2 [t

]: changed MAX value from 3 ns to 5 ns

d(COH–TIMH)

d(COH–TIML)

Figure 6–28:

–

renamed figure from “TIM0/TIM1/WDTOUT Timings When Configured as Inputs” to “TIM0/TIM1/WDTOUT Timings When

Configured as Timer Input Pins”

ix

April 2001 – Revised June 2003

SPRS166D

Revision History

PAGE(S)

NO.

ADDITIONS/CHANGES/DELETIONS

141

Figure 6–29:

–

renamed figure from “TIM0/TIM1/WDTOUT Timings When Configured as Outputs” to “TIM0/TIM1/WDTOUT Timings

When Configured as Timer Output Pins”

142

144

145

Added Section 6.15.2, TIM0/TIM1/WDTOUT General-Purpose I/O Timings

Added Section 6.15.3, TIM0/TIM1/WDTOUT Interrupt Timings

Table 6–33, McBSP Transmit and Receive Timing Requirements:

–

Parameter M16 [t

Parameter M18 [t

Parameter M20 [t

], CLKR ext: changed MIN value from 2 ns to 6 ns

], CLKX ext: changed MIN value from 2 ns to 6 ns

h(CKRL–FRH)

h(CKRL–DRV)

h(CKXL–FXH)

146

149

Table 6–34, McBSP Transmit and Receive Switching Characteristics:

Parameter M7 [t ]: deleted “DXENA = 0” from “Delay time, CLKX high to DX valid. This applies to all bits

–

d(CKXH–DXV)

except the first bit transmitted.”

Table 6–37, McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0):

–

Parameter M30 [t

Parameter M31 [t

], SLAVE: changed MIN value from “2 – 6P” to “0 – 5P”

su(DRV–CKXL)

], SLAVE: changed MIN value from “6 + 6P” to “8 + 6P”

h(CKXL–DRV)

149

151

Table 6–38, McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0):

Parameter M26 [t ], SLAVE: changed MAX value from “5P + 10” to “4P + 18”

–

d(CKXH–DXV)

Table 6–40, McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0):

–

Parameter M36:

–

changed symbol from “t

“t

d(CKXH–DXV)” to d(CKXL–DXV)”

changed parameter description from “Delay time, CLKX high to DX valid” to “Delay time, CLKX low to DX valid”

SLAVE: changed MAX value from “5P + 10” to “4P + 18”

Parameter M37 [t

], SLAVE: changed MAX value from “5P + 10” to “4P + 18”

dis(CKXL–DXHZ)

152

154

Table 6–42, McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1):

Parameter M45 [t ], SLAVE: changed MAX value from “5P + 10” to “4P + 18”

–

d(CKXL–DXV)

Table 6–43, McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1):

–

Parameter M58 [t

Parameter M59 [t

], SLAVE: changed MIN value from “2 – 6P” to “0 – 5P”

su(DRV–CKXL)

], SLAVE: changed MIN value from “6 + 6P” to “8 + 6P”

h(CKXL–DRV)

154

156

Table 6–44, McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1):

–

Parameter M55 [t

Parameter M56 [t

], SLAVE: changed MAX value from “5P + 10” to “4P + 18”

d(CKXH–DXV)

dis(CKXH–DXHZ)

], SLAVE: changed MAX value from “5P + 10” to “4P + 18”

Section 6.17:

–

renamed section from “HPI Timings” to “Host-Port Interface Timings”

added “HPI.” to “HAS” signal name

156

162

164

165

Added Section 6.17.1, HPI Read and Write Timings

Added Section 6.17.2, HPI General-Purpose I/O Timings

Added Section 6.17.3, HPI.HAS Interrupt Timings

Section 6.18:

2 2

–

renamed section from “I C Timings” to “Inter-Integrated Circuit (I C) Timings”

165

Figure 6–47:

changed title from “I C Timings” to “I C Receive Timings”

2

–

x

SPRS166D

April 2001 – Revised June 2003

Revision History

PAGE(S)

NO.

ADDITIONS/CHANGES/DELETIONS

166

167

Figure 6–48:

changed title from “I C Timings” to “I C Transmit Timings”

2

–

Section 6.19:

–

renamed section from “UART Timings” to “Universal Asynchronous Receiver/Transmitter (UART) Timings”

Figure 6–49, UART Timings:

–

added “UART.” to “TX” and “RX” signal names

xi

April 2001 – Revised June 2003

SPRS166D

Revision History

xii

SPRS166D

April 2001 – Revised June 2003

Contents

Section

Page

1

2

TMS320VC5502 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

3

5

7

2.1

2.2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1

2.2.2

Ball Grid Array (GGW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Low-Profile Quad Flatpack (PGF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23

24

25

26

27

28

29

30

31

32

33

34

35

36

38

39

40

42

43

45

46

47

49

58

59

60

62

63

66

3.1

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1

3.1.2

3.1.3

3.1.4

3.1.5

On-Chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2

3.3

Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Configurable External Ports and Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1

3.3.2

3.3.3

3.3.4

Parallel Port Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Host Port Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Port 2 Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Bus Selection Register (XBSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.1

3.4.2

3.4.3

Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer Signal Selection Register (TSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5

3.6

3.7

3.8

Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

Inter-Integrated Circuit (I C) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Host-Port Interface (HPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Direct Memory Access (DMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.1

DMA Channel 0 Control Register (DMA_CCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9

System Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9.1

3.9.2

3.9.3

3.9.4

3.9.5

3.9.6

Input Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EMIF Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Changing the Clock Group Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10

Idle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10.1

3.10.2

3.10.3

3.10.4

3.10.5

Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IDLE Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Module Behavior at Entering IDLE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Wake-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Auto-Wakeup/Idle Function for McBSP and DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiii

April 2001 – Revised June 2003

SPRS166D

Contents

Section

Page

3.10.6

3.10.7

Clock State of Multiplexed Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IDLE Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

66

3.11

General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

73

3.11.1

3.11.2

General-Purpose I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parallel Port General-Purpose I/O (PGPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

73

75

3.12

3.13

External Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12.1 External Bus Control Register (XBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internal Ports and System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

82

83

84

3.13.1

3.13.2

3.13.3

3.13.4

3.13.5

XPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Time-Out Control Register (TOCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

84

87

89

90

91

3.14

3.15

3.16

CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

92

94

108

109

110

3.16.1

3.16.2

3.16.3

IFR and IER Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4

5

6

Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

111

112

113

114

115

116

117

118

119

120

122

125

129

134

135

137

138

6.1

6.2

6.3

6.4

6.5

6.6

6.7

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics Over Recommended Operating Case Temperature Range . . . . . . .

Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7.1

6.7.2

6.7.3

6.7.4

6.7.5

Internal System Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Generation in Bypass Mode (APLL Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Generation in Lock Mode (APLL Synthesis Enabled) . . . . . . . . . . . . . . . . . . .

EMIF Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8

Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8.1

6.8.2

6.8.3

Asynchronous Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programmable Synchronous Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Synchronous DRAM Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.9

HOLD/HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Interrupt and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . .

XF Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10

6.11

6.12

xiv

SPRS166D

April 2001 – Revised June 2003

Contents

Page

Section

6.13

6.14

6.15

General-Purpose Input/Output (GPIOx) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parallel General-Purpose Input/Output (PGPIOx) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIM0/TIM1/WDTOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

139

140

141

142

144

145

148

149

156

162

164

165

167

6.15.1

6.15.2

6.15.3

TIM0/TIM1/WDTOUT Timer Pin Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIM0/TIM1/WDTOUT General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . .

TIM0/TIM1/WDTOUT Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16

6.17

Multichannel Buffered Serial Port (McBSP) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16.1

6.16.2

6.16.3

McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

McBSP as SPI Master or Slave Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Host-Port Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.17.1

6.17.2

6.17.3

HPI Read and Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HPI General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HPI.HAS Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

6.18

6.19

Inter-Integrated Circuit (I C) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Universal Asynchronous Receiver/Transmitter (UART) Timings . . . . . . . . . . . . . . . . . . . . . . . . .

7

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

168

169

7.1

7.2

Ball Grid Array Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Low-Profile Quad Flatpack Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xv

April 2001 – Revised June 2003

SPRS166D

Figures

Figure

List of Figures

Page

2–1

2–2

176-Terminal GGW Ball Grid Array (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

176-Pin PGF Low-Profile Quad Flatpack (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

5

3–1

3–2

3–3

3–4

3–5

3–6

3–7

3–8

3–9

Block Diagram of the TMS320VC5502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320VC5502 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Bus Selection Register Layout (0x6C00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer Signal Selection Register Layout (0x8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

UART Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23

26

31

33

34

35

37

38

40

42

43

47

49

51

52

53

54

55

56

57

58

66

68

69

71

72

73

74

76

77

78

79

2

I C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA Channel 0 Control Register Layout (0x0C01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 System Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–11 Internal System Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–12 Clock Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–13 PLL Control/Status Register Layout (0x1C80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–14 PLL Multiplier Control Register Layout (0x1C88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–15 PLL Divider 0 Register Layout (0x1C8A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–16 PLL Divider 1 Register Layout (0x1C8C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–17 PLL Divider 2 Register Layout (0x1C8E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–18 PLL Divider 3 Register Layout (0x1C90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–19 Oscillator Divider1 Register Layout (0x1C92) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–20 Oscillator Wakeup Control Register Layout (0x1C98) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–21 CLKOUT3 Select Register Layout (0x1C82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–22 CLKOUT Selection Register Layout (0x8400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–23 Clock Mode Control Register Layout (0x8C00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–24 IDLE Configuration Register Layout (0x0001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–25 IDLE Status Register Layout (0x0002) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–26 Peripheral IDLE Control Register Layout (0x9400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–27 Peripheral IDLE Status Register Layout (0x9401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–28 Master IDLE Control Register Layout (0x9402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–29 Master IDLE Status Register Layout (0x9403) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–30 GPIO Direction Register Layout (0x3400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–31 GPIO Data Register Layout (0x3401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–32 Parallel GPIO Enable Register 0 Layout (0x4400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–33 Parallel GPIO Direction Register 0 Layout (0x4401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–34 Parallel GPIO Data Register 0 Layout (0x4402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–35 Parallel GPIO Enable Register 1 Layout (0x4403) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–36 Parallel GPIO Direction Register 1 Layout (0x4404) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–37 Parallel GPIO Data Register 1 Layout (0x4405) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xvi

SPRS166D

April 2001 – Revised June 2003

Figures

Page

Figure

3–38 Parallel GPIO Enable Register 2 Layout (0x4406) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–39 Parallel GPIO Direction Register 2 Layout (0x4407) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–40 Parallel GPIO Data Register 2 Layout (0x4408) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–41 External Bus Control Register Layout (0x8800) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–42 XPORT Configuration Register Layout (0x0100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–43 XPORT Bus Error Register Layout (0x0102) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–44 DPORT Configuration Register Layout (0x0200) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–45 DPORT Bus Error Register Layout (0x0202) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–46 IPORT Bus Error Register Layout (0x0302) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–47 System Configuration Register Layout (0x07FD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–48 Time-Out Control Register Layout (0x9000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–49 IFR0, IER0, DBIFR0, and DBIER0 Registers Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–50 IFR1, IER1, DBIFR1, and DBIER1 Registers Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

80

81

83

85

86

87

88

89

90

91

109

6–1

6–2

6–3

6–4

6–5

6–6

6–7

6–8

6–9

3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internal System Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bypass Mode Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Multiply-by-N Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ECLKIN Timings for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ECLKOUT1 Timings for EMIF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ECLKOUT2 Timings for EMIF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Asynchronous Memory Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Asynchronous Memory Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

115

117

118

119

120

121

123

124

126

127

128

130

131

132

133

134

136

137

138

139

140

141

6–10 Programmable Synchronous Interface Read Timings (With Read Latency = 2) . . . . . . . . . . . . . . . .

6–11 Programmable Synchronous Interface Write Timings (With Write Latency = 0) . . . . . . . . . . . . . . . .

6–12 Programmable Synchronous Interface Write Timings (With Write Latency = 1) . . . . . . . . . . . . . . . .

6–13 SDRAM Read Command (CAS Latency 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–14 SDRAM Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–15 SDRAM ACTV Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–16 SDRAM DCAB Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–17 SDRAM DEAC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–18 SDRAM REFR Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–19 SDRAM MRS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–20 SDRAM Self-Refresh Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–21 EMIF.HOLD/HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–22 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–23 External Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–24 External Interrupt Acknowledge Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–25 XF Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–26 General-Purpose Input/Output (GPIOx) Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–27 Parallel General-Purpose Input/Output (PGPIOx) Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–28 TIM0/TIM1/WDTOUT Timings When Configured as Timer Input Pins . . . . . . . . . . . . . . . . . . . . . . . .

xvii

April 2001 – Revised June 2003

SPRS166D

Figures

Figure

Page

6–29 TIM0/TIM1/WDTOUT Timings When Configured as Timer Output Pins . . . . . . . . . . . . . . . . . . . . . .

6–30 TIM0/TIM1/WDTOUT General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–31 TIM0/TIM1/WDTOUT Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–32 McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–33 McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–34 McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–35 McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . .

6–36 McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . .

6–37 McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . .

6–38 McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . .

6–39 Non-Multiplexed Read/Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–40 Multiplexed Read Timings Using HPI.HAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–41 Multiplexed Read Timings With HPI.HAS Held High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–42 Multiplexed Write Timings Using HPI.HAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–43 Multiplexed Write Timings With HPI.HAS Held High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–44 HINT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–45 HPI General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–46 HPI.HAS Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

141

143

144

147

148

150

151

153

155

157

158

159

160

161

163

164

165

166

167

2

6–47 I C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

6–48 I C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–49 UART Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1

7–2

TMS320VC5502 176-Ball MicroStar BGA Plastic Ball Grid Array Package . . . . . . . . . . . . . . . . . . .

TMS320VC5502 176-Pin Low-Profile Quad Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

168

169

xviii

SPRS166D

April 2001 – Revised June 2003

Tables

Page

List of Tables

Table

2–1

2–2

2–3

176-Terminal GGW Ball Grid Array Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

176-Pin PGF Low-Profile Quad Flatpack Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4

6

7

3–1

3–2

3–3

3–4

3–5

3–6

3–7

3–8

On-Chip ROM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Boot Configuration Selection Via the BOOTM[2:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320VC5502 Routing of Parallel Port Mux Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320VC5502 Routing of Host Port Mux Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320VC5502 Routing of Serial Port 2 Mux Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Bus Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer Signal Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Synchronization Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internal Clocks Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Control/Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Multiplier Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Divider 0 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Divider 1 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Divider 2 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Divider3 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Oscillator Divider1 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Oscillator Wakeup Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKOUT3 Select Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKOUT Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Mode Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Number of Reference Clock Cycles Needed Until Program Flow Begins . . . . . . . . . . . . . . . . . . . . .

Peripheral Behavior at Entering IDLE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Wake-Up Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Domain Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IDLE Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral IDLE Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Master IDLE Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Master IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GPIO Direction Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GPIO Data Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320VC5502 PGPIO Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parallel GPIO Enable Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parallel GPIO Direction Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parallel GPIO Data Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parallel GPIO Enable Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parallel GPIO Direction Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parallel GPIO Data Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24

25

27

29

30

32

35

41

44

45

49

50

51

52

53

54

55

56

57

58

59

62

65

66

67

68

69

71

72

73

74

75

76

77

78

79

3–9

3–10

3–11

3–12

3–13

3–14

3–15

3–16

3–17

3–18

3–19

3–20

3–21

3–22

3–23

3–24

3–25

3–26

3–27

3–28

3–29

3–30

3–31

3–32

3–33

3–34

3–35

3–36

3–37

3–38

3–39

3–40

3–41

3–42

xix

April 2001 – Revised June 2003

SPRS166D

Tables

Table

Page

3–43

3–44

3–45

3–46

3–47

3–48

3–49

3–50

3–51

3–52

3–53

3–54

3–55

3–56

3–57

3–58

3–59

3–60

3–61

3–62

3–63

3–64

3–65

3–66

3–67

3–68

3–69

3–70

3–71

3–72

3–73

3–74

3–75

3–76

3–77

Parallel GPIO Enable Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parallel GPIO Direction Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parallel GPIO Data Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pins With Pullups, Pulldowns, and Bus Holders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Bus Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Addresses Under Scope of XPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

XPORT Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

XPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DPORT Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Time-Out Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Bus Controller Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Memory Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Trace FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer Signal Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Multichannel Serial Port #0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Multichannel Serial Port #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Multichannel Serial Port #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Device Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

80

81

82

83

84

85

86

87

88

89

90

91

92

94

95

96

99

101

102

103

104

105

106

107

108

2

I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKOUT Selector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IDLE Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1

6–2

6–3

6–4

6–5

6–6

6–7

6–8

6–9

6–10

6–11

Thermal Resistance Characteristics (Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Thermal Resistance Characteristics (Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKIN in Bypass Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKOUT in Bypass Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKIN in Lock Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKOUT in Lock Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EMIF Timing Requirements for ECLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EMIF Switching Characteristics for ECLKOUT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EMIF Switching Characteristics for ECLKOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Asynchronous Memory Cycle Timing Requirements for ECLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . .

115

116

117

118

119

120

121

122

xx

SPRS166D

April 2001 – Revised June 2003

Tables

Page

Table

6–12

6–13

6–14

6–15

6–16

6–17

6–18

6–19

6–20

6–21

6–22

6–23

6–24

6–25

6–26

6–27

6–28

6–29

6–30

6–31

6–32

6–33

6–34

6–35

6–36

6–37

6–38

6–39

6–40

6–41

6–42

6–43

6–44

6–45

6–46

6–47

6–48

6–49

6–50

6–51

6–52

6–53

Asynchronous Memory Cycle Switching Characteristics for ECLKOUT1 . . . . . . . . . . . . . . . . . . . . .

Programmable Synchronous Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programmable Synchronous Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .

Synchronous DRAM Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Synchronous DRAM Cycle Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EMIF.HOLD/HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EMIF.HOLD/HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Interrupt and Interrupt Acknowledge Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . .

External Interrupt and Interrupt Acknowledge Switching Characteristics . . . . . . . . . . . . . . . . . . . . .

XF Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GPIO Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GPIO Pins Configured as Outputs Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PGPIO Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PGPIO Pins Configured as Outputs Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIM0/TIM1/WDTOUT Pins Configured as Timer Input Pins Timing Requirements . . . . . . . . . . . . .

TIM0/TIM1/WDTOUT Pins Configured as Timer Output Pins Switching Characteristics . . . . . . . .

TIM0/TIM1/WDTOUT General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .

TIM0/TIM1/WDTOUT General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . .

TIM0/TIM1/WDTOUT Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

McBSP Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

McBSP Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . .

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . .

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . .

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . .

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . .

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . .

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . .

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . .

HPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HPI Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HPI General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HPI General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HPI.HAS Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

122

125

129

134

135

137

138

139

140

141

142

144

145

146

148

149

151

152

154

156

162

164

165

166

167

2

I C Signals (SDA and SCL) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

I C Signals (SDA and SCL) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

UART Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxi

April 2001 – Revised June 2003

SPRS166D

Tables

xxii

SPRS166D

April 2001 – Revised June 2003

Features

1

TMS320VC5502 Features

D

High-Performance, Low-Power, Fixed-Point

TMS320C55x Digital Signal

Processor (DSP)

– 3.33-/5-ns Instruction Cycle Time

– 300-/200-MHz Clock Rate

– 16K-Byte Instruction Cache (I-Cache)

– One/Two Instructions Executed per Cycle

– Dual Multipliers [Up to 600 Million

Multiply-Accumulates Per Second

(MMACS)]

D

Programmable Low-Power Control of Six

Device Functional Domains

On-Chip Peripherals

– Six-Channel Direct Memory Access

(DMA) Controller

– Three Multichannel Buffered Serial Ports

(McBSPs)

– Programmable Analog Phase-Locked

Loop (APLL) Clock Generator

– Two Arithmetic/Logic Units (ALUs)

– One Program Bus, Three Internal

Data/Operand Read Buses, and Two

Internal Data/Operand Write Buses

– General-Purpose I/O (GPIO) Pins and a

Dedicated Output Pin (XF)

– 8-Bit/16-Bit Parallel Host-Port Interface

(HPI)

D

Instruction Cache (16K Bytes)

– Four Timers

32K x 16-Bit On-Chip RAM That is

Composed of Eight Blocks of 4K × 16-Bit

Dual-Access RAM (DARAM) (64K Bytes)

– Two 64-Bit General-Purpose Timers

– 64-Bit Programmable Watchdog Timer

– 64-Bit DSP/BIOS Counter

D

16K × 16-Bit One-Wait-State On-Chip ROM

(32K Bytes)

2

– Inter-Integrated Circuit (I C) Interface

– Universal Asynchronous Receiver/

Transmitter (UART)

8M × 16-Bit Maximum Addressable External

Memory Space

D

On-Chip Scan-Based Emulation Logic

32-Bit External Parallel Bus Memory

Supporting External Memory Interface

(EMIF) With General-Purpose Input/Output

(GPIO) Capabilities and Glueless Interface

to:

– Asynchronous Static RAM (SRAM)

– Asynchronous EPROM

– Synchronous DRAM (SDRAM)

– Synchronous Burst RAM (SBRAM)

†

IEEE Std 1149.1 (JTAG) Boundary Scan

Logic

Packages:

– 176-Terminal LQFP (Low-Profile Quad

Flatpack) (PGF Suffix)

– 176-Terminal MicroStar BGA (Ball Grid

Array) (GGW Suffix)

D

3.3-V I/O Supply Voltage

D

Emulation/Debug Trace Capability Saves

Last 16 Program Counter (PC)

Discontinuities and Last 32 PC Values

1.26-V Core Supply Voltage

TMS320C55x, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.

All trademarks are the property of their respective owners.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

1

April 2001 – Revised June 2003

SPRS166D

Introduction

2

Introduction

This section describes the main features of the TMS320VC5502 and gives a brief description of the device.

NOTE: This document is designed to be used in conjunction with the TMS320C55x DSP CPU Reference

Guide (literature number SPRU371).

2.1 Description

The TMS320VC5502 (5502) fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP

generation CPU processor core. The C55x DSP architecture achieves high performance and low power

through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal

bus structure that is composed of one program bus, three data read buses, two data write buses, and

additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to

threedatareadsandtwodatawritesinasinglecycle. Inparallel, theDMAcontrollercanperformdatatransfers

independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication

in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of

the ALUs is under instruction set control, providing the ability to optimize parallel activity and power

consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The

InstructionUnit(IU)performs32-bitprogramfetchesfrominternalorexternalmemoryandqueuesinstructions

for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources,

and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution

of conditional instructions.

The 5502 peripheral set includes an external memory interface (EMIF) that provides glueless access to

asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as

synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog timer, and

an I-Cache. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a

variety of industry-standard serial devices, and multichannel communication with up to 128 separately

enabled channels. The host-port interface (HPI) is a 8-/16-bit parallel interface used to provide host processor

access to 32K words of internal memory on the 5502. The HPI can be configured in either multiplexed or

non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller

provides data movement for six independent channel contexts without CPU intervention. Two

general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog phase-locked loop

(APLL) clock generation are also included.

The 5502 is supported by the industry’s award-winning eXpressDSP , Code Composer Studio Integrated

Development Environment (IDE), DSP/BIOS , Texas Instruments’ algorithm standard, and the industry’s

largest third-party network. The Code Composer Studio IDE features code generation tools that include a

C Compiler, Visual Linker, simulator, RTDX , XDS510 emulation device drivers, and evaluation modules.

The 5502 is also supported by the C55x DSP Library, which features more than 50 foundational software

kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

C55x, eXpressDSP, Code Composer Studio, RTDX, and XDS510 are trademarks of Texas Instruments.

2

SPRS166D

April 2001 – Revised June 2003

Introduction

2.2 Pin Assignments

2.2.1 Ball Grid Array (GGW)

Figure 2–1 illustrates the ball locations for the 176-pin ball grid array (BGA) package and Table 2–1 lists the

signal names and terminal numbers.

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11

13 15

12 14 16

17

2

4

6

8

10

Figure 2–1. 176-Terminal GGW Ball Grid Array (Bottom View)

3

April 2001 – Revised June 2003

SPRS166D

Introduction

Table 2–1. 176-Terminal GGW Ball Grid Array Ball Assignments

BALL

NO.

BALL

NO.

BALL

NO.

BALL

NO.

SIGNAL NAME

B1

C2

C1

D3

D2

D1

E3

E2

E1

F3

F2

F1

G4

G3

G2

G1

H1

H4

H3

H2

J1

GPIO6

GPIO4

GPIO2

GPIO1

GPIO0

TIM1

U2

T3

HCNTL1

HCNTL0

T17

R16

R17

P15

P16

P17

N15

N16

N17

M15

M16

M17

L14

L15

L16

L17

K17

K14

K15

K16

J17

A19

A18

A16

B15

A15

C14

B14

A14

C13

B13

A13

C12

B12

A12

D11

C11

B11

A11

A10

D10

C10

B10

A9

D16

D15

D14

D13

D12

D11

D10

D9

U3

V

SS

V

SS

R4

HR/W

HDS2

A17

A16

T4

U4

CV

DV

DD

TIM0

R5

HDS1

HRDY

A15

A14

INT0

T5

CV

U5

DV

V

SS

DV

DD

D8

D7

INT1

INT2

R6

CLKOUT

XF

A13

A12

T6

DV

U6

V

SS

CV

V

SS

D6

DD

INT3

NMI/WDTOUT

IACK

P7

C15

C14

A11

A10

A9

R7

D5

D4

T7

HINT

V

SS

U7

PV

DD

A8

CV

DD

CLKR0

DR0

U8

PSENSE

X1

DV

D3

D2

D1

D0

DD

P8

A7

A6

A5

FSR0

CLKX0

R8

X2/CLKIN

EMIFCLKS

T8

CV

DD

DX0

U9

V

SS

V

SS

A4

V

SS

J4

P9

C13

C12

C11

C10

C9

J14

D9

EMU1/OFF

J3

FSX0

CLKR1

DR1

R9

J15

A3

A2

C9

EMU0

TDO

J2

T9

J16

B9

K1

K2

K4

K3

L1

U10

T10

P10

R10

U11

T11

R11

P11

U12

T12

R12

U13

T13

R13

U14

T14

R14

U15

T15

U16

H17

H16

H14

H15

G17

G16

G15

G14

F17

F16

F15

E17

E16

E15

D17

D16

D15

C17

C16

B17

CV

A8

V

SS

DD

FSR1

DX1

D31

D30

D29

B8

TDI

TRST

TCK

C8

D8

CLKX1

C7

C8

V

SS

V

SS

V

SS

A7

TMS

L2

FSX1

DR2

DX2

ECLKIN

D28

D27

D26

B7

RESET

HPIENA

HD7

L3

ECLKOUT2

ECLKOUT1

C7

L4

D7

M1

M2

M3

N1

N2

N3

P1

P2

P3

R1

R2

T1

CV

A6

CV

DD

SP3

SP2

DV

DD

C6

C5

DV

DD

HD6

HD5

DV

D25

D24

B6

C6

DV

A5

DD

SP1

SP0

C4

C3

D23

D22

D21

D20

D19

B5

HD4

HD3

C5

V

SS

V

SS

C2

A4

CV

DD

SCL

SDA

HC1

HC0

HCS

B4

HD2

HD1

C1

C0

C4

V

SS

A3

V

SS

A21

A20

D18

D17

B3

HD0

A2

GPIO7

NOTE: CV

is core V

, DV

is I/O V

, and PV

is PLL V

. PSENSE must be connected to ground.

DD

4

SPRS166D

April 2001 – Revised June 2003

Introduction

2.2.2 Low-Profile Quad Flatpack (PGF)

Figure 2–2illustratesthepinlocationsforthe176-pinlow-profilequadflatpack(LQFP)andTable 2–2 provides

a numerical list (by pin number) of the pin assignments.

132

89

133

88

176

45

1

44

Figure 2–2. 176-Pin PGF Low-Profile Quad Flatpack (Top View)

5

April 2001 – Revised June 2003

SPRS166D

Introduction

Table 2–2. 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments

NO.

SIGNAL NAME

1

GPIO6

GPIO4

GPIO2

GPIO1

GPIO0

TIM1

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

HCNTL1

HCNTL0

89

90

A19

A18

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

D16

D15

D14

D13

D12

D11

D10

D9

2

3

V

SS

91

V

SS

4

HR/W

HDS2

92

A17

A16

5

93

6

CV

94

DV

DD

7

TIM0

HDS1

HRDY

95

A15

A14

8

INT0

96

9

CV

DV

97

V

SS

DV

DD

D8

D7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

INT1

INT2

CLKOUT

XF

98

A13

A12

99

DV

V

SS

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

CV

V

SS

D6

DD

INT3

NMI/WDTOUT

IACK

C15

C14

A11

A10

A9

D5

D4

HINT

V

SS

PV

DD

A8

CV

DD

CLKR0

DR0

PSENSE

X1

DV

D3

D2

D1

D0

DD

A7

A6

A5

FSR0

CLKX0

X2/CLKIN

EMIFCLKS

CV

DD

DX0

V

SS

V

SS

A4

V

SS

C13

C12

C11

C10

C9

EMU1/OFF

FSX0

CLKR1

DR1

A3

A2

EMU0

TDO

CV

V

SS

DD

FSR1

DX1

D31

D30

D29

TDI

TRST

TCK

C8

CLKX1

C7

V

SS

V

SS

V

SS

TMS

FSX1

DR2

DX2

ECLKIN

D28

D27

D26

RESET

HPIENA

HD7

ECLKOUT2

ECLKOUT1

CV

DD

SP3

SP2

DV

DD

C6

C5

DV

DD

HD6

HD5

DV

D25

D24

DV

DD

SP1

SP0

C4

C3

D23

D22

D21

D20

D19

HD4

HD3

V

SS

V

SS

C2

CV

DD

SCL

SDA

HC1

HC0

HCS

HD2

HD1

C1

C0

V

SS

V

SS

A21

A20

D18

D17

HD0

GPIO7

NOTE: CV

is core V

, DV

is I/O V

, and PV

is PLL V

. PSENSE must be connected to ground.

DD

6

SPRS166D

April 2001 – Revised June 2003

Introduction

2.3 Signal Descriptions

Table 2–3 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2, Pin

Assignments, for exact pin locations based on package type.

Table 2–3. Signal Descriptions

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

Parallel Port — Address Bus

The A[21:18] pins of the Parallel Port serve oneoftwofunctions:parallelgeneral-purpose

input/output (PGPIO) signals PGPIO[3:0] or external memory interface (EMIF) address

bus signals EMIF.A[21:18]. The function of the A[21:18] pins is determined by the state of

theGPIO6pinduringreset. TheA[21:18]pinsaresettoPGPIO[3:0]ifGPIO6islowduring

reset. The A[21:18] pins are set to EMIF.A[21:18] if GPIO6 is high during reset. The

function of the A[21:18] pins will be set once the device is taken out of reset (RESET pin

transitions from a low to high state).

A[21:18]

I/O/Z

The A[21:18] bus includes bus holders to reduce the static power dissipation caused by

floating, unused pins. The bus holders also eliminate the need for external bias resistors

onunusedpins. Whenthebusgoesintoahigh-impedancestate, thebusholderskeepthe

address bus at the logic level that was most recently driven. The bus holders are enabled

at reset and can be enabled/disabled through the External Bus Control Register (XBCR).

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO[3:0] is selected if GPIO6 is low during reset. The

PGPIO[3:0] signals are configured as inputs after reset.

PGPIO[3:0]

I/O/Z

O/Z

EMIF address bus. EMIF.A[21:18] is selected if GPIO6 is high during reset. The

EMIF.A[21:18] signals are in a high-impedance state during reset and are configured as

outputs after reset with an output value of 0.

EMIF.A[21:18]

The A[17:2] pins of the Parallel Port serve one of two functions: host-port interface (HPI)

address bus signals HPI.HA[15:0] or external memory interface (EMIF) address bus

signals EMIF.A[17:2]. The function of the A[17:2] pins is determined by the state of the

GPIO6 pin during reset. The A[17:2] pins are set to HPI.HA[15:0] if GPIO6 is low during

reset. The A[17:2] pins are set to EMIF.A[17:2] if GPIO6 is high during reset. The function

of the A[17:2] pins will be set once the device is taken out of reset (RESET pin transitions

from a low to high state).

A[17:2]

I/O/Z

The A[17:2] bus includes bus holders to reduce the static power dissipation caused by

floating, unused pins. The bus holders also eliminate the need for external bias resistors

onunusedpins. Whenthebusgoesintoahigh-impedancestate, thebusholderskeepthe

address bus at the logic level that was most recently driven. The bus holders are enabled

at reset and can be enabled/disabled through the External Bus Control Register (XBCR).

C, D, F,

M

HPI address bus. HPI.HA[15:0] is selected when GPIO6 is low during reset. The

HPI.HA[15:0] signals are configured as inputs after reset.

The HPI will operate in non-multiplexed mode when GPIO6 is low during reset. In

non-multiplexed mode, the HPI uses separate address and data buses: a 16-bit address

bus (HPI.HA[15:0]) and a 16-bit data bus (HPI.HD[15:0]). Each host cycle on the data bus

consists of one 16-bit data transfer.

HPI.HA[15:0]

EMIF.A[17:2]

I

EMIF address bus. EMIF.A[17:2] is selected when GPIO6 is high during reset. The

EMIF.A[17:2] signals are in a high-impedance state during reset and are configured as

outputs after reset with an output value of 0.

O/Z

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

7

April 2001 – Revised June 2003

SPRS166D

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

Parallel Port — Data Bus

TheD[31:16] pins of the Parallel Port serve one of two functions: parallel general-purpose

input/output(PGPIO) signals PGPIO[19:4] or external memory interface (EMIF) data bus

signals EMIF.D[31:16]. The function of the D[31:16] pins is determined by the state of the

GPIO6 pin during reset. The D[31:16] pins are set to PGPIO[19:4] if GPIO6 is low during

reset. The D[31:16] pins are set to EMIF.D[31:16] if GPIO6 is high during reset. The

function of the D[31:16] pins will be set once the device is taken out of reset (RESET pin

transitions from a low to high state).

D[31:16]

I/O/Z

The D[31:16] bus includes bus holders to reduce the static power dissipation caused by

floating, unused pins. The bus holders also eliminate the need for external bias resistors

onunusedpins. Whenthebusgoesintoahigh-impedancestate, thebusholderskeepthe

data bus at the logic level that was most recently driven. The bus holders are enabled at

reset and can be enabled/disabled through the External Bus Control Register (XBCR).

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO[19:4] is selected when GPIO6 is low during reset.

The PGPIO[19:4] signals are configured as inputs after reset.

PGPIO[19:4]

I/O/Z

EMIF data bus. EMIF.D[31:16] is selected when GPIO6 is high during reset. The

EMIF.D[31:16] signals are configured as inputs after reset.

EMIF.D[31:16]

The D[15:0] pins of the Parallel Port serve one of two functions: host-port interface (HPI)

data bus signals HPI.HD[15:0] and external memory interface (EMIF) data bus signals

EMIF.D[15:0].The function of the D[15:0] pins is determined by the state of the GPIO6 pin

during reset. The D[15:0] pins are set to HPI.HD[15:0] if GPIO6 is low during reset. The

D[15:0] pins are set to EMIF.D[15:0] if GPIO6 is high during reset. The function of the

D[15:0] pins will be set once the device is taken out of reset (RESET pin transitions from a

low to high state).

D[15:0]

I/O/Z

The D[15:0] bus includes bus holders to reduce the static power dissipation caused by

floating, unused pins. The bus holders also eliminate the need for external bias resistors

on unused pins. When the bus goes into a high-impedance state, the bus holders keep

the data bus at the logic level that was most recently driven. The bus holders are enabled

at reset and can be enabled/disabled through the External Bus Control Register (XBCR).

C, D, F,

M

HPI data bus. HPI.HD[15:0] is selected when GPIO6 is low during reset. The

HPI.HD[15:0] signals are configured as inputs after reset.

The HPI will operate in non-multiplexed mode when GPIO6 is low during reset. In

non-multiplexed mode, the HPI uses separate address and data buses: a 16-bit address

bus (HPI.HA[15:0]) and a 16-bit data bus (HPI.HD[15:0]). Each host cycle on the data bus

consists of one 16-bit data transfer.

HPI.HD[15:0]

EMIF.D[15:0]

I/O/Z

EMIF data bus. EMIF.D[15:0] is selected when GPIO6 is high during reset. The

EMIF.D[15:0] signals are configured as inputs after reset.

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

8

SPRS166D

April 2001 – Revised June 2003

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

Parallel Port — Control Pins

The C0 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO20 or external memory interface control signal

EMIF.ARE/SADS/SDCAS/SRE. The function of the C0 pin is determined by the state of

theGPIO6pinduringreset. TheC0pinissettoPGPIO20ifGPIO6islowduringreset. The

C0 pin is set to EMIF.ARE/SADS/SDCAS/SRE if GPIO6 is high during reset. The function

of the C0 pin will be set once the device is taken out of reset (RESET pin transitions from a

low to high state).

C0

I/O/Z

Parallel general-purpose I/O. PGPIO20 is selected when GPIO6 is low during reset.

The PGPIO20 signal is configured as an input after reset.

PGPIO20

C, D, F,

G, H, M

EMIFcontrolpin. EMIF.ARE/SADS/SDCAS/SREisselectedwhenGPIO6ishighduring

reset. The EMIF.ARE/SADS/SDCAS/SRE signal is in a high-impedance state during

reset and is set to output after reset with an output value of 1.

EMIF.ARE/SADS/

SDCAS/SRE

The EMIF.ARE/SADS/SDCAS/SRE signal serves four different functions when used by

the EMIF: asynchronous memory read-enable (EMIF.ARE), synchronous memory

address strobe (EMIF.SADS), SDRAM column-address strobe (EMIF.SDCAS), and

synchronousread-enable(EMIF.SRE)(selectedbyRENENintheCESecondaryControl

Register 1).

O/Z

The C1 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO21 or external memory interface control signal

EMIF.AOE/SOE/SDRAS. The function of the C1 pin is determined by the state of the

GPIO6pinduringreset. TheC1pinissettoPGPIO21ifGPIO6islowduringreset. TheC1

pin is set to EMIF.AOE/SOE/SDRAS if GPIO6 is high during reset. The function of the C1

pin will be set once the device is taken out of reset (RESET pin transitions from a low to

high state).

C1

I/O/Z

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO21 is selected when GPIO6 is low during reset.

The PGPIO21 signal is configured as an input after reset.

PGPIO21

I/O/Z

O/Z

EMIF control pin. EMIF.AOE/SOE/SDRAS is selected when GPIO6 is high during reset.

TheEMIF.AOE/SOE/SDRASsignalisinahigh-impedancestateduringresetandissetto

output after reset with an output value of 1.

EMIF.AOE/SOE/

SDRAS

The EMIF.AOE/SOE/SDRAS signal serves three different functions when used by the

EMIF: asynchronous memory output-enable (EMIF.AOE), synchronous memory

output-enable (EMIF.SOE), and SDRAM row-address strobe (EMIF.SDRAS).

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

9

April 2001 – Revised June 2003

SPRS166D

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Parallel Port — Control Pins (Continued)

Function

†

The C2 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO22 or external memory interface control signal

EMIF.AWE/SWE/SDWE. The function of the C2 pin is determined by the state of the

GPIO6pinduringreset. TheC2pinissettoPGPIO22ifGPIO6islowduringreset. TheC2

pin is set to EMIF.AWE/SWE/SDWE if GPIO6 is high during reset. The function of the C2

pin will be set once the device is taken out of reset (RESET pin transitions from a low to

high state).

C2

I/O/Z

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO22 is selected when GPIO6 is low during reset.

The PGPIO22 signal is configured as an input after reset.

PGPIO22

I/O/Z

O/Z

EMIF control pin. EMIF.AWE/SWE/SDWE is selected when GPIO6 is high during reset.

TheEMIF.AWE/SWE/SDWEsignal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

EMIF.AWE/

SWE/SDWE

The EMIF.AWE/SWE/SDWE signal serves three different functions when used by the

EMIF: asynchronous memory write-enable (EMIF.AWE), synchronous memory

write-enable (EMIF.SWE), and SDRAM write-enable (EMIF.SDWE).

The C3 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO23 or external memory interface control signal

EMIF.ARDY. The function of the C3 pin is determined by the state of the GPIO6 pin during

reset. The C3 pin is set to PGPIO23 if GPIO6 is low during reset. The C3 pin is set to

EMIF.ARDY if GPIO6 is high during reset. The function of the C3 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

C3

I/O/Z

I

Parallel general-purpose I/O. PGPIO23 is selected when GPIO6 is low during reset.

The PGPIO23 signal is configured as an input after reset.

F, G, H,

J

PGPIO23

EMIF data ready pin. EMIF.ARDY is selected when GPIO6 is high during reset.

The EMIF.ARDY signal indicates that an external device is ready for a bus transaction to

be completed. If the device is not ready (EMIF.ARDY is low), the processor extends the

memory access by one cycle and checks EMIF.ARDY again. An internal pullup is

includedto disable this feature if not used. The internal pullup can be disabled through the

External Bus Control Register (XBCR).

EMIF.ARDY

The C4 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO24 or external memory interface control signal

EMIF.CE0. The function of the C4 pin is determined by the state of the GPIO6 pin during

reset. The C4 pin is set to PGPIO24 if GPIO6 is low during reset. The C4 pin is set to

EMIF.CE0 if GPIO6 is high during reset. The function of the C4 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

C4

I/O/Z

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO24 is selected when GPIO6 is low during reset.

The PGPIO24 signal is configured as an input after reset.

PGPIO24

EMIF.CE0

I/O/Z

O/Z

EMIF chip-select for memory space CE0. EMIF.CE0 is selected when GPIO6 is high

during reset. The EMIF.CE0 signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

10

SPRS166D

April 2001 – Revised June 2003

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

Parallel Port — Control Pins (Continued)

The C5 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO25 or external memory interface control signal

EMIF.CE1. The function of the C5 pin is determined by the state of the GPIO6 pin during

reset. The C5 pin is set to PGPIO25 if GPIO6 is low during reset. The C5 pin is set to

EMIF.CE1 if GPIO6 is high during reset. The function of the C5 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

C5

I/O/Z

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO25 is selected when GPIO6 is low during reset.

PGPIO25

I/O/Z

O/Z

The PGPIO25 signal is configured as an input after reset.

EMIF chip-select for memory space CE1. EMIF.CE1 is selected when GPIO6 is high

during reset. The EMIF.CE1 signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

EMIF.CE1

The C6 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO26 or external memory interface control signal

EMIF.CE2. The function of the C6 pin is determined by the state of the GPIO6 pin during

reset. The C6 pin is set to PGPIO26 if GPIO6 is low during reset. The C6 pin is set to

EMIF.CE2 if GPIO6 is high during reset. The function of the C6 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

C6

I/O/Z

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO26 is selected when GPIO6 is low during reset.

PGPIO26

EMIF.CE2

I/O/Z

O/Z

The PGPIO26 signal is configured as an input after reset.

EMIF chip-select for memory space CE2. EMIF.CE2 is selected when GPIO6 is high

during reset. The EMIF.CE2 signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

The C7 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO27 or external memory interface control signal

EMIF.CE3. The function of the C7 pin is determined by the state of the GPIO6 pin during

reset. The C7 pin is set to PGPIO27 if GPIO6 is low during reset. The C7 pin is set to

EMIF.CE3 if GPIO6 is high during reset. The function of the C7 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

C7

I/O/Z

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO27 is selected when GPIO6 is low during reset.

PGPIO27

EMIF.CE3

I/O/Z

O/Z

The PGPIO27 signal is configured as an input after reset.

EMIF chip-select for memory space CE3. EMIF.CE3 is selected when GPIO6 is high

during reset. The EMIF.CE3 signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

11

April 2001 – Revised June 2003

SPRS166D

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

Parallel Port — Control Pins (Continued)

The C8 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO28 or external memory interface control signal

EMIF.BE0. The function of the C8 pin is determined by the state of the GPIO6 pin during

reset. The C8 pin is set to PGPIO28 if GPIO6 is low during reset. The C8 pin is set to

EMIF.BE0 if GPIO6 is high during reset. The function of the C8 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

C8

I/O/Z

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO28 is selected when GPIO6 is low during reset.

PGPIO28

I/O/Z

O/Z

The PGPIO28 signal is configured as an input after reset.

EMIFbyte-enable0control. EMIF.BE0isselectedwhenGPIO6ishighduringreset. The

EMIF.BE0 signal is in a high-impedance state during reset and is set to output after reset

with an output value of 1.

EMIF.BE0

The C9 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO29 or external memory interface control signal

EMIF.BE1. The function of the C9 pin is determined by the state of the GPIO6 pin during

reset. The C9 pin is set to PGPIO29 if GPIO6 is low during reset. The C9 pin is set to

EMIF.BE1 if GPIO6 is high during reset. The function of the C9 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

C9

I/O/Z

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO29 is selected when GPIO6 is low during reset.

PGPIO29

EMIF.BE1

I/O/Z

O/Z

The PGPIO29 signal is configured as an input after reset.

EMIFbyte-enable1control. EMIF.BE1isselectedwhenGPIO6ishighduringreset. The

EMIF.BE1 signal is in a high-impedance state during reset and is set to output after reset

with an output value of 1.

The C10 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO30 or external memory interface control signal

EMIF.BE2. The function of the C10 pin is determined by the state of the GPIO6 pin during

reset. The C10 pin is set to PGPIO30 if GPIO6 is low during reset. The C10 pin is set to

EMIF.BE2 if GPIO6 is high during reset. The function of the C10 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

C10

I/O/Z

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO30 is selected when GPIO6 is low during reset.

PGPIO30

EMIF.BE2

I/O/Z

O/Z

The PGPIO30 signal is configured as an input after reset.

EMIFbyte-enable2control. EMIF.BE2isselectedwhenGPIO6ishighduringreset. The

EMIF.BE2 signal is in a high-impedance state during reset and is set to output after reset

with an output value of 1.

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

12

SPRS166D

April 2001 – Revised June 2003

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

Parallel Port — Control Pins (Continued)

The C11 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO31 or external memory interface control signal

EMIF.BE3. The function of the C11 pin is determined by the state of the GPIO6 pin during

reset. The C11 pin is set to PGPIO31 if GPIO6 is low during reset. The C11 pin is set to

EMIF.BE3 if GPIO6 is high during reset. The function of the C11 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

C11

I/O/Z

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO31 is selected when GPIO6 is low during reset.

PGPIO31

I/O/Z

O/Z

The PGPIO31 signal is configured as an input after reset.

EMIFbyte-enable3control. EMIF.BE3isselectedwhenGPIO6ishighduringreset. The

EMIF.BE3 signal is in a high-impedance state during reset and is set to output after reset

with an output value of 1.

EMIF.BE3

The C12 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO32 or external memory interface control signal

EMIF.SDCKE. The function of the C12 pin is determined by the state of the GPIO6 pin

during reset. The C12 pin is set to PGPIO32 if GPIO6 is low during reset. The C12 pin is

set to EMIF.SDCKE if GPIO6 is high during reset. The function of the C12 pin will be set

once the device is taken out of reset (RESET pin transitions from a low to high state).

C12

I/O/Z

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO32 is selected when GPIO6 is low during reset.

PGPIO32

I/O/Z

O/Z

The PGPIO32 signal is configured as an input after reset.

EMIFSDRAM clock-enable. EMIF.SDCKE is selected when GPIO6 is high during reset.

The EMIF.SDCKE signal is in a high-impedance state during reset and is set to output

after reset with an output value of 1.

EMIF.SDCKE

The C13 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO33 or external memory interface control signal

EMIF.SOE3. The function of the C13 pin is determined by the state of the GPIO6 pin

during reset. The C13 pin is set to PGPIO33 if GPIO6 is low during reset. The C13 pin is

set to EMIF.SOE3 if GPIO6 is high during reset. The function of the C13 pin will be set

once the device is taken out of reset (RESET pin transitions from a low to high state).

C13

I/O/Z

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO33 is selected when GPIO6 is low during reset.

PGPIO33

I/O/Z

O/Z

The PGPIO33 signal is configured as an input after reset.

EMIF synchronous memory output-enable for CE3. EMIF.SOE3 is selected when

GPIO6 is high during reset. The EMIF.SOE3 signal is in a high-impedance state during

reset and is set to output after reset with an output value of 1.

EMIF.SOE3

The EMIF.SOE3 is intended for glueless FIFO interface.

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

13

April 2001 – Revised June 2003

SPRS166D

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Parallel Port — Control Pins (Continued)

Function

†

The C14 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO34 or external memory interface control signal

EMIF.HOLD. The function of the C14 pin is determined by the state of the GPIO6 pin

during reset. The C14 pin is set to PGPIO34 if GPIO6 is low during reset. The C14 pin is

set to EMIF.HOLD if GPIO6 is high during reset. The function of the C14 pin will be set

once the device is taken out of reset (RESET pin transitions from a low to high state).

C14

I/O/Z

F, G, H,

J, M

Parallel general-purpose I/O. PGPIO34 is selected when GPIO6 is low during reset.

PGPIO34

I/O/Z

I

The PGPIO34 signal is configured as an input after reset.

EMIF hold request. EMIF.HOLD is selected when GPIO6 is high during reset.

EMIF.HOLD

EMIF.HOLD is asserted by an external host to request control of the address, data, and

control signals.

The C15 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO35 or external memory interface control signal

EMIF.HOLDA. The function of the C15 pin is determined by the state of the GPIO6 pin

during reset. The C15 pin is set to PGPIO35 if GPIO6 is low during reset. The C15 pin is

set to EMIF.HOLDA if GPIO6 is high during reset. The function of the C15 pin will be set

once the device is taken out of reset (RESET pin transitions from a low to high state).

C15

I/O/Z

O/Z

Parallel general-purpose I/O. PGPIO35 is selected when GPIO6 is low during reset.

C, D, F,

G, H, M

PGPIO35

The PGPIO35 signal is configured as an input after reset.

EMIF hold acknowledge. EMIF.HOLDA is selected when GPIO6 is high during reset.

The EMIF.HOLDA signal is in a high-impedance state during reset and is set to output

after reset with an output value of ‘1’

EMIF.HOLDA

EMIF.HOLDA is asserted by the DSP to indicate that the DSP is in the HOLD state and

that the EMIF address, data, and control signals are in a high-impedance state, allowing

the external memory interface to be accessed by other devices.

EMIF — Clock Pins

External EMIF input clock. ECLKIN is selected as the input clock to the EMIF when

EMIFCLKS is high.

ECLKIN

I

C, L

F, M

EMIF output clock. ECLKOUT1 drives the EMIF input clock by default. ECLKOUT1 can

be held low or set to a high-impedance state through the EMIF Global Control Register 1

(EGCR1). The ECLKOUT1 pin is in a high-impedance state during reset and is enabled

(toggling) after reset.

ECLKOUT1

O/Z

EMIFoutputclock. ECLKOUT2canbeenabledtodrivetheEMIFinputclockdividedbya

factor of 1, 2, or 4 through the EMIF Global Control Register 2 (EGCR2). ECLKOUT2 can

be held low or set to a high-impedance state through the EGCR2 register. The

ECLKOUT2pinisenabled(toggling)duringandafterresetwithaclockfrequencyequalto

the EMIF input clock divided by 4.

ECLKOUT2

EMIFCLKS

O/Z

I

F

EMIF input clock source select. The clock source for the EMIF is determined by the

state of the EMIFCLKS pin. The EMIF uses an internal clock (SYSCLK3) if EMIFCLKS is

low. ECLKIN is used as the clock source if EMIFCLKS is high.

C, L

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

14

SPRS166D

April 2001 – Revised June 2003

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

Host Port — Data Bus

The HD[7:0] pins of the Host Port serve one of two functions: parallel general-purpose

input/output (PGPIO) signals PGPIO[43:36] or host-port interface (HPI) data bus signals

HPI.HD[7:0]. The function of the HD[7:0] pins is determined by the state of the GPIO6 pin

during reset. The HD[7:0] pins are set to PGPIO[43:36] if GPIO6 is low during reset. The

HD[7:0] pins are set to HPI.HD[7:0] if GPIO6 is high during reset. The function of the

HD[7:0]pins will be set once the device is taken out of reset (RESET pin transitions from a

low to high state).

HD[7:0]

I/O/Z

The HD[7:0] bus includes bus holders to reduce the static power dissipation caused by

floating, unused pins. The bus holders also eliminate the need for external bias resistors

onunusedpins. Whenthebusgoesintoahigh-impedancestate, thebusholderskeepthe

address bus at the logic level that was most recently driven. The bus holders are enabled

at reset and can be enabled/disabled through the External Bus Control Register (XBCR).

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO[43:36] is selected when GPIO6 is low during

reset. The PGPIO[43:36] signals are configured as inputs after reset.

PGPIO[43:36]

HPI.HD[7:0]

I/O/Z

O/Z

Host data bus. HPI.HD[7:0] is selected when GPIO6 is high during reset. The

HPI.HD[7:0] signals are configured as inputs after reset.

The HPI will operate in mulitplexed mode when GPIO6 is high during reset. In multiplexed

mode, an 8-bit data bus (HPI.HD[7:0]) carries both address and data. Each host cycle on

the bus consists of two consecutive 8-bit transfers.

Host Port — Control Pins

The HC0 pin of the Host Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO44 or host-port interface (HPI) signal HPI.HAS. The

function of the HC0 pin is determined by the state of the GPIO6 pin during reset. The HC0

pinissettoPGPIO44ifGPIO6islowduringreset. TheHC0pinissettoHPI.HASifGPIO6

is high during reset. The function of the HC0 pin will be set once the device is taken out of

reset (RESET pin transitions from a low to high state).

HC0

I/O/Z

C, F, G,

H, J, M

Parallel general-purpose I/O. PGPIO44 is selected when GPIO6 is low during reset.

The PGPIO44 signal is configured as an input after reset.

PGPIO44

HPI.HAS

I/O/Z

I

Host address strobe. HPI.HAS is selected when GPIO6 is high during reset. The

HPI.HAS signal is configured as an input after reset.

HostswithmultiplexedaddressanddatapinsmayrequireHPI.HAStolatchtheaddressin

the HPIA register. HPI.HAS is only available when the HPI is operating in multiplexed

mode.

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

15

April 2001 – Revised June 2003

SPRS166D

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

Host Port — Control Pins (Continued)

The HC1 pin of the Host Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO45 or host-port interface (HPI) signal HPI.HBIL. The

function of the HC1 pin is determined by the state of the GPIO6 pin during reset. The HC1

pinissettoPGPIO45ifGPIO6islowduringreset. TheHC1pinissettoHPI.HBILifGPIO6

is high during reset. The function of the HC1 pin will be set once the device is taken out of

reset (RESET pin transitions from a low to high state).

HC1

I/O/Z

F, G, H,

K, M

Parallel general-purpose I/O. PGPIO45 is selected when GPIO6 is low during reset.

The PGPIO45 signal is configured as an input after reset.

PGPIO45

I/O/Z

I

Host byte identification. HPI.HBIL is selected when GPIO6 is high during reset. The

HPI.HBIL signal is configured as an input after reset.

HPI.HBIL

In multiplexed mode, the host must use HPI.HBIL to identify the first and second bytes of

the host cycle.

HPI Pins

HPI access control pins. The four binary states of the HCNTL0 and HCNTL1 pins

determine which HPI register is being accessed by the host (HPIC, HPID with

autoincrementing, HPIA, or HPID). The HCNTL0 and HCNTL1 pins are configured as

inputs after reset.

HCNTL0

HCNTL1

I/O/Z

F, J, M

C, F, J, HPI chip-select. HCS must be low for the HPI to be selected by the host. The HCS pin is

HCS

I/O/Z

M

configured as an input after reset.

Host read- or write-select. HR/W indicates whether the current access is to be a read or

HR/W

F, J, M

write operation. The HR/W pin is configured as an input after reset.

HDS1

HDS2

Host data strobe pins. The HDS1 and HDS2 pins are used for strobing data in and out of

I

C, J

the HPI. The HDS1 and HDS2 pins are configured as inputs after reset.

Hostready(fromDSPtohost). TheHRDYpininformsthehostwhentheHPIisreadyfor

HRDY

HINT

O/Z

F, J, M the next transfer. The HRDY pin is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

Hostinterrupt(fromDSPtohost). TheHINTpinisusedbytheDSPtointerruptthehost.

F, J, M The HINT signal is in a high-impedance state during reset and is set to output after reset

with an output value of 1.

O/Z

HPI enable. The HPIENA pin must be driven high to enable the HPI for operation. If the

HPIENA pin is low, the HPI will be completely disabled and all HPI output pins will be in a

HPIENA

I

C

high-impedance state.

If the HPI is not needed, the HPIENA pin must be pulled low.

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

16

SPRS166D

April 2001 – Revised June 2003

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

Interrupt and Reset Pins

Maskable external interrupts. INT0–INT3 are maskable interrupts. They are enabled

through the Interrupt Enable Registers (IER0 and IER1). All maskable interrupts are

globally enabled/disabled through the Interrupt Mode bit (INTM in ST1_55). INT0–INT3

can be polled and reset via the Interrupt Flag Registers (IFR0 and IFR1). All interrupts are

prioritized as shown in Table 3–77, Interrupt Table.

INT[3:0]

I

C, L

Non-maskableexternalinterruptorWatchdogTimeroutput. Thefunctionofthispinis

controlled by the Timer Signal Selection Register (TSSR). By default, the NMI/WDTOUT

pin has the function of the NMI signal.

C, F, J,

M

NMI/WDTOUT

I/O/Z

NMI is an external interrupt that cannot be masked by the Interrupt Enable Registers

(IER0 and IER1). When NMI is activated, the interrupt is always performed.

WDTOUT serves as an input and output pin for the Watchdog Timer.

Interrupt acknowledge. IACK indicates the receipt of an interrupt and that the program

counter is fetching the interrupt vector location designated on the address bus. The IACK

pin is set to a value of ‘1’ during reset.

IACK

O/Z

I

F, M

C, L

Device reset. RESET causes the digital signal processor (DSP) to terminate current

programexecution. When RESET is brought to a high level, program execution begins by

fetching the reset interrupt service vector at the reset vector address FFFF00h

(IVPD:FFFFh). RESET affects various registers and status bits.

RESET

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

17

April 2001 – Revised June 2003

SPRS166D

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

General-Purpose I/O Pins

General-purpose configurable inputs/outputs. GPIO[7:0] can be individually

configuredasinputsoroutputsviatheGPIODirectionRegister(IODIR). Datacanberead

frominputsorwrittentooutputsviatheGPIODataRegister(IODATA). TheGPIOpinsare

configured as inputs after reset.

Boot mode selection signals. GPIO[2:0]/BOOTM[2:0] are sampled following reset to

configure the boot mode for the DSP. After the boot is completed, these pins can be used

as general-purpose inputs/outputs.

The GPIO4 pin is also used as an output for handshaking purposes on some of the boot

modes. Although this pin is not involved in boot mode selection, users should be aware

that this pin will become active as an output during the bootload process and should

design accordingly. After the bootload process is complete, the loaded application may

change the function of the GPIO4 pin.

Multiplexed general-purpose input/output pins. The GPIO3 signal is multiplexed with

the CLKX2 signal through the SP0 pin. The function of the SP0 pin is determined by the

state of the GPIO7 pin during reset. The SP0 pin is set to GPIO3 if GPIO7 is low during

reset. The SP0 pin is set to CLKX2 if GPIO7 is high during reset. The function of the SP0

pin will be set once the device is taken out of reset (RESET pin transitions from a low to

high state).

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

TheGPIO5signalismultiplexedwiththeFSX2signalthroughtheSP2pin. Thefunctionof

the SP2 pin is determined by the state of the GPIO7 pin during reset. The SP2 pin is set to

GPIO5 if GPIO7 is low during reset. The SP2 pin is set to FSX2 if GPIO7 is high during

reset. The function of the SP2 pin will be set once the device is taken out of reset (RESET

pin transitions from a low to high state).

F, G, H,

M

I/O/Z

Input clock source selection. The CLKMD0 bit of the Clock Mode Control Register

(CLKMD)determineswhichclock, eitherOSCOUTorX2/CLKIN, isusedasaninputclock

source to the DSP. If GPIO4 is low at reset, the CLKMD0 bit of the Clock Mode Control

Register (CLKMD) will be set to ‘0’ and the internal oscillator and the external crystal will

generate an input clock (OSCOUT) for the DSP. If GPIO4 is high, the CLKMD0 bit will be

set to ‘1’ and the input clock will be taken directly from the X2/CLKIN pin.

GPIO2/BOOTM2

GPIO1/BOOTM1

GPIO0/BOOTM0

An external crystal or ceramic resonator must be attached to the X1 and X2/CLKIN pins

when the internal oscillator is used to generate a clock to the DSP. Otherwise, when the

oscillator is not used to generate the input clock for the DSP, an externally generated

3.3-V clock must be applied to the X2/CLKIN pin and the X1 pin must be left unconnected.

Functionselectionformultiplexedpins. TheGPIO6pinisusedtoselectthefunctionof

the multiplexed signals in the Parallel Port and the Host Port. The EMIF will be disabled

and the HPI will operate in non-multiplexed mode when the GPIO6 pin is low during reset.

The EMIF will be enabled and the HPI will operate in multiplexed mode when the GPIO6

pin is high during reset. The function of the multiplexed signals will be set once the device

is taken out of reset (RESET pin transitions from a low to high state).

TheGPIO7pinisusedtoselectthefunctionofthemultiplexedsignalsofSerialPort2. The

UART will be enabled and McBSP2 will be disabled when GPIO7 is low during reset.

McBSP2 will be enabled and the UART will be disalbed when GPIO7 is high during reset.

The function of the multiplexed signals will be set once the device is taken out of reset

(RESET pin transitions from a low to high state).

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

18

SPRS166D

April 2001 – Revised June 2003

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

General-Purpose I/O Pins (Continued)

External output (latchedsoftware-programmable signal). XF is set high by the BSET XF

instruction, set low by BCLR XF instruction, or by loading ST1. XF is used for signaling

other processors in multiprocessor configurations or used as a general-purpose output

pin. The XF pin is set to a value of ‘1’ during reset.

XF

O/Z

F

Oscillator/Clock Pins

Clock output. CLKOUT can be set to reflect the clock of the Fast Peripherals Clock

Group, Slow Peripherals Clock Group, and the External Memory Interface Clock Group.

TheCLKOUT pin is set to the internal clock SYSCLK1 during and after reset. SYSCLK1 is

set equal to a divided-by-four CLKIN or OSCOUT (depending on the state of the GPIO4

pin) during and after reset. SYSCLK1 is used to clock the Fast Peripheral Clock Group.

CLKOUT

F

Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as

X2/CLKIN

X1

I

the clock input.

Output pin from the internal oscillator for the crystal. If the internal oscillator is not

O

used, X1 should be left unconnected.

Multichannel Buffered Serial Port Pins (McBSP0 and McBSP1)

C, F, G,

CLKR0

DR0

I/O/Z

Receive clock input of McBSP0. The CLKR0 pin is configured as an input after reset.

Serial data receive input of McBSP0

H, M

I

L, G

F, G, H, Frame synchronization pulse for receive input of McBSP0. The FSR0 pin is

FSR0

I/O/Z

M

configured as an input after reset.

C, F, G,

H, M

CLKX0

DX0

I/O/Z

O/Z

Transmit clock of McBSP0. The CLKX0 pin is configured as an input after reset.

Serial data transmit output of McBSP0. The DX0 pin is in a high-impedance state

F, H, M

during and after reset.

F, G, H, Frame synchronization pulse for transmit output of McBSP0. The FSX0 pin is

FSX0

I/O/Z

M

configured as an input after reset.

C, G,

H, M

CLKR1

DR1

I/O/Z

I

Receive clock input of McBSP1. The CLKR1 pin is configured as an input after reset.

Serial data receive input of McBSP1

L, G

F, G, H, Frame synchronization pulse for receive input of McBSP1. The FSR1 pin is

FSR1

I/O/Z

M

configured as an input after reset.

Serial data transmit output of McBSP1. The DX1 pin is in a high-impedance state

DX1

O/Z

F, H, M

during and after reset.

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

19

April 2001 – Revised June 2003

SPRS166D

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

Multichannel Buffered Serial Port Pins (McBSP0 and McBSP1) (Continued)

C, F, G,

CLKX1

FSX1

I/O/Z

Transmit clock of McBSP1. The CLKX1 pin is configured as an input after reset.

H, M

F, G, H, Frame synchronization pulse for transmit output of McBSP1. The FSX1 pin is

M

configured as an input after reset.

Serial Port 2 (McBSP2/UART) Pins

McBSP2 data receive input

DR2

DX2

I

L, G

McBSP2 data transmit output. The DX2 pin is in a high-impedance state during and

O/Z

F, H, M

after reset.

TheSP0pinofSerialPort2servesoneoftwofunctions:GPIO3orCLKX2. Thefunctionof

the SP0 pin is determined by the state of the GPIO7 pin during reset. The SP0 pin is set to

SP0

I/O/Z

C, F, M GPIO3 if GPIO7 is low during reset. The SP0 pin is set to CLKX2 if GPIO7 is high during

reset. The function of the SP0 pin will be set once the device is taken out of reset (RESET

pin transitions from a low to high state).

GPIO3. GPIO3isselectedifGPIO7islowduringreset. TheGPIO3signalisconfiguredas

input after reset.

GPIO3

O

G, H

McBSP2 transmit clock. CLKX2 is selected if GPIO7 is high during reset. The CLKX2

CLKX2

I/O

G, H

signal is configured as input after reset.

The SP1 pin of Serial Port 2 serves one of two functions: UART.TX or CLKR2. The

function of the SP1 pin is determined by the state of the GPIO7 pin during reset. The SP1

C, F, M pinissettoUART.TXifGPIO7islowduringreset. TheSP1pinissettoCLKR2ifGPIO7is

high during reset. The function of the SP1 pin will be set once the device is taken out of

reset (RESET pin transitions from a low to high state).

SP1

I/O/Z

UART transmit data output. UART.TX is selected if GPIO7 is low during reset. The

UART.TX signal outputs a value of 1 during and after reset.

UART.TX

CLKR2

O

McBSP2 receive clock. CLKR2 is selected if GPIO7 is high during reset. The CLKR2

I/O

G, H

signal is configured as input after reset.

The SP2 pin of Serial Port 2 serves one of two functions: GPIO5 or FSX2. The function of

the SP2 pin is determined by the state of the GPIO7 pin during reset. The SP2 pin is set to

SP2

I/O/Z

F, M

GPIO5 if GPIO7 is low during reset. The SP2 pin is set to FSX2 if GPIO7 is high during

reset. The function of the SP2 pin will be set once the device is taken out of reset (RESET

pin transitions from a low to high state).

GPIO5. GPIO5isselectedifGPIO7islowduringreset. TheGPIO5signalisconfiguredas

input after reset.

GPIO5

FSX2

I/O/Z

G, H

FramesynchronizationpulsefortransmitterofMcBSP2. FSX2isselectedifGPIO7is

high during reset. The FSX2 signal is configured as input after reset.

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

20

SPRS166D

April 2001 – Revised June 2003

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

Serial Port 2 (McBSP2/UART) Pins (Continued)

The SP3 pin of Serial Port 2 serves one of two functions: UART.RX or FSR2. The function

of the SP3 pin is determined by the state of the GPIO7 pin during reset. The SP3 pin is set

to UART.RX if GPIO7 is low during reset. The SP3 pin is set to FSR2 if GPIO7 is high

during reset. The function of the SP3 pin will be set once the device is taken out of reset

(RESET pin transitions from a low to high state).

SP3

I/O/Z

F, M

G, H

UART.RX

FSR2

I

UART receive data input. UART.RX is selected if GPIO7 is low during reset.

Frame synchronization pulse for receiver of McBSP2. FSR2 is selected if GPIO7 is

high during reset. The FSR2 signal is configured as input after reset.

I/O/Z

2

I C Pins

2

SCL

SDA

I/O/Z

C, F, M I C clock bidirectional port. (Open collector I/O)

2

C, F, M I C data bidirectional port. (Open collector I/O)

Timer Pins

Input/OutputpinforTimer0. TheTIM0pincanbeconfiguredasanoutputoraninputvia

the Timer Signal Selection Register (TSSR). When configured as an output, the TIM0 pin

can signal a pulse or a change of state when the Timer 0 count matches its period. When

configured as an input, the TIM0 pin can be used to provide the clock source for Timer 0

(external clock source mode) or it can be used to start/stop the timer from counting (clock

F, G, H,

TIM0

TIM1

I/O/Z

M

gating mode). This pin can also be used as general-purpose I/O. The TIM0 pin is

configured as an input after reset.

Input/OutputpinforTimer1. TheTIM1pincanbeconfiguredasanoutputoraninputvia

the Timer Signal Selection Register (TSSR). When configured as an output, the TIM1 pin

can signal a pulse or a change of state when the Timer 1 count matches its period. When

configured as an input, the TIM1 pin can be used to provide the clock source for Timer 1

F, G, H,

M

(external clock source mode) or it can be used to start/stop the timer from counting (clock

gating mode). This pin can also be used as general-purpose I/O. The TIM1 pin is

configured as an input after reset.

Supply Pins

V

S

Digital Ground. Dedicated ground for the device.

SS

CV

Digital Power, + V . Dedicated power supply for the core CPU.

DD

PV

Digital Power, + V . Dedicated power supply for the PLL module.

DD

PSENSE

DV

For test purposes only. Must be connected to ground.

S

Digital Power, + V . Dedicated power supply for the I/O pins.

DD

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

21

April 2001 – Revised June 2003

SPRS166D

Introduction

Table 2–3. Signal Descriptions (Continued)

Name

Multiplexed

Signal Name

Type

‡

Other

Function

†

Test Pins

IEEE standard 1149.1testclock. TCK is normally a free-running clock signal with a 50%

duty cycle. The changes on test access port (TAP) of input signals TMS and TDI are

clocked into the TAP controller, instruction register, or selected test data register on the

rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of

TCK.

TCK

I

C, J

IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into

TDI

I

O/Z

I

J

the selected register (instruction or data) on a rising edge of TCK.

IEEEstandard1149.1testdataoutput.Thecontentsoftheselectedregister(instruction

or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance

state except when the scanning of data is in progress.

TDO

TMS

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial

J

control input is clocked into the TAP controller on the rising edge of TCK.

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1

scan system control of the operations of the device. If TRST is not connected or driven

low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are

ignored. Pin has an internal pulldown device.

TRST

EMU0

I

C, L, K

Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF

condition.WhenTRSTisdrivenhigh, EMU0isusedasaninterrupttoorfromtheemulator

system and is defined as I/O by way of the IEEE standard 1149.1 scan system.

I/O/Z

J

The EMU0 and EMU1/OFF pins must be pulled up when an emulator is not connected.

Internal pullups have been included for the purpose. If the user chooses to disable these

pullups through the XBCR, external pullup resistors must be added to these two pins.

Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as

an interrupt to or from the emulator system and is defined as I/O by way of IEEE standard

1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The

EMU1/OFF signal, when active (low), puts all output drivers into the high-impedance

state. Note that OFF is used exclusively for testing and emulation purposes (not for

multiprocessing applications). Therefore, for the OFF condition, the following apply:

TRST = low,

EMU1/OFF

I/O/Z

J

EMU0 = high,

EMU1/OFF = low

The EMU0 and EMU1/OFF pins must be pulled up when an emulator is not connected.

Internal pullups have been included for the purpose. If the user chooses to disable these

pullups through the XBCR, external pullup resistors must be added to these two pins.

†

‡

I = Input, O = Output, S = Supply, Z = High impedance

Other Pin Characteristics:

A – Internal pullup [always enabled]

B – Internal pulldown [always enabled]

C – Hysteresis input

D – Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E – Pin is high impedance in HOLD mode (due to HOLD pin).

F – Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G – Pin can be configured as a general-purpose input.

H – Pin can be configured as a general-purpose output.

J – Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K – Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L – Fail-safe pin

M – Pin is in high-impedance during reset (RESET pin is low)

22

SPRS166D

April 2001 – Revised June 2003

Functional Overview

3

Functional Overview

The following functional overview is based on the block diagram in Figure 3–1.

P, B, C, D, E, and F Buses and Control Signals

55x Core

32K Dual-Access RAM

Program/Data

16K ROM

Program/Data

Instruction

Cache

[2:0]

TCK

TMS

GPIO[2:0]

GPIO4

Peripheral Bus

4

[7:6]

3

TDI

GPIO[7:6]

Emulation

Control

GPIO

TDO

DMA Bus

5

TRST

EMU0

EMU1/OFF

FSX0

DX0

Transmit

Receive

ECLKIN

ECLKOUT1

ECLKOUT2

EMIFCLKS

CLKX0

FSR0

DR0

External

Memory

Interface

McBSP0

McBSP1

McBSP2

CLKR0

A[21:18]

FSX1

DX1

D[31:16]

C0–C15

A[17:2]

D[15:0]

Transmit

Receive

CLKX1

FSR1

DR1

A[21:18]

D[31:16]

C0–C15

A[17:2]

D[15:0]

CLKR1

[3:0]

[19:4]

[35:20]

[43:36]

44

DX2

DR2

PGPIO

45

Rx

Tx

HA[15:0]

HD[15:0]

UART

†

SP0

SP1

SP2

SP3

HAS

Serial

Port 2

MUX

HBIL

HD[7:0]

HC0

Host

Port

MUX

HPI

HC1

Module

DMA

Controller

6 Channels

HCNTL0

HCNTL1

HCS

SDL

SDA

I2C

HR/W

Timer 0

Timer 1

HDS1

TIM0

TIM1

HDS2

HRDY

HINT

HPIENA

Interrupt

Logic

WDTimer

WDTOUT

Muxing

Logic

NMI

NMI/WDTOUT

INT3

X1

RESET

APLL

CLKIN

CLKOUT

INT[2:0]

†

HD[15:8] are not used when the HPI is operated in multiplexed mode.

Figure 3–1. Block Diagram of the TMS320VC5502

23

April 2001 – Revised June 2003

SPRS166D

Functional Overview

3.1 Memory

The 5502 supports a unified memory map (program and data accesses are made to thesamephysicalspace).

The total on-chip memory is 48K words (32K 16-bit words of RAM and 16K 16-bit words of ROM).

3.1.1 On-Chip ROM

TMS320VC5502 incorporates 16K x16-bit of on-chip, one-wait-state maskable ROM that can be mapped into

program memory space. The on-chip ROM is located at the byte address range FF8000h–FFFFFFh when

MPNMC = 0 at reset. When MPNMC = 1 at reset, the on-chip ROM is disabled and not present in the memory

map, and byte address range FF8000h–FFFFFFh is directed to external memory space. MPNMC is a bit

located in the ST3 status register, and its status is determined by the logic level on the BOOTM[2:0] pins when

sampled at reset. If BOOTM[2:0] are set to 00h or 04h at reset, the MPNMC bit is set to 1 and the on-chip ROM

is disabled; otherwise, the MPNMC bit is cleared to 0 and the on-chip ROM is enabled. These pins are not

sampled again until the next hardware reset. The software reset instruction does not affect the MPNMC bit.

Software can be used to set or clear the MPNMC bit.

The ROM can be accessed by the program bus (P) and the two read data buses (C and D). The on-chip ROM

is a two-cycle-per-word memory access, except for the first word access, which requires four cycles.

Thestandardon-chipROMcontainsabootloaderwhichprovidesavarietyofmethodstoloadapplicationcode

automaticallyafterpowerupora hardware reset. For more information, see Section 3.1.5, Boot Configuration.

A vector table associated with the bootloader is also contained in the ROM. A boot mode branch table is

included in the ROM which contains hard-coded jumps to the beginning of each boot mode code section in

the bootloader.

A sine look-up table is provided containing 256 values (crossing 360 degrees) expressed in Q15 format.

The standard on-chip ROM layout is shown in Table 3–1.

Table 3–1. On-Chip ROM Layout

STARTING BYTE ADDRESS

FF_8000h

CONTENTS

Bootloader Program

FF_ECAEh

Bootloader Revision Number

Boot Mode Branch Table

Sine Table

FF_ECB0h

FF_ED00h

FF_EF00h

Reserved

FF_FF00h

Interrupt Vector Table

24

SPRS166D

April 2001 – Revised June 2003

Functional Overview

3.1.2 On-Chip Dual-Access RAM (DARAM)

TMS320VC5502 features 32K x 16-bit (64K bytes) of on-chip dual-access RAM. This memory enhances

system performance, since the C55x CPU can access a DARAM block twice per machine cycle. The DARAM

is composed of 8 blocks of 4K x 16-bit each (see Table 3–2). Each block in the DARAM can support two reads

in one cycle, a read and a write in one cycle, or two writes in one cycle. The dual-access RAM is located in

the (byte) address range 000000h–00FFFFh, it can be accessed by the program, data and DMA buses. The

HPI has NO access to the DARAM block when device is in reset.

Table 3–2. DARAM Blocks

BYTE ADDRESS RANGE

000000h – 001FFFh

002000h – 003FFFh

004000h – 005FFFh

006000h – 007FFFh

008000h – 009FFFh

00A000h – 00BFFFh

00C000h – 00DFFFh

00E000h – 00FFFFh

MEMORY BLOCK

DARAM 0

DARAM 1

DARAM 2

DARAM 3

DARAM 4

DARAM 5

DARAM 6

DARAM 7

3.1.3 Instruction Cache

On the TMS320VC5502, instructions may reside in internal memory or external memory. When instructions

reside in external memory, the I-Cache can improve the overall system performance by buffering the most

recent instructions accessed by the CPU.

The 5502 includes a 16K-byte instruction cache, which consists of a single 2-way cache block. The 2-way

cache uses 2-way associative mapping and holds up to 16K bytes: 512 sets, two lines per set, four 32-bit

words per line. In the 2-way cache, each line is identified by a unique tag. The 2-way cache is updated based

on a least-recently-used algorithm.

Control bits in the CPU status register ST3_55 provide the ability to enable, freeze, and flush the cache.

For more information on the instruction cache, see the TMS320VC5501/5502 DSP Instruction Cache

Reference Guide (literature number SPRU630).

25

April 2001 – Revised June 2003

SPRS166D

Functional Overview

3.1.4 Memory Map

000000h

002000h

000000h

002000h

DARAM0

(8K Bytes)

DARAM0

(8K Bytes)

DARAM1

(8K Bytes)

DARAM1

(8K Bytes)

004000h

006000h

004000h

006000h

008000h

DARAM2

(8K Bytes)

DARAM2

(8K Bytes)

DARAM3

(8K Bytes)

DARAM3

(8K Bytes)

008000h

00A000h

DARAM4

(8K Bytes)

DARAM4

(8K Bytes)

00A000h

DARAM5

(8K Bytes)

DARAM5

(8K Bytes)

00C000h

00E000h

00C000h

00E000h

DARAM6

(8K Bytes)

DARAM6

(8K Bytes)

DARAM7

(8K Bytes)

DARAM7

(8K Bytes)

010000h

400000h

010000h

400000h

External CE0 Space

(4M minus 64K Bytes )

External CE0 Space

(4M minus 64K Bytes )

†

External CE1 Space

(4M Bytes)

External CE1 Space

(4M Bytes)

800000h

C00000h

External CE2 Space

(4M Bytes)

800000h

C00000h

External CE2 Space

(4M Bytes)

External CE3 Space

‡

(4M minus 32K Bytes )

External CE3 Space

(4M Bytes)

FF8000h

ROM

(32K Bytes)

MPNMC = 0

MPNMC = 1

†

‡

The 64K bytes are the on-chip DARAM block.

The 32K bytes are for on-chip ROM block.

Figure 3–2. TMS320VC5502 Memory Map

26

SPRS166D

April 2001 – Revised June 2003

Functional Overview

3.1.5 Boot Configuration

The on-chip bootloader provides a way to transfer application code and tables from an external source to the

on-chip RAM at power up. The 5502 provides several options to download the code to accommodate varying

system requirements. These options include:

•

Host-port interface (HPI) boot, both in multiplexed and non-multiplexed modes

External memory boot (via EMIF) from 16-bit asynchronous memory

Serial port boot (from McBSP0) with 16-bit element length

SPI EPROM boot (from McBSP0) supporting EPROMs with 24-bit addresses

2

I C EPROM boot (from I C) supporting EPROMs larger than 512K bits

UART boot

Direct execution (no boot) from 16- or 32-bit external asynchronous memory

The external pins BOOTM2, BOOTM1, and BOOTM0 select the boot configuration. The values of

BOOTM[2:0] are latched with the rising edge of the RESET input. BOOTM2 is shared with GPIO2, BOOTM1

is shared with GPIO1, and BOOTM0 is shared with GPIO0.

The boot configurations available are summarized in Table 3–3.

Table 3–3. Boot Configuration Selection Via the BOOTM[2:0] Pins

BOOTM[2:0]

000

BOOT PROCESS

Direct execution from 16-bit external asynchronous memory

SPI EPROM boot

001

010

Serial port boot (from McBSP0)

011

External memory boot (via EMIF) from 16-bit asynchronous memory

Direct execution from 32-bit external asynchronous memory

HPI boot

100

101

2

110

I C EPROM boot

111

UART boot

3.2 Peripherals

The 5502 includes the following on-chip peripherals:

†

•

An external memory interface (EMIF)

–

Supporting a 32-bit interface to asynchronous memory, SDRAM, and SBSRAM

†

A host-port interface (HPI)

–

Configurable to 8 bits (multiplexed mode) or 16 bits (non-multiplexed mode)

•

A six-channel direct memory access (DMA) controller

Three multichannel buffered serial ports (McBSPs)

A programmable analog phase-locked loop (APLL) clock generator

General-purpose I/O (GPIO) pins and a dedicated output pin (XF)

†

The 5502 can be configured as follows:

•

32-bit external memory interface with 8-bit (multiplexed) host-port interface

no external memory interface with 16-bit (non-multiplexed) host-port interface

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SPRS166D

Functional Overview

•

Four timers

–

Two 64-bit general-purpose timers

A programmable watchdog timer

A DSP/BIOS timer

2

•

An Inter-integrated Circuit (I C) multi-master and slave interface

A Universal Asynchronous Receiver/Transmitter (UART)

For detailed information on the C55x DSP peripherals, see the following documents:

•

TMS320VC5501/5502 DSP Instruction Cache Reference Guide (literature number SPRU630)

TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618)

TMS320VC5501/5502/5509 DSP Inter-Integrated Circuit (I2C) Module Reference Guide

(literature number SPRU146)

•

TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)

TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide

(literature number SPRU613)

•

TMS320VC5501/5502/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide

(literature number SPRU592)

TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide

(literature number SPRU621)

TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) Reference Guide

(literature number SPRU597)

3.3 Configurable External Ports and Signals

A number of pins on the 5502 have two functions, a feature that allows system designers to choose an

appropriate media interface for his/her application without the need for a large pin-count package. Three

muxes are included in the 5502 to control the configuration of these dual-function pins: the Parallel Port Mux,

the Host Port Mux, and the Serial Port 2 Mux. The state of these muxes is set at reset based on the state of

the GPIO6 and GPIO7 pins. The External Bus Selection Register (XBSR) reflects the configuration of these

muxes after the 5502 comes out of reset.

3.3.1 Parallel Port Mux

The Parallel Port Mux of the 5502 controls the function of 20 address signals (pins A[21:2]), 32 data signals

(pins D[31:0]), and 16 control signals (pins C0 through C15). The Parallel Port Mux supports two different

modes:

•

Full EMIF mode: The EMIF is enabled and its 20 address, 32 data, and 16 control signals are routed to

their corresponding pins on the Parallel Port Mux.

•

Non-multiplexed HPI mode: The HPI is enabled with its 16 address, 16 data, and 9 control signals routed

to their corresponding pins on the Parallel Port Mux. Moreover, 16 control signals, 4 address signals, and

16 data signals of the Parallel Port Mux that are not needed for HPI operation are set to

general-purpose I/O (PGPIO).

The mode of the Parallel Port Mux is determined by the state of the GPIO6 pin at reset. If GPIO6 is low, the

EMIF will be disabled and the HPI will be enabled in non-multiplexed mode: pins A[17:2] are set to

HPI.HA[15:0] and pins D[15:0] are set to HPI.HD[15:0]. All address, data, and control signals in the Parallel

Port Mux not needed by the HPI are set to parallel general-purpose I/O. The Parallel/Host Port Mux Mode bit

field in the External Bus Selection Register (XBSR) will also be set to 0 to reflect the non-multiplexed HPI mode

of the Parallel Port Mux.

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Functional Overview

If GPIO6 is high at reset, the HPI will be enabled in multiplexed mode and the EMIF will be fully enabled: pins

A[21:2] are set to EMIF.A[21:2], pins D[31:0] are set to EMIF[31:0], and pins C[15:0] are set to their

corresponding EMIF operation. The Parallel/Host Port Mux Mode bit field in the XBSR will be set to 1 to reflect

the full EMIF mode of the Parallel Port Mux. Note that in multiplexed mode, the HPI will use the HD[7:0] pins

to strobe in address and data information (see Section 3.7, Host-Port Interface (HPI), for more information on

the operation of the HPI in multiplexed and non-multiplexed modes).

Table 3–4liststheindividualroutingoftheEMIF, PGPIO, andHPIsignalstotheexternalparalleladdress, data,

and control buses.

Table 3–4. TMS320VC5502 Routing of Parallel Port Mux Signals

PARALLEL/HOST PORT MUX MODE = 0

(HPI NON-MULTIPLEX)

PARALLEL/HOST PORT MUX MODE = 1

(FULL EMIF)

Address Bus

HPI.HA[15:0]

PGPIO[3:0]

Data Bus

A[17:2]

EMIF.A[17:2]

EMIF.A[21:18]

A[21:18]

D[15:0]

HPI.HD[15:0]

PGPIO[19:4]

Control Bus

PGPIO20

EMIF.D[15:0]

EMIF.D[31:16]

D[31:16]

C0

C1

EMIF.ARE/SADS/SDCAS/SRE

EMIF.AOE/SOE/SDRAS

EMIF.AWE/SWE/SDWE

EMIF.ARDY

PGPIO21

C2

PGPIO22

C3

PGPIO23

C4

PGPIO24

EMIF.CE0

C5

PGPIO25

EMIF.CE1

C6

PGPIO26

EMIF.CE2

C7

PGPIO27

EMIF.CE3

C8

PGPIO28

EMIF.BE0

C9

PGPIO29

EMIF.BE1

C10

C11

C12

C13

C14

C15

PGPIO30

EMIF.BE2

PGPIO31

EMIF.BE3

PGPIO32

EMIF.SDCKE

EMIF.SOE3

PGPIO33

PGPIO34

EMIF.HOLD

PGPIO35

EMIF.HOLDA

3.3.2 Host Port Mux

The 5502 Host Port Mux controls the function of 8 data signals (pins HD[7:0]) and 2 control signals (pins HC0

and HC1). The Host Port Mux supports two different modes:

•

8-bit multiplexed mode: The HPI’s 8 data and 2 control signals are routed to their corresponding pins

on the Host Port Mux.

•

Parallel general-purpose I/O mode: All pins on the Host Port Mux are routed to PGPIO. The HPI is

enabled to 16-bit (non-multiplexed) mode, but communicates through the Parallel Port Mux.

The mode of the Host Port Mux is determined by the state of the GPIO6 pin at reset. If GPIO6 is low, the pins

of the Host Port Mux will be set to PGPIO. The HPI will still be enabled, but it will communicate through the

Parallel Port Mux. The Parallel/Host Port Mux Mode bit of the External Bus Control Register will be set to 0

to reflect the PGPIO mode of the Host Port Mux.

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Functional Overview

If GPIO6 is high, the HPI will be enabled in 8-bit (multiplexed) mode: pins HD[7:0] are set to HPI.HD[7:0], and

HC0 and HC1 are set to HPI.HAS and HPI.HBIL, respectively. The Parallel/Host Port Mux Mode bit field in

the XBSR will be set to 1 to reflect the HPI multiplexed mode of the Host Port Mux. See Section 3.7, Host-Port

Interface (HPI), for more information on the operation of the HPI in multiplexed and non-multiplexed modes.

Table 3–5 lists the individual routing of the HPI and PGPIO signals to the Host Port Mux pins.

Table 3–5. TMS320VC5502 Routing of Host Port Mux Signals

PARALLEL/HOST PORT MUX MODE = 0

(PGPIO)

PARALLEL/HOST PORT MUX MODE = 1

(8-BIT HPI MULTIPLEXED)

Data Bus

PGPIO[43:36]

Control Bus

PGPIO44

HD[7:0]

HPI.HD[7:0]

HC0

HC1

HPI.HAS

HPI.HBIL

PGPIO45

3.3.3 Serial Port 2 Mux

The 5502 has three serial ports: McBSP0, McBSP1, and McBSP2, each of which has six signals. The signals

for McBSP0 and McBSP1 are directly routed to pins on the 5502. Four of the pins for McBSP2 are multiplexed

with two pins of the on-chip UART and two pins of the GPIO, the mode of the Serial Port 2 Mux determines

which signals are routed to the 5502 pins.

The mode of the Serial Port 2 Mux is determined by the state of the GPIO7 pin at reset. If GPIO7 is low, the

UART is enabled and its RX and TX pins are routed to the SP1 and SP3 pins, respectively. The GPIO3 and

GPIO5 pins are routed to the SP0 and SP2 pins, respectively. In this mode, McBSP2 will be disabled and any

writes or reads to/from its registers will result in a bus error if the PERITOEN bit of the Time-Out Control

Register is set to 1.

If GPIO7 is high, McBSP2 will be enabled and its CLKX2, CLKR2, FSX2, and FSR2 signals will be routed to

theSP0, SP1, SP2, andSP3pins, respectively. Inthismode, theUARTwillbedisabledandanywritesorreads

to/from its registers will result in a bus error if the PERITOEN bit of the Time-Out Control Register is set to 1.

GPIO3 and GPIO5 will not be available during this mode of the Serial Port 2 Mux.

Table 3–6 lists the individual routing of the McBSP2, UART, and GPIO signals to the Serial Port 2 Mux pins.

Table 3–6. TMS320VC5502 Routing of Serial Port 2 Mux Signals

SP0

SP1

SP2

SP3

SERIAL PORT 2 MUX MODE = 0

SERIAL PORT 2 MUX MODE = 1

GPIO3

UART.TX

GPIO5

CLKX2

CLKR2

FSX2

UART.RX

FSR2

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Functional Overview

3.3.4 External Bus Selection Register (XBSR)

The External Bus Selection Register controls the mode of the Parallel Port Mux, Host Port Mux, and the Serial

Port 2 Mux. The Parallel Port Mux can be configured to support the 32-bit EMIF or to support the HPI in 16-bit

(non-multiplexed) mode and parallel general-purpose I/O. The Host Port Mux can be configured to support

the HPI in 8-bit (multiplexed) mode or parallel general-purpose I/O (PGPIO). The Serial Port 2 Mux can be

configured to support either the McBSP2 or the UART and general-purpose I/O.

The XBSR configures the Parallel Port Mux and the Host Port Mux at reset based on the state of the GPIO6

pin at reset. When GPIO6 is high at reset, the Parallel Port Mux will be configured to support the 32-bit EMIF

and the Host Port Mux will be configured to support the HPI in 8-bit (multiplexed) mode. When GPIO6 is low

at reset, the Parallel Port Mux will be configured to support the HPI in 16-bit (non-multiplexed) mode and

parallel general-purpose I/O (PGPIO) and the Host Port Mux will be configured to support parallel

general-purpose I/O. The Paralle/Host Port Mux Mode bit of the XBSR will reflect the mode selected for the

†

Parallel and Host Port Muxes.

The XBSR configures the Serial Port 2 Mux based on the state of the GPIO7 pin at reset. When GPIO7 is high

atreset, theSerialPort2MuxwillbeconfiguredtosupporttheMcBSP2. WhenGPIO7islowatreset, theSerial

Port 2 Mux will be configured to support the UART and general-purpose I/O (PGPIO). The Serial Port 2 Mux

†

Mode bit of the XBSR will reflect the mode selected for the Serial Port 2 Mux.

The clock to the McBSP2, UART, and EMIF modules is disabled automatically when these modules are not

selected through the External Bus Selection Register. Note that any accesses to disabled modules will result

in a bus error if the PERITOEN bit of the Time-Out Control Register is set to 1.

15

8

Reserved

R, 00000000

7

4

3

2

1

0

Parallel /Host

Port Mux

Mode

Serial Port 2

Mux Mode

†

Reserved

R, 0000

Reserved

R, 0

R/W, 0

R/W, GPIO7

R/W, GPIO6

LEGEND: R = Read, W = Write, n = value at reset

†

This reserved bit must be kept as zero during any writes to XBSR.

Figure 3–3. External Bus Selection Register Layout (0x6C00)

†

Modifying the XBSR to change the mode of the Parallel Port Mux, Host Port Mux, and Serial Port 2 Mux after the 5502 has been brought out

of reset is not recommended.

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Functional Overview

Table 3–7. External Bus Selection Register Bit Field Description

BIT NAME

Reserved

BIT NO.

15–4

3

ACCESS

R

RESET VALUE

000000000000

0

DESCRIPTION

Reserved

R/W

Reserved. This reserved bit must be kept as zero during any writes

to XBSR.

Serial Port 2 Mux

Mode

2

R/W

GPIO7

Serial Port 2 Mux Mode bit. Determines the mode of the third serial

port.

Serial Port 2 Mux Mode = 0: The Serial Port 2 Mux is configured to

support the UART and PGPIO. In this

mode, the UART is enabled and its two

signals are routed to the corresponding

pins on the Serial Port 2 Mux. GPIO3

and GPIO5 are also routed to their

corresponding pins on the Serial Port 2

Mux.

Serial Port 2 Mux Mode = 1: The Serial Port 2 Mux is configured to

support the McBSP2. In this mode, the

McBSP2 is enabled and its six signals

are routed to their corresponding pins

on the Serial Port 2 Mux.

Reserved

1

0

R

0

Reserved

Parallel/Host Port

Mux Mode

R/W

GPIO6

Parllel/Host Port Mux Mode bit. Determines the mode of the Parallel

Port Mux and the Host Port Mux.

•

Parallel/Host Port Mux Mode = 0:

The Parallel Port Mux is configured to support the HPI in 16-bit

(non-multiplexed) mode and PGPIO. In this mode, the HPI is

enabled and its 16 address, 16 data, and 9 control signals are

routed to their corresponding pins on the Parallel Port Mux. The

rest of the pins are routed to PGPIO. The EMIF cannot be used

in this mode.

The Host Port Mux is configured to support PGPIO. In this mode,

the Host Port Mux pins will be routed to PGPIO.

•

Parallel/Host Port Mux Mode = 1:

The Parallel Port Mux is configured to support the 32-bit EMIF. In

this mode, the EMIF is enabled and its 20 address, 32 data, and

16 control signals are routed to their corresponding pins on the

Parallel Port Mux.

The Host Port Mux is configured to support the HPI in 8-bit

(multiplexed) mode. In this mode, the HPI is enabled and its eight

data/address and two control signals are routed to their

corresponding pins on the Host Port Mux.

3.4 Timers

The 5502 has four 64-bit timers: Timer 0, Timer 1, Watchdog Timer (WDT), and Timer 3. The first two timers,

Timer 0 and Timer 1, are mainly used as general-purpose timers. The third timer, the Watchdog Timer, can

be used as either a general-purpose timer or a watchdog timer. The fourth timer is reserved as a DSP/BIOS

counter; users have no access to this timer.

Each timer has one input, one output, and one interrupt signal: TIN, TOUT, and TINT, respectively. Timer 0,

Timer 1, and the Watchdog Timer are each assigned a pin: TIM0 pin is assigned to Timer 0, TIM1 is assigned

to Timer 1, and NMI/WDTOUT is used by the Watchdog Timer. The input (TIN) or output (TOUT) signal of

Timer 0, Timer 1, and the Watchdog Timer can be connected to their respective pins via the Timer Signal

Selection Register (TSSR).

TheDSP/BIOStimerinput, output, andinterruptsignalsarenotinternallyconnected. Nointerruptsareneeded

from this timer; therefore, the timer interrupt signal is not internally connected to the CPU interrupt logic.

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Functional Overview

The interrupt signal (TINT) of the Watchdog Timer can be internally connected to the NMI, RESET, and INT3

signals via the TSSR.

Note that the NMI/WDTOUT pin has a dual function: Watchdog Timer pin and NMI input pin. The function of

the NMI/WDTOUT pin can be selected through the TSSR.

For more information on the 5502 timers, see the TMS320VC5501/5502 DSP Timers Reference Guide

(literature number SPRU618).

3.4.1 Timer Interrupts

As stated earlier, each timer has one input, one output, and one interrupt signal: TIN, TOUT, and TINT,

respectively. The interrupt signals of Timer 0 and Timer 1 are directly connected to the interrupt logic of the

DSP (see Figure 3–4). The interrupts for Timer 0 and Timer 1 are maskable and can be enabled or disabled

through the TINT0 and TINT1 bits of the interrupt enable registers (IER0 and IER1); setting TINT0 of IER0

to ‘1’ enables the interrupt for Timer 0 and setting TINT1 of IER1 enables the interrupt for Timer 1.

TMS320VC5502 DSP

Interrupt Logic

RESET

INT3

NMI

TINT1

TINT0

Timer0

TINT

10

Others

Timer1

TINT

Watchdog

Timer

01

11

10

TINT

IWCON

RESET

INT3

NMI/WDTOUT

Figure 3–4. Timer Interrupts

The interrupt signal for the Watchdog Timer can be internally connected to the RESET, INT3, or NMI signals

by setting the IWCON bit of the Timer Signal Selection Register (TSSR) appropriately (see Figure 3–4). The

DSP will be reset once the Watchdog Timer generates an interrupt if the timer interrupt is connected toRESET

(IWCON = ‘01’). A non-maskable interrupt will be generated if the timer interrupt is connected to NMI (IWCON

= ‘10’). An external interrupt will be generated when the timer interrupt signal is connected to INT3 (IWCON

= ‘11’), but only if the INT3 bit of IER0 is set to ‘1’.

Refer to Section 3.16, Interrupts, for more information on using interrupts.

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Functional Overview

3.4.2 Timer Pins

The 5502 has one pin for each timer: TIM0 for Timer 0, TIM1 for Timer 1, and NMI/WDTOUT for the Watchdog

Timer. Either the output (TOUT) or input (TIN) signal can be connected to the timer pin (see Figure 3–5). When

the timer pin is configured as an output, the TOUT signal is connected to the pin. The TIN signal is connected

to the pin when the pin is configured as an input. Each pin can be configured as input or output through the

Timer Signal Selection Register (TSSR) (bits TIM0_MODE, TIM1_MODE, and WDT_MODE).

TMS320VC5502 DSP

TSSR

TIN

TIM0_MODE

Timer0

TOUT

TIM0

TIM1

TIN

TIM1_MODE

WDT_MODE

Timer1

TOUT

TIN

Watchdog

Timer

NMI/WDTOUT

TOUT

Figure 3–5. Timer Pins

When configured as input, the timer pin can be used to source an external clock to the timer. Also, when the

timer pin is configured as input and the timer is running off an internal clock, the timer pin can be used to start

or stop count of the timer (clock gating).

When the timer pin is configured as an output, the timer pin can signal a pulse (pulse mode) or a change of

state (clock mode) when the timer count matches its period.

The NMI/WDTOUT pin has two functions: Watchdog Timer pin or NMI pin. The NMI/WDTOUT_CFG bit of the

TSSR controls the function of this pin. It is possible to configure the NMI/WDTOUT pin as NMI

(NMI/WDTOUT_CFG = ‘1’) and also connect the Watchdog Timer TINT signal to the NMI signal

(IWCON = ‘10’). In this case, the external NMI signal will be overridden by the TINT signal of the Watchdog

Timer, i.e., applying a signal to the NMI/WDTOUT pin will not generate the non-maskable interrupt NMI.

For all three timers (Timer 0, Timer 1, and the Watchdog Timer), both the TIN and TOUT signals can be used

for general-purpose input/output. The timer pin must be configured for input to use the TIN signal as

general-purpose input/output. The timer pin can be configured as an input by setting the pin mode bit of the

Timer Signal Selection Register (TSSR) to ‘0’. The TOUT signal can be used as general-purpose input/output

if the timer pin is configured for output. The timer pin can be configured as an output by setting the pin mode

bit of the TSSR to ‘1’. The GPIO Enable Register (GPEN), GPIO Direction Register (GPIODIR), and the GPIO

Data Register (GPDAT) of each timer can be used to control the state of the timer pins when used as

general-purpose input/output.

34

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Functional Overview

3.4.3 Timer Signal Selection Register (TSSR)

The Timer Signal Selection Register (TSSR) controls several pin characteristics for Timer 0, Timer 1, and the

Watchdog Timer. The TSSR can be used to specify whether the pins of Timer 0, Timer 1, and the Watchdog

Timer are inputs or outputs. The TSSR also determines how the interrupt signal of the Watchdog Timer is

connected internally and sets the function for the NMI/WDTOUT pin of the 5502. By default, all timer pins

(TIM0, TIM1, and NMI/WDTOUT) are set as inputs, the interrupt signal of the Watchdog Timer is not internally

connected to anything, and the NMI/WDTOUT pin has the function of the NMI signal.

15

8

Reserved

R, 00000000

7

6

5

4

3

2

1

0

NMI/WDTOUT

_CFG

Reserved

R, 00

WDT_MODE

R/W, 0

TIM1_MODE

R/W, 0

TIM0_MODE

R/W, 0

IWCON

R/W, 00

R/W, 1

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–6. Timer Signal Selection Register Layout (0x8000)

Table 3–8. Timer Signal Selection Register Bit Field Description

BIT NAME

Reserved

BIT NO.

15–6

5

ACCESS

R

RESET VALUE

0000000000

0

DESCRIPTION

Reserved

WDT_MODE

R/W

WDT pin mode

WDT_MODE = 0: WDTOUT pin is used as the timer input

pin.

WDT_MODE = 1: WDTOUT pin is used as the timer output

pin.

TIM1_MODE

TIM0_MODE

4

3

R/W

0

TIM1 pin mode

TIM1_MODE = 0: TIM1 pin is used as the timer input pin.

TIM1_MODE = 1: TIM1 pin is used as the timer output pin.

TIM0 pin mode

TIM0_MODE = 0: TIM0 pin is used as the timer input pin.

TIM0_MODE = 1: TIM0 pin is used as the timer output pin.

†

If NMI/WDTOUT_CFG = 1 and IWCON = 10, only the WDTOUT signal will drive the NMI signal; the external source driving the NMI/WDTOUT

pin will be ignored.

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Functional Overview

Table 3–8. Timer Signal Selection Register Bit Field Description (Continued)

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

IWCON

2:1

R/W

00

Internal WDT output signal connection

IWCON = 00:

IWCON = 01:

Internal watchdog timer interrupt (TINT)

signal has no internal connection.

Internal watchdog timer interrupt (TINT)

signal has an internal connection to

RESET pin.

IWCON = 10:

IWCON = 11:

Internal watchdog timer interrupt (TINT)

signal has an internal connection to NMI

pin.

Internal watchdog timer interrupt (TINT)

signal has an internal connection to INT3

pin.

†

NMI/WDTOUT_CFG

0

R/W

1

NMI/WDTOUT configuration

NMI/WDTOUT_CFG = 0: NMI/WDTOUT pin is used as the

WDTOUT pin.

NMI/WDTOUT_CFG = 1: NMI/WDTOUT pin is used as the

†

NMI input pin.

†

If NMI/WDTOUT_CFG = 1 and IWCON = 10, only the WDTOUT signal will drive the NMI signal; the external source driving the NMI/WDTOUT

pin will be ignored.

3.5 Universal Asynchronous Receiver/Transmitter (UART)

The UART peripheral is based on the industry-standard TL16C550B asynchronous communications element,

which in turn, is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up

(characterorTL16C450mode), theUARTcanbeplacedinanalternateFIFO(TL16C550)mode. Thisrelieves

the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and

transmitter FIFOs store up to 16 bytes, including three additional bits of error status per byte for the receiver

FIFO.

The UART performs serial-to-parallel conversions on data received from a peripheral device or modem and

parallel-to-serial conversion on data received from the CPU. The CPU can read the UART status at any time.

The UART includes control capability and a processor interrupt system that can be configured to minimize

software management of the communications link.

The UART includes a programmable baud rate generator capable of dividing the CPU clock by divisors from 1

to 65535 and producing a 16× reference clock for the internal transmitter and receiver logic.

The UART pins are multiplexed with the pins of McBSP2. The Serial Port 2 Mux determines which pins are

connected to the SP0, SP1, SP2, and SP3. If GPIO7 is high at reset, the Serial Port 2 Mux Mode bit in the

External Bus Selection Register (XBSR) will be set to 1 to indicate that the UART module is enabled. In this

mode, the TX and RX signals of the UART will be routed to the SP1 and SP3 pins, respectively. If GPIO7 is

low at reset, the Serial Port 2 Mux Mode bit will be set to 0 to indicate that the UART module is disabled. In

this mode, any reads or writes to the UART registers will result in bus errors if the PERITOEN bit of the

Time-Out Control Register is set to 1.

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Functional Overview

S

e

l

e

c

t

8

Receiver

FIFO

8

Receiver

Shift

Register

8

RX

Data

Bus

Receiver

Buffer

Peripheral

Bus

signal

Buffer

Register

16

Receiver

Timing and

Control

Line

Control

Register

Divisor

Latch (LS)

16

Baud

Generator

Divisor

Latch (MS)

Transmitter

Timing and

Control

Line

Status

Register

8

Transmitter

FIFO

S

e

l

e

c

t

Transmitter

Shift

Register

Transmitter

Holding

Register

8

TX

signal

Modem

Control

Register

8

Control

Logic

Interrupt

Enable

Register

Interrupt/

Event

Control

Logic

Interrupt to CPU

Event to DMA controller

Interrupt

Identification

Register

8

Power and

Emulation

Control

FIFO

Register

Control

Register

Figure 3–7. UART Functional Block Diagram

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Functional Overview

2

3.6 Inter-Integrated Circuit (I C) Module

2

The TMS320VC5502 also includes an I C serial port for control purposes. Features of the I C port include:

2

•

Compatibility with Philips’ I C-Bus Specification, Version 2.1 (January 2000)

Fast mode up to 400 Kbps (no fail-safe I/O buffers)

Noise filters (on the SDA and SCL pins) to suppress noise of 50 ns or less (I C module clock must be in

the range of 7 MHz to 12 MHz)

2

•

7-bit and 10-bit device addressing modes

Master (transmit/receive) and slave (transmit/receive) functionality

Events: DMA, interrupt, or polling

Slew-rate limited open-drain output buffers

2

The I C module clock must be in the range of 7 MHz to 12 MHz. This is necessary for the proper operation

2

of the I C module.

NOTE: For additional information, see the TMS320VC5501/5502/5509 DSP Inter-Integrated

Circuit (I2C) Module Reference Guide (literature number SPRU146).

2

Figure 3–8 is a block diagram of the I C module.

2

I C Module

Clock

SYSCLK2

Prescale

From PLL

Clock Generator

I2CPSC

Bit Clock

Generator

Control

SCL

Noise

Filter

Own

2

I C Clock

I2CCLKH

I2CCLKL

I2COAR

I2CSAR

I2CMDR

I2CCNT

Address

Slave

Address

Mode

Transmit

I2CXSR

Data

Count

Transmit

Shift

Transmit

Buffer

I2CDXR

SDA

Interrupt/DMA

I2CIER

Noise

Filter

2

I C Data

Interrupt

Enable

Receive

I2CDRR

Receive

Buffer

Status

I2CSTR

Interrupt

Source

Receive

Shift

I2CRSR

I2CISRC

NOTE A: Shading denotes control/status registers.

2

Figure 3–8. I C Module Block Diagram

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Functional Overview

3.7 Host-Port Interface (HPI)

The 5502 HPI provides an interface to a host with the following features:

•

16-bit host address bus and 16-bit host data bus (non-multiplexed mode only)

Multiplexed and non-multiplexed modes

Host access to on-chip DARAM (excluding CPU memory-mapped registers)

16-bit address register with autoincrement capability for faster transfers

Multiple address/data strobes provide a glueless interface to a variety of hosts

HRDY signal for handshaking with host

The 5502 HPI can access all of internal DARAM space (excluding memory-mapped CPU registers), but it

cannot access peripheral registers or external memory. Note that all memory accesses made through the HPI

are word-addressed.

The 5502 HPI supports both multiplexed 8-bit and non-multiplexed 16-bit modes. One of these two modes

can be selected via the GPIO6 pin. At reset, if GPIO6 is low, the HPI non-multiplexed 16-bit mode is enabled

and some of the HPI signals can be used as GPIOs. If GPIO6 is high, the HPI can be used in multiplexed 8-bit

mode. Similarly, some of the HPI signals can be used as GPIOs. (See Section 3.3.2, Host Port Mux, for more

information on pin multiplexing for both modes of the HPI.)

NOTE: No host access should occur when the HPI is placed in IDLE. The host cannot wake

up the DSP through the DSP_INT bit of the HPIC1 register when the DSP is in IDLE mode.

When GPIO6 is low at reset, the 5502 HPI will be configured in non-multiplexed mode. In this mode, pins

A[17:2] and pins D[15:0] of the Parallel Port Mux will be set to HPI.HA[15:0] and HPI.HD[15:0], respectively.

In non-multiplexed mode, the host can read/write 16-bit data from the 5502’s internal memory by using the

16-bit address and data bus and the HPI control signals [see the TMS320VC5501/5502 DSP Host Port

Interface (HPI) Reference Guide (literature number SPRU620) for more information on the 5502 HPI]. Note

that in this mode, the 5502 EMIF wil be disabled.

When GPIO6 is high at reset, the 5502 HPI will be configured in multiplexed mode. In this mode, pins HD[7:0],

HC0, and HC1 of the Host Port Mux will be set to HPI.HD[7:0], HPI.HAS, and HPI.HBIL, respectively. In

multiplexed mode, the host can only send 8 bits of data at a time through the HPI.HD[7:0] bus; therefore, some

extra steps have to be taken to read/write from the 5502’s internal memory [see the TMS320VC5501/5502

DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620) for more information on the

5502 HPI]. Note that in this mode, the EMIF is fully enabled.

The 5502 HPI has its own register set, therefore the HINT bit of CPU register ST3_55 is not used for

DSP-to-host interrrupts. The HINT bit in the Host Port Control Register (HPIC) should be used for DSP-to-host

interrupts.

The HPI can access the entire DARAM space of the 5502 excluding memory-mapped CPU registers;

however, it does not have access to external memory of the peripheral I/O space. The HPI cannot access

internal DARAM space when the device is in reset.

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Functional Overview

3.8 Direct Memory Access (DMA) Controller

The 5502 DMA provides the following features:

•

Four standard ports for the following data resources: two for DARAM, one for Peripherals, and one for

External Memory

•

Six channels, which allow the DMA controller to track the context of six independent DMA channels

Programmable low/high priority for each DMA channel

One interrupt for each DMA channel

Event synchronization. DMA transfers in each channel can be dependent on the occurrence of selected

events.

•

Programmable address modification for source and destination addresses

Idle mode that allows the DMA controller to be placed in a low-power (idle) state under software control

The 5502 has an Auto-wakeup/Idle function for McBSP to DMA to on-chip memory data transfers when the

DMA and the McBSP are both set to IDLE. In the case that the McBSP is set to external clock mode and the

McBSP and the DMA are set to idle, the McBSP and the DMA can wake up from IDLE state automatically if

the McBSP gets a new data transfer. The McBSP and the DMA enter the idle state automatically after data

transfer is complete. [The clock generator (PLL) should be active and the PLL core should not be in

power-down mode for the Auto-wakeup/Idle function to work.]

The 5502 DMA controller allows transfers to be synchronized to selected events. The 5502 supports

16 separate synchronization events and each channel can be tied to separate synchronization event

independent of the other channels. Synchronization events are selected by programming the SYNC field in

the channel-specific DMA Channel Control Register (DMA_CCR).

The5502DMAcanaccessalltheinternalDARAMspaceaswellasallexternalmemoryspace. The5502DMA

2

also has access to the registers for the following peripheral modules: McBSP, UART, GPIO, PGPIO, and I C.

3.8.1 DMA Channel 0 Control Register (DMA_CCR0)

The DMA Channel 0 Control Register (DMA_CCR0) bit layouts are shown in Figure 3–9. DMA_CCR1 to

DMA_CCR5 have similar bit layouts. See the TMS320VC5501/5502 DSP Direct Memory Access (DMA)

Controller Reference Guide (literature number SPRU613) for more information on the DMA Channel n Control

Register (n = 0, 1, 2, 3, 4, or 5).

15

14

13

12

11

10

9

8

DSTAMODE

R/W, 00

SRCAMODE

R/W, 00

ENDPROG

R/W, 0

WP

REPEAT

R/W, 0

AUTOINIT

R/W, 0

7

6

5

4

0

EN

PRIO

FS

SYNC

R/W, 0

R/W, 00000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–9. DMA Channel 0 Control Register Layout (0x0C01)

The SYNC field (bits[4:0]) of the DMA_CCR register specifies the event that can initiate the DMA transfer for

the corresponding DMA channel. The five bits allow several configurations as listed in Table 3–9. The bits are

set to zero upon reset. For those synchronization modes with more than one peripheral listed, the Serial Port 2

Mux Mode bit field of the External Bus Selection Register (XBSR) dictates which peripheral event is actually

connected to the DMA input.

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Functional Overview

Table 3–9. Synchronization Control Function

SYNC FIELD IN

DMA_CCR

SYNCHRONIZATION MODE

00000b

00001b

00010b

00011b

00100b

00101b

00110b

00111b

01000b

No event synchronized

McBSP 0 Receive Event (REVT0)

McBSP 0 Transmit Event (XEVT0)

Reserved (Do not use this value)

McBSP1 Receive Event (REVT1)

McBSP1 Transmit Event (XEVT1)

Reserved (Do not use this value)

Reserved/McBSP Event

01001b

01010b

01011b

01100b

Serial Port 2 Mux Mode = 0: Reserved

Serial Port 2 Mux Mode = 1: McBSP2 Receive Event (REVT2)

Reserved/McBSP Event

Serial Port 2 Mux Mode = 0: Reserved

Serial Port 2 Mux Mode = 1: McBSP2 Transmit Event (XEVT2)

Reserved/UART Event

Serial Port 2 Mux Mode = 0: UART Receive Event (UARTREVT)

Serial Port 2 Mux Mode = 1: Reserved

Reserved/UART Event

Serial Port 2 Mux Mode = 0: UART Transmit Event (UARTXEVT)

Serial Port 2 Mux Mode = 1: Reserved

01101b

01110b

Timer 0 Event

Timer 1 Event

01111b

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

10000b

10001b

10010b

10011b

2

I C Receive Event

2

10100b

Other values

I C Transmit Event

Reserved (Do not use these values)

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Functional Overview

3.9.1 Input Clock Source

The clock input to the 5502 can be sourced from either an externally generated 3.3-V clock input on the

X2/CLKIN pin, or from the on-chip oscillator if an external crystal circuit is attached to the device as shown

in Figure 3–11. The CLKMD0 bit of the Clock Mode Control Register (CLKMD) determines which clock, either

OSCOUT or X2/CLKIN, is used as an input clock source to the DSP. If GPIO4 is low at reset, the CLKMD0

bit of the Clock Mode Control Register (CLKMD) will be set to ‘0’ and the internal oscillator and the external

crystal will generate the input clock to the DSP. If GPIO4 is high, the CLKMD0 bit will be set to ‘1’ and the input

clock will be taken directly from the X2/CLKIN pin.

The input clock source to the DSP can be directly used to generate the clocks to other parts of the system

(Bypass Mode) or it can be multiplied by a value from 2 to 15 and divided by a value from 1 to 32 to achieve

adesiredfrequency(PLLMode). ThePLLENbitofthePLLControl/StatusRegister(PLLCSR)isusedtoselect

between the PLL and bypass modes of the clock generator.

TheclockgeneratedthrougheitherthePLLModeortheBypassModecanbefurtherdivideddowntogenerate

a clock source for other parts of the system, or Clock Groups. Clock groups allow for lower power and

performance optimization since the frequency of groups with no high-speed requirements can be set to

one-fourth or one-half the frequency of other groups. A description of the different clock groups included in

the 5502 and the procedure for changing the operating frequency for those clock groups are described later

in this section.

3.9.1.1 Internal System Oscillator With External Crystal

The 5502 includes an internal oscillator which can be used in conjunction with an external crystal or ceramic

resonator to generate the input clock to the DSP. The oscillator requires an external crystal or ceramic

resonator connected across the X1 and X2/CLKIN pins. If the internal oscillator is not used, an external clock

source must be applied to the X2/CLKIN pin and the X1 pin should be left unconnected. Since the internal

oscillator can be used as a clock source to the PLL, the crystal oscillation frequency can be multiplied to

generate the input clock to the different clock groups of the DSP.

The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective series

resistance (ESR) as specified in Table 3–10. The connection of the required circuit is shown in Figure 3–11.

Under some conditions, all the components shown are not required. The capacitors, C and C , should be

1

2

chosen such that the equation below is satisfied. C in the equation is the load specified for the crystal that

L

is also specified in Table 3–10.

C₁C₂

C_L+

(C₁) C₂)

X2/CLKIN

X1

R

S

Crystal

C

2

1

Figure 3–11. Internal System Oscillator With External Crystal

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SPRS166D

Functional Overview

Table 3–10. Recommended Crystal Parameters

MAXIMUM ESR

SPECIFICATIONS (Ω)

MAXIMUM

FREQUENCY RANGE (MHz)

C

(pF)

R

(kΩ)

S

LOAD

C

(pF)

SHUNT

20–15

15–12

12–10

10–8

8–6

40

60

80

10

16

18

7

0

7

2.8

2.2

8.8

14

6–5

The recommended ESR is presented as a maximum, and theoretically, a crystal with a lower maximum ESR

might seem to meet these specifications. However, it is recommended that crystals with actual maximum ESR

specifications as shown in Table 3–10 be used since this will result in maximum crystal performance reliability.

The internal oscillator can be set to power-down mode through the use of the OSCPWRDN bit in the PLL

Control/Status Register (PLLCSR). If the internal oscillator and the external crystal are generating the input

clock for the DSP (CLKMD0 = 0), the internal oscillator will be set to power-down mode when the OSCPWRDN

bit is set to 1 and the clock generator is set to its idle mode (CLKIS bit of the IDLE Status Register (ISTR)

becomes 1). If the X2/CLKIN pin is supplying the input clock to the DSP (CLKMD0 = 1), the internal oscillator

will be set to power-down immediately after the OSCPWRDN bit is set to 1.

The 5502 has internal circuitry that will count down a predetermined number of clock cycles (41,032 reference

clock cycles) to allow the oscillator input to become stable after waking up from power-down state or after

reset. If a reset is asserted, program flow will start after all stabilization periods have expired; this includes the

oscillator stabilization period only if GPIO4 is low at reset. If the oscillator is coming out of power-down mode,

program flow will start immediately after the oscillator stabilization period has completed. See Section 3.9.6,

Reset Sequence, for more details on program flow after reset or after oscillator power-down. See

Section 3.10, Idle Control, for more information on the oscillator power-down mode.

3.9.1.2 Clock Generation With PLL Disabled (Bypass Mode, Default)

After reset, the PLL multiplier (M1) and its divider (D0) will be bypassed by default and the input clock to point C

in Figure 3–12 will be taken from, depending on the state of the GPIO4 pin after reset, either the internal

oscillator or the X2/CLKIN pin. The PLL can be taken out of bypass mode as described in Section 3.9.4.1,

C55x Subsystem Clock Group.

3.9.1.3 Clock Generation With PLL Enabled (PLL Mode)

When not in bypass mode, the frequency of the input clock can be divided down by a programmable

divider (D0) by any factor from 1 to 32. The output clock of the divider can be multiplied by any factor from 2

to 15 through a programmable multiplier (M1). The divider factor can be set through the PLLDIV0 bit of the

PLL Divider 0 Register. The multiplier factor can be set through the PLLM bits of the PLL Multiplier Control

Register.

Thereisaspecificminimumandmaximumreferenceclock(PLLREF)andoutputclock(PLLOUT)fortheblock

labeled “PLL” in Figure 3–10, as well as for the C55x Core clock (CLKOUT3), the Fast Peripherals clock

(SYSCLK1), the Slow Peripherals clock (SYSCLK2), and the EMIF internal clock (SYSCLK3). The clock

generator must not be configured to exceed any of these constraints (certain combinations of external clock

input, internal dividers, and PLL multiply ratios might not be supported). See Table 3–11 for the PLL clock input

and output frequency ranges.

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Functional Overview

3.9.1.4 Frequency Ranges for Internal Clocks

There are specific minimum and maximum reference clocks for all of the internal clocks. Table 3–11 lists the

minimum and maximum frequencies for the internal clocks of the TMS320VC5502.

†

Table 3–11. Internal Clocks Frequency Ranges

VC5502-200

VC5502-300

CLOCK SIGNAL

UNIT

MIN

MAX

20

MIN

MAX

20

OSCOUT (CLKMD = 0)

PLLREF (PLLEN = 1)

PLLOUT (PLLEN = 1)

CLKOUT3

5

12

70

–

5

12

70

–

MHz

100

200

300

200

300

SYSCLK1

–

150

–

150

SYSCLK2

–

SYSCLK1

–

SYSCLK1

‡

SYSCLK1

SYSCLK3

–

SYSCLK1

–

†

Also see the electrical specification (timing requirements and switching characteristics parameters) in Section 6.7, Clock Options, of this data

manual.

When an internal clock is used for the EMIF module, the frequency for SYSCLK3 must also be less than or equal to 100 MHz. When an external

clock is used, the maximum frequency of SYSCLK3 can be equal to or less than the frequency of SYSCLK1; however, the frequency of the clock

signal applied to the ECLKIN pin must be less than or equal to 100 MHz.

‡

3.9.2 Clock Groups

The TMS320VC5502 has four clock groups: the C55x Subsystem Clock Group, the Fast Peripherals Clock

Group, the Slow Peripherals Clock Group, and the External Memory Interface Clock Group. Clock groups

allow for lower power and performance optimization since the frequency of groups with no high-speed

requirements can be set to 1/4 or 1/2 the frequency of other groups.

3.9.2.1 C55x Subsystem Clock Group

The C55x Subsystem Clock Group includes the C55x CPU core, internal memory (DARAM and ROM), the

ICACHE, and all CPU-related modules. The input clock to this clock group is taken from the CLKOUT3 signal

(as shown in Figure 3–10), the source of which can be controlled through the CLKOUT3 Select Register

(CK3SEL). The different options for the CLKOUT3 signal are intended for test purposes; it is recommended

that the CK3SEL bits of the CK3SEL register be kept at their default value of ‘1011b’ during normal operation.

When operating the clock generator in PLL Mode, the frequency of CLKOUT3 can be set by adjusting the

divider and multiplier values of D0 and M1 through the PLLDIV0 and PLLM registers, respectively.

3.9.2.2 Fast Peripherals Clock Group

The Fast Peripherals Clock Group includes the DMA, HPI, and the timers. The input clock to this clock group

is taken from the output of divider 1 (D1) (as shown in Figure 3–10). By default, the divider is set to divide its

input clock by four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV1

bits of the PLL Divider1 Register (PLLDIV1) through software.

3.9.2.3 Slow Peripherals Clock Group

2

The Slow Peripherals Clock Group includes the McBSPs, I C, and the UART. The input clock to this clock

group is taken from the output of divider 2 (D2). by default, the divider is set to divide its input clock by four,

but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV2 bits of the PLL

Divider2Register(PLLDIV2)throughsoftware. TheclockfrequencyoftheSlowPeripheralsClockGroupmust

be equal to or less than that of the Fast Peripherals Clock Group.

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April 2001 – Revised June 2003

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Functional Overview

3.9.2.4 External Memory Interface Clock Group

The External Memory Interface Clock Group includes the External Memory Interface (EMIF) module and the

external data bridge modules. The input clock to this clock group is taken from the output of divider 3 (D3).

By default, the divider is set to divide its input clock by four, but the divide value can be changed to divide-by-1

or divide-by-2 by modifying the PLLDIV3 bits of the PLL Divider3 Register (PLLDIV3) through software. The

clock frequency of the External Memory Interface Clock Group must be equal to or less than that of the Fast

Peripherals Clock Group.

3.9.3 EMIF Input Clock Selection

The EMIF may be clocked from an external asynchronous clock source through the ECLKIN pin if a specific

EMIF frequency is needed. The source for the EMIF clock can be specified through the EMIFCLKS pin. If

EMIFCLKS is low, then the EMIF will be clocked via the same internal clock that feeds the data bridge module

and performance will be optimal. If EMIFCLKS is high, then an external asynchronous clock, which can be

taken up to 100 MHz (TBD), will clock the EMIF. The data throughput performance may be degraded due to

synchronization issues when an external clock source is used for the EMIF.

46

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Functional Overview

3.9.4 Changing the Clock Group Frequencies

DSP software can be used to change the clock frequency of each clock group by setting adequate values in

the PLL control registers. Figure 3–12 shows which PLL control registers affect the different portions of the

clock generator. The following sections describe the procedures for changing the frequencies of each clock

group.

OSCOUT

X2/CLKIN

CLKMD0

0

Point A

Point B

Divider

D0

PLL Core

Point C

1

0

Multiplier M1

1

Divider

D1

SYSCLK1

SYSCLK2

SYSCLK3

Divider

D2

PLLEN

Divider

D3

CLKOUT3

Divider

OD1

PLLCSR

PLLM

PLLDIV0

PLLDIV1

PLLDIV2

PLLDIV3

OSCDIV1

CK3SEL

WKEN

Oscillator Power-Down Control

Figure 3–12. Clock Generator Registers

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Functional Overview

3.9.4.1 C55x Subsystem Clock Group

Changes to the PLL Control Register (PLLCSR), the PLL Divider0 Register (PLLDIV0), and the PLL Multiplier

Register (PLLM) affect the clock of this clock group. The following procedure must be followed to change or

to set the PLL to a specific value:

1. Switch to bypass mode by setting the PLLEN bit to 0.

2. Set the PLL to its reset state by setting the PLLRST bit to 1.

3. Change the PLL setting through the PLLM and PLLDIV0 bits.

4. Wait for 1 µs.

5. Release the PLL from its reset state by setting PLLRST to 0.

6. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt.

7. Switch back to PLL mode by setting the PLLEN bit to 1.

The frequency of the C55x Subsystem Clock Group can be up to 300 MHz for the TMS320VC5502-300 and

up to 200 MHz for the TMS320VC5502-200.

3.9.4.2 Fast Peripherals Clock Group

ChangestotheclockoftheC55xSubsystemClockGroupaffecttheclockoftheFastPeripheralsClockGroup.

The PLLDIV1 value of the PLL Divider1 Register (PLLDIV1) should not be set in a manner that makes the

frequency for this clock group greater than 150 MHz. There must be no activity in the modules included in the

Fast Peripherals Clock Group when the value of PLLDIV1 is being changed. It is recommended that the fast

peripheral modules be put in IDLE mode before changing the PLLDIV1 value.

3.9.4.3 Slow Peripherals Clock Group

Changes to the clock of the C55x Subsystem Clock Group affect the clock of the Slow Peripherals Clock

Group. The PLLDIV2 value of the PLL Divider2 Register (PLLDIV2) should not be set in a manner that makes

the frequency for this clock group greater than 150 MHz or greater than the frequency of the Fast Peripherals

Clock Group. There must be no activity in the modules included in the Slow Peripherals Clock Group when

the value of PLLDIV2 is being changed. It is recommended that the slow peripheral modules be put in IDLE

mode before changing the PLLDIV2 value.

3.9.4.4 External Memory Interface Clock Group

Changes to the clock of the C55x Subsystem Clock Group affect the clock of the External Memory Interface

Clock Group. The PLLDIV3 value of the PLL Divider3 Register (PLLDIV3) should not be set in a manner that

makes the frequency for this clock group greater than 100 MHz or greater than the frequency of the Fast

Peripherals Clock Group, whichever is smaller. If an external clock is used, the clock on the ECLKIN pin can

be up to 100 MHz and the output of divider 3 can be set equal to or lower than the frequency of the Fast

Peripherals Clock Group. There must be no external memory accesses when the value of PLLDIV3 is being

changed, this means that the value of PLLDIV3 cannot be changed by a program that is being executed from

external memory. It is recommended that the EMIF be put in IDLE mode before changing the PLLDIV3 value.

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Functional Overview

3.9.5 PLL Control Registers

The 5502 PLL control registers are accessible via the I/O memory map.

Table 3–12. PLL Control Registers

ADDRESS

1C80h

1C82h

1C88h

1C8Ah

1C8Ch

1C8Eh

1C90h

1C92h

1C98h

REGISTER

PLLCSR

CK3SEL

PLLM

PLLDIV0

PLLDIV1

PLLDIV2

PLLDIV3

OSCDIV1

WKEN

3.9.5.1 PLL Control / Status Register (PLLCSR)

15

8

0

Reserved

R, 00000000

7

6

5

4

3

2

1

Reserved

R, 0

STABLE

R, 1

LOCK

R, 0

Reserved

R, 0

PLLRST

R/W, 1

OSCPWRDN

R/W, 0

PLLPWRDN

R/W, 0

PLLEN

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–13. PLL Control/Status Register Layout (0x1C80)

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Functional Overview

Table 3–13. PLL Control/Status Register Bit Field Description

BIT NAME

Reserved

STABLE

BIT NO.

ACCESS

RESET VALUE

000000000

1

DESCRIPTION

15:7

6

R

Reserved. Reads return 0. Writes have no effect.

Oscillator output stable. This bit indicates if the OSCOUT/CLKIN

input has stabilized.

STABLE = 0:

STABLE = 1:

OSCOUT/CLKIN output is not yet stable.

Oscillator counter is not done counting

41,032 reference clock cycles.

OSCOUT/CLKIN input is stable. This is true if

any one of the three cases is true:

a) Oscillator counter has finished counting.

b) Oscillator counter is disabled.

c) Test mode.

LOCK

5

R

0

Lock mode indicator. This bit indicates whether the clock generator

is in its lock mode.

LOCK = 0:

LOCK = 1:

The PLL is in the process of getting a phase

lock.

The clock generator is in the lock mode. The

PLL has a phase lock and the output clock of

the PLL has the frequency determined by the

PLLM register and PLLDIV0 register.

Reserved

PLLRST

4

3

R

0

1

Reserved. Reads return 0. Writes have no effect.

Asserts RESET to PLL

R/W

PLLRST = 0:

PLLRST = 1:

PLL reset released

PLL reset asserted

OSCPWRDN

2

R/W

0

Sets internal oscillator to power-down mode

OSCPWRDN = 0: Oscillator operational

OSCPWRDN = 1: Oscillator set to power-down mode based on

state of CLKMD0 bit of Clock Mode Control

Register (CLKMD).

When CLKMD0 = 0, the internal oscillator is set

to power-down mode when the clock generator

is set to its idle mode [CLKIS bit of the IDLE

Status Register (ISTR) becomes 1].

When CLKMD0 = 1, the internal oscillator is set

to power-down mode immediately after the

OSCPWRDN bit is set to 1.

PLLPWRDN

PLLEN

1

0

R/W

0

Selects PLL power down

PLLPWRDN = 0: PLL operational

PLLPWRDN = 1: PLL placed in power-down state

PLL mode enable. This bit controls the multiplexer before dividers

D1, D2, and D3.

PLLEN = 0:

PLLEN = 1:

Bypass mode. Divider D1 and PLL are

bypassed. SYSCLK1 to 3 divided down

directly from input reference clock.

PLL mode. Divider D1 and PLL are not

bypassed. SYSCLK1 to 3 divided down from

PLL output.

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3.9.5.2 PLL Multiplier Control Register (PLLM)

15

8

Reserved

R, 00000000

7

5

4

0

Reserved

R, 000

PLLM

R/W, 00000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–14. PLL Multiplier Control Register Layout (0x1C88)

Table 3–14. PLL Multiplier Control Register Bit Field Description

BIT NAME

Reserved

PLLM

BIT NO.

15:5

ACCESS

R

RESET VALUE

00000000000

00000

DESCRIPTION

Reserved. Reads return 0. Writes have no effect.

PLL multiplier-select

4:0

R/W

PLLM = 00000–00001:

PLLM = 00010:

PLLM = 00011:

PLLM = 00100:

PLLM = 00101:

PLLM = 00110:

PLLM = 00111:

PLLM = 01000:

PLLM = 01001:

PLLM = 01010:

PLLM = 01011:

PLLM = 01100:

PLLM = 01101:

PLLM = 01110:

PLLM = 01111:

PLLM = 10000–11111:

Reserved

Times 2

Times 3

Times 4

Times 5

Times 6

Times 7

Times 8

Times 9

Times 10

Times 11

Times 12

Times 13

Times 14

Times 15

Reserved

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3.9.5.3 PLL Divider 0 Register (PLLDIV0) (Prescaler)

This register controls the value of the PLL prescaler (Divider D0).

15

14

8

0

D0EN

R/W, 1

Reserved

R, 0000000

7

5

4

Reserved

R, 000

PLLDIV0

R/W, 00000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–15. PLL Divider 0 Register Layout (0x1C8A)

Table 3–15. PLL Divider 0 Register Bit Field Description

BIT NAME

D0EN

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

15

R/W

1

Divider D0 enable

D0EN = 0:

D0EN = 1:

Divider 0 disabled

Divider 0 enabled

Reserved

PLLDIV0

14:5

4:0

R

0000000000

00000

Reserved. Reads return 0. Writes have no effect.

Divider D0 ratio

R/W

PLLDIV0 = 00000:

PLLDIV0 = 00001:

PLLDIV0 = 00010:

PLLDIV0 = 00011:

PLLDIV0 = 00100:

PLLDIV0 = 00101:

PLLDIV0 = 00110:

PLLDIV0 = 00111:

PLLDIV0 = 01000:

PLLDIV0 = 01001:

PLLDIV0 = 01010:

PLLDIV0 = 01011:

PLLDIV0 = 01100:

PLLDIV0 = 01101:

PLLDIV0 = 01110:

PLLDIV0 = 01111:

PLLDIV0 = 10000:

PLLDIV0 = 10001:

PLLDIV0 = 10010:

PLLDIV0 = 10011:

PLLDIV0 = 10100:

PLLDIV0 = 10101:

PLLDIV0 = 10110:

PLLDIV0 = 10111:

PLLDIV0 = 11000:

PLLDIV0 = 11001:

PLLDIV0 = 11010:

PLLDIV0 = 11011:

PLLDIV0 = 11100:

PLLDIV0 = 11101:

PLLDIV0 = 11110:

PLLDIV0 = 11111:

Divide by 1

Divide by 2

Divide by 3

Divide by 4

Divide by 5

Divide by 6

Divide by 7

Divide by 8

Divide by 9

Divide by 10

Divide by 11

Divide by 12

Divide by 13

Divide by 14

Divide by 15

Divide by 16

Divide by 17

Divide by 18

Divide by 19

Divide by 20

Divide by 21

Divide by 22

Divide by 23

Divide by 24

Divide by 25

Divide by 26

Divide by 27

Divide by 28

Divide by 29

Divide by 30

Divide by 31

Divide by 32

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3.9.5.4 PLL Divider1 Register (PLLDIV1) for SYSCLK1

This register controls the value of the divider D1 for SYSCLK1. It is in both the BYPASS and PLL paths.

15

14

8

D1EN

R/W, 1

Reserved

R, 0000000

7

5

4

0

Reserved

R, 000

PLLDIV1

R/W, 00011

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–16. PLL Divider 1 Register Layout (0x1C8C)

Table 3–16. PLL Divider 1 Register Bit Field Description

BIT NAME

D1EN

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

15

R/W

1

Divider D1 enable

D1EN = 0:

D1EN = 1:

Divider 1 disabled

Divider 1 enabled

Reserved

PLLDIV1

14:5

4:0

R

0000000000

00011

Reserved. Reads return 0. Writes have no effect.

Divider D1 ratio (SYSCLK1 divider)

R/W

PLLDIV1 = 00000:

PLLDIV1 = 00001:

PLLDIV1 = 00010:

PLLDIV1 = 00011:

Divide by 1

Divide by 2

Reserved

Divide by 4

PLLDIV1 = 00100–11111: Reserved

3.9.5.5 PLL Divider2 Register (PLLDIV2) for SYSCLK2

This register controls the value of the divider D2 for SYSCLK2. It is in both the BYPASS and PLL paths.

15

14

8

D2EN

R/W, 1

Reserved

R, 0000000

7

5

4

0

Reserved

R, 000

PLLDIV2

R/W, 00011

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–17. PLL Divider 2 Register Layout (0x1C8E)

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Table 3–17. PLL Divider 2 Register Bit Field Description

BIT NAME

D2EN

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

15

R/W

1

Divider D2 enable

D2EN = 0:

D2EN = 1:

Divider 2 disabled

Divider 2 enabled

Reserved

PLLDIV2

14:5

4:0

R

0000000000

00011

Reserved. Reads return 0. Writes have no effect.

Divider D2 ratio (SYSCLK2 divider)

R/W

PLLDIV2 = 00000:

PLLDIV2 = 00001:

PLLDIV2 = 00010:

PLLDIV2 = 00011:

Divide by 1

Divide by 2

Reserved

Divide by 4

PLLDIV2 = 00100–11111: Reserved

3.9.5.6 PLL Divider3 Register (PLLDIV3) for SYSCLK3

This register controls the value of the divider D3 for SYSCLK3. It is in both the BYPASS and PLL paths.

15

14

8

D3EN

R/W, 1

Reserved

R, 0000000

7

5

4

0

Reserved

R, 000

PLLDIV3

R/W, 00011

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–18. PLL Divider 3 Register Layout (0x1C90)

Table 3–18. PLL Divider3 Register Bit Field Description

BIT NAME

D3EN

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

15

R/W

1

Divider D3 enable

D3EN = 0:

D3EN = 1:

Divider 3 disabled

Divider 3 enabled

Reserved

PLLDIV3

14:5

4:0

R

0000000000

00011

Reserved. Reads return 0. Writes have no effect.

Divider D3 ratio (SYSCLK3 divider)

R/W

PLLDIV3 = 00000:

PLLDIV3 = 00001:

PLLDIV3 = 00010:

PLLDIV3 = 00011:

Divide by 1

Divide by 2

Reserved

Divide by 4

PLLDIV3 = 00100–11111: Reserved

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3.9.5.7 Oscillator Divider1 Register (OSCDIV1) for CLKOUT3

This register controls the value of the divider OD1 for CLKOUT3. It does not go through the PLL path.

15

14

8

0

OD1EN

R/W, 0

Reserved

R, 0000000

7

5

4

Reserved

R, 000

OSCDIV1

R/W, 00000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–19. Oscillator Divider1 Register Layout (0x1C92)

Table 3–19. Oscillator Divider1 Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Oscillator divider OD1 enable

OD1EN

15

R/W

0

OD1EN = 0:

OD1EN = 1:

Oscillator divider 1 disabled

Oscillator divider 1 enabled

Reserved

OSCDIV1

14:5

4:0

R

0000000000

00000

Reserved. Reads return 0. Writes have no effect.

Divider OD1 ratio (CLKOUT3 divider)

R/W

OSCDIV1 = 00000:

OSCDIV1 = 00001:

OSCDIV1 = 00010:

OSCDIV1 = 00011:

OSCDIV1 = 00100:

OSCDIV1 = 00101:

OSCDIV1 = 00110:

OSCDIV1 = 00111:

OSCDIV1 = 01000:

OSCDIV1 = 01001:

OSCDIV1 = 01010:

OSCDIV1 = 01011:

OSCDIV1 = 01100:

OSCDIV1 = 01101:

OSCDIV1 = 01110:

OSCDIV1 = 01111:

OSCDIV1 = 10000:

OSCDIV1 = 10001:

OSCDIV1 = 10010:

OSCDIV1 = 10011:

OSCDIV1 = 10100:

OSCDIV1 = 10101:

OSCDIV1 = 10110:

OSCDIV1 = 10111:

OSCDIV1 = 11000:

OSCDIV1 = 11001:

OSCDIV1 = 11010:

OSCDIV1 = 11011:

OSCDIV1 = 11100:

OSCDIV1 = 11101:

OSCDIV1 = 11110:

OSCDIV1 = 11111:

Divide by 1

Divide by 2

Divide by 3

Divide by 4

Divide by 5

Divide by 6

Divide by 7

Divide by 8

Divide by 9

Divide by 10

Divide by 11

Divide by 12

Divide by 13

Divide by 14

Divide by 15

Divide by 16

Divide by 17

Divide by 18

Divide by 19

Divide by 20

Divide by 21

Divide by 22

Divide by 23

Divide by 24

Divide by 25

Divide by 26

Divide by 27

Divide by 28

Divide by 29

Divide by 30

Divide by 31

Divide by 32

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3.9.5.8 Oscillator Wakeup Control Register (WKEN)

This register controls whether different events in the system are enabled to wake up the device after entering

OSCPWRDN.

15

8

Reserved

R, 00000000

7

5

4

3

2

1

0

Reserved

R, 000

WKEN4

R/W, 1

WKEN3

R/W, 1

WKEN2

R/W, 1

WKEN1

R/W, 1

WKEN0

R/W, 1

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–20. Oscillator Wakeup Control Register Layout (0x1C98)

Table 3–20. Oscillator Wakeup Control Register Bit Field Description

BIT NAME

Reserved

WKEN4

BIT NO.

15:5

4

ACCESS

R

RESET VALUE

00000000000

1

DESCRIPTION

Reserved. Reads return 0. Writes have no effect.

R/W

Input INT3 can wake up the oscillator when the OSCPWRDN bit in

PLLCSR is asserted to logic 1.

WKEN4 = 0: Wake-up enabled. A low-to-high transition on INT3

wakes up the oscillator and clears the OSCPWRDN bit.

WKEN4 = 1: Wake-up disabled. A low-to-high transition on INT3 does

not wake up the oscillator.

WKEN3

WKEN2

WKEN1

WKEN0

3

2

1

0

R/W

1

Input INT2 can wake up the oscillator when the OSCPWRDN bit in

PLLCSR is asserted to logic 1.

WKEN3 = 0: Wake-up enabled. A low-to-high transition on INT2

wakes up the oscillator and clears the OSCPWRDN bit.

WKEN3 = 1: Wake-up disabled. A low-to-high transition on INT2 does

not wake up the oscillator.

Input INT1 can wake up the oscillator when the OSCPWRDN bit in

PLLCSR is asserted to logic 1.

WKEN2 = 0: Wake-up enabled. A low-to-high transition on INT1

wakes up the oscillator and clears the OSCPWRDN bit.

WKEN2 = 1: Wake-up disabled. A low-to-high transition on INT1 does

not wake up the oscillator.

Input INT0 can wake up the oscillator when the OSCPWRDN bit in

PLLCSR is asserted to logic 1.

WKEN1 = 0: Wake-up enabled. A low-to-high transition on INT0

wakes up the oscillator and clears the OSCPWRDN bit.

WKEN1 = 1: Wake-up disabled. A low-to-high transition on INT0

does not wake up the oscillator.

Input NMI can wake up the oscillator when the OSCPWRDN bit in

PLLCSR is asserted to logic 1.

WKEN0 = 0: Wake-up enabled. A low-to-high transition on NMI

wakes up the oscillator and clears the OSCPWRDN bit.

WKEN0 = 1: Wake-up disabled. A low-to-high transition on NMI

does not wake up the oscillator.

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3.9.5.9 CLKOUT3 Select Register (CK3SEL)

This register controls which clock is output onto the CLKOUT3 so that it may be used to test and debug

the PLL (in addition to its normal function of being a direct input clock divider). Modes other than

CK3SEL = 1011 are intended for debug use only and should not be used during normal operation.

15

8

Reserved

R, 00000000

7

4

3

0

Reserved

R, 0000

CK3SEL

R/W, 1011

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–21. CLKOUT3 Select Register Layout (0x1C82)

Table 3–21. CLKOUT3 Select Register Bit Field Description

BIT NAME

Reserved

CK3SEL

BIT NO.

15:4

ACCESS

R

RESET VALUE

000000000000

1011

DESCRIPTION

Reserved. Reads return 0. Writes have no effect.

†

3:0

R/W

Output on CLK3SEL pin

CK3SEL = 1001

CK3SEL = 1010

CK3SEL = 0000–0111

CLKOUT3 becomes point A in Figure 3–12

CLKOUT3 becomes point B in Figure 3–12

CLKOUT3 becomes oscillator divider output

in Figure 3–12

CK3SEL = 1011

CK3SEL = Other

CLKOUT3 becomes point C in Figure 3–12

Not supported

†

The different options for the CLKOUT3 signal are intended for test purposes; it is recommended that the CK3SEL bits of the CK3SEL register

be kept at their default value of ‘1011b’ during normal operation.

3.9.5.10 CLKOUT Selection Register (CLKOUTSR)

As described in Section 3.9.2, Clock Groups, the 5502 has different clock groups, each of which can be driven

by a clock that is different from the CPU clock. The CLKOUT Selection Register determines which clock signal

is reflected on the CLKOUT pin.

15

8

Reserved

R, 00000000

7

3

2

1

0

Reserved

R, 00000

CLKOSEL

R/W, 01

CLKOUTDIS

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–22. CLKOUT Selection Register Layout (0x8400)

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Table 3–22. CLKOUT Selection Register Bit Field Description

BIT NAME

Reserved

BIT NO.

ACCESS

R

RESET VALUE

DESCRIPTION

15–3

0000000000000 Reserved

CLKOSEL

2:1

R/W

01

CLKOUT source-select

CLKOSEL = 00:

CLKOSEL = 01:

CLKOSEL = 10:

CLKOSEL = 11:

Reserved

CLKOUT source is SYSCLK1

CLKOUT source is SYSCLK2

CLKOUT source is SYSCLK3

CLKOUTDIS

0

R/W

0

Disable CLKOUT

CLKOUTDIS = 0: CLKOUT enabled

CLKOUTDIS = 1: CLKOUT disabled (driving 0)

3.9.5.11 Clock Mode Control Register (CLKMD)

15

8

Reserved

R, 00000000

7

1

0

Reserved

CLKMD0

R/W, GPIO4

state at reset

R, 0000000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–23. Clock Mode Control Register Layout (0x8C00)

Table 3–23. Clock Mode Control Register Bit Field Description

BIT NAME

Reserved

CLKMD0

BIT NO.

15–1

0

ACCESS

R

RESET VALUE

DESCRIPTION

000000000000000

Reserved

R/W

GPIO4 state at reset Clock output source-select

CLKMD0 = 0: OSCOUT is selected as clock input source

CLKMD0 = 1: X2/CLKIN is selected as clock input source

3.9.6 Reset Sequence

When RESET is low, the clock generator is in bypass mode with the input clock set to CLKIN or X2/CLKIN,

dependent upon the state of GPIO4. After the RESET pin transitions from low to high, the following events

will occur in the order listed below.

•

GPIO6 and GPIO7 are sampled on the rising edge of the reset signal. The state of GPIO6 and GPIO7

determines the function of the multiplexed pins of the 5502, see Section 3.3, Configurable External Ports

and Signals, for more information on pin multiplexing. The state of GPIO6 and GPIO7 during the rising

edge of reset determines the values for the Parallel/Host Port Mux Mode and the Serial Port 2 Mux Mode

bits, respectively, of the External Bus Control Register (XBSR).

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•

GPIO4 is sampled on the rising edge of the reset signal to set the state of the CLKMD0 bit of the Clock

Mode Control Register (CLKMD), which in turns, determines the clock source for the DSP. The CLKMD0

bit selects either the internal oscillator output (OSCOUT) or the X2/CLKIN pin as the input clock source

for the DSP. If GPIO4 is low at reset, the CLKMD0 bit will be set to 0 and the internal oscillator and the

external crystal generate the input clock for the DSP. If GPIO4 is high, the CLKMD0 bit will be set to 1 and

the input clock will be taken directly from the X2/CLKIN pin.

After the reset signal transitions from low to high, the DSP will not be taken out of reset immediately.

Instead, an internal counter will count 41032 clock cycles to allow the internal oscillator to stabilize (only

if GPIO4 was low). The internal counter will also add 70 reference clock cycles to allow the reset signal

to propagate through different parts of the device.

•

After all internal delay cycles have expired, the BOOTM[2:0] pins will be sampled and their values will be

storedintheBootModeRegister(BOOTM_MODE). ThevalueintheBOOTM_MODEregisterwillbeused

by the bootloader to determine the boot mode of the DSP.

Program flow will commence after all internal delay cycles have expired.

The 5502 has internal circuitry that will count down 70 reference clock cycles to allow reset signals to

propagate correctly to all parts of the device after reset (RESET pin goes high). Furthermore, the 5502 also

has internal circuitry that will count down 41,032 reference clock cycles to allow the oscillator input to become

stable after waking up from power-down state or reset. If a reset is asserted, program flow will start after all

stabilization periods have expired; this includes the oscillator stabilization period only if GPIO4 is low at reset.

If the oscillator is coming out of power-down mode, program flow will start immediately after the oscillator

stabilization period has completed. Table 3–24 summarizes the number of reference clock cycles needed

before program flow begins.

Table 3–24. Number of Reference Clock Cycles Needed Until Program Flow Begins

CONDITION

Oscillator Not Used (GPIO4 = 1)

Oscillator Used (GPIO4 = 0)

REFERENCE CLOCK CYCLES

70

After Reset

41,102

41,032

After Oscillator Power-Down

All output (O/Z) and input/output (I/O/Z) pins (except for CLKOUT, ECLKOUT2, and XF) will go into

high-impedance mode during reset and will come out of high-impedance mode when the stabilization periods

have expired. All output (O/Z) and input/output (I/O/Z) pins will retain their value when the device enters a

power-down mode such as IDLE3 mode.

3.10 Idle Control

The Idle function is implemented for low power consumption. The Idle function achieves low power

consumption by gating the clock to unused parts of the chip, and/or setting the clock generator (PLL) and the

internal oscillator to a power-down mode.

3.10.1 Clock Domains

The 5502 provides six clock domains to power-off the main clock to the portions of the device that are not being

used. The six domains are:

•

CPU Domain

Master Port Domain (includes DMA and HPI modules)

ICACHE

Peripherals Domain

Clock Generator Domain

EMIF Domain

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Functional Overview

3.10.2 IDLE Procedures

Before entering idle mode (executing the IDLE instruction), the user has first to determine which part of the

system needs to be disabled and then program the Idle Control Register (ICR) accordingly. When the IDLE

instructionisexecuted, theICRwillbecopiedintotheIdleStatusRegister(ISTR). ThedifferentbitsoftheISTR

register will be propagated to disable the chosen domains. Special care has to be taken in programming the

ICR as some IDLE domain combinations are not valid (for example: CPU on and clock generator off).

3.10.2.1 CPU Domain Idle Procedure

The 5502 CPU can be idled by executing the following procedure.

1. Write ‘1’ to the CPUI bit (bit 0 of ICR).

2. Execute the IDLE instruction.

3. CPU will go to idle state

3.10.2.2 Master Port Domain (DMA/HPI) Idle Procedure

The clock to the DMA module and/or the HPI module will be stopped when the DMA and/or the HPI bit in the

MICR is set to 1 and the MPIS bit in the ISTR becomes 1. The DMA will go into idle immediately if there is no

data transfer taking place. If there is a data transfer taking place, then it will finish the current transfer and then

go into idle. The HPI will go into idle regardless of whether or not there is a data transfer taking place. Software

must confirm that the HPI has no activity before setting it to idle.

The 5502 DMA module and the HPI module can be disabled by executing the following procedure.

1. Write ‘1’ to the DMA bit and/or the HPI bit in MICR.

2. Write ‘1’ to the MPI bit in ICR.

3. Execute the IDLE instruction.

4. DMA and/or HPI go/goes to idle.

3.10.2.3 Peripheral Modules Idle Procedure

The clock to the modules included in the Peripherals Domain will be stopped when their corresponding bit in

the PICR is set to 1 and the PERIS bit in the ISTR becomes 1. Each module in this domain will go into idle

immediately if it has no activity. If the module being set to idle has activity, it will wait until the activity completes

before going into idle.

Each peripheral module can be idled by executing the following procedure.

1. Write ‘1’ to the corresponding bit in PICR for each peripheral to be idled.

2. Write ‘1’ to the PERI bit in ICR.

3. Execute the IDLE instruction.

4. Every peripheral with its corresponding PICR bit set will go to idle.

3.10.2.4 EMIF Module Idle Procedure

The 5502 EMIF can be idled in one of two ways: through the ICR and through the PICR. The EMIF will go into

idle immediately if there is no data transfer taking place within the DMA. If there is a data transfer taking place,

then the EMIF will wait until the DMA finishes the current transfer and goes into idle before going into idle itself.

Please note that while the EMIF is in idle, the SDRAM refresh function of the EMIF will not be available.

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The 5502 EMIF can be idled through the ICR only when the following modules are set to idle: CPU, I-Port,

ICACHE, DMA, and HPI. To place the EMIF in idle using the ICR, execute the following procedure:

1. Write ‘1’ to the DMA and HPI bits in MICR.

2. Write ‘1’ to the CPUI, MPI, ICACHEI, EMIFI, and IPORTI bits in ICR.

3. Execute the IDLE instruction.

4. EMIF and all modules listed in Step 2 will go to idle.

The 5502 EMIF can also be idled through the PICR. To place the EMIF in idle using the PICR, execute the

following procedure:

1. Write a ‘1’ to the EMIF bit in PICR.

2. Write a ‘1’ to the PERI bit in ICR.

3. Execute IDLE instruction.

4. EMIF will go to IDLE.

3.10.2.5 IDLE2 Mode

In IDLE2 mode, all modules except the CLOCK module are set to idle state. To place the 5502 in IDLE2 mode,

perform the following steps.

1. Write a ‘1’ to all peripheral module bits in the PICR.

2. Write a ‘1’ to the HPI and DMA bits in MICR.

3. Write a ‘1’ to all domain bits in the ICR except the CLOCK domain bit (CLKI).

4. Execute the IDLE instruction.

5. All internal clocks will be disabled, the CLOCK module will remain active.

3.10.2.6 IDLE3 Mode

In IDLE3 mode, all modules (including the CLOCK module) are set to idle state. To place the 5502 in IDLE3

mode, perform the following steps.

1. Clear (i.e., set to ‘0’) the PLLEN bit in PLLCSR to place the PLL in bypass mode.

2. Set the PLLPWRDN and PLLRST bits in PLLCSR to ‘1’.

3. Write a ‘1’ to all peripheral module bits in PICR.

4. Write a ‘1’ to the HPI and DMA bits in MICR.

5. Write a ‘1’ to all domain bits in ICR.

6. Execute the IDLE instruction.

7. PLL core is set to power-down mode and all internal clocks are disabled.

3.10.2.7 IDLE3 Mode With Internal Oscillator Disabled

In this state, all modules (including the CLOCK module) are set to the idle state and the internal oscillator is

set to the power-down mode. This is the lowest power-consuming state that 5502 can be placed under.

1. Clear (i.e., set to ‘0’) the PLLEN bit in PLLCSR to place the PLL in bypass mode.

2. Set the PLLPWRDN, PLLRST, and OSCPWRDN bits in PLLCSR to ‘1’.

3. Set the WKEN register to specify which event will wake up internal oscillator [e.g., set bit 1 to have

†

interrupt 0 (INT0) wake up the oscillator].

†

External interrupt being used must be enabled through IER prior to setting the 5502 to IDLE.

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4. Write a ‘1’ to all peripheral module bits in the PICR.

5. Write a ‘1’ to the HPI and DMA bits in MICR.

6. Write a ‘1’ to all domain bits in the ICR.

7. Execute the IDLE instruction.

8. Internal oscillator is set to power-down mode, PLL core is set to power-down mode, and all internal clocks

are disabled.

3.10.3 Module Behavior at Entering IDLE State

All transactions must be completed before entering the IDLE state. Table 3–25 lists the behavior of each

module before entering the IDLE state.

Table 3–25. Peripheral Behavior at Entering IDLE State

MODULE BEHAVIOR AT ENTERING IDLE STATE

CLOCK DOMAIN

MODULES

(ASSUMING THE IDLE CONTROL IS SET)

CPU

Enter IDLE after CPU stops pipeline.

Interrupt Controller

IDLE Controller

PLL Controller

Enter IDLE after CPU stops.

CPU

Enter IDLE state after current DMA transfer to internal memory, EMIF, or

peripheral, or enter IDLE state immediately if no transfer exists.

DMA

Master Port

ICACHE

DMA has function of Auto-wakeup/Idle with McBSP data transfer during

IDLE.

HPI

Enter IDLE state immediately. Software has to take care of HPI activity.

Enter IDLE state after current data transfer from EMIF or program fetch

from CPU finishes, or enter IDLE state immediately if no transfer and no

access exist.

ICACHE

External Bus Selection Register Enter IDLE after CPU stops.

Timer Signal Selection Register Enter IDLE after CPU stops.

CLKOUT Selection Register

External Bus Control Register

Clock Mode Control Register

Timer0/1 and WDT

Enter IDLE after CPU stops.

Enter IDLE state immediately

DSP/BIOS Timer

External Clock and Frame:

Enter IDLE state after current McBSP activity is finished or enter IDLE

state immediately if no activity exists. McBSP has function of

Auto-wakeup/Idle with DMA transfer during IDLE.

Peripheral

MCBSP0/1/2

Internal Clock and Frame:

Enter IDLE state immediately if both transmitter and receiver are in reset

(XRST = 0 and RRST = 0). IDLE state not entered otherwise.

GPIO

I2C

Enter IDLE state immediately.

2

Enter IDLE state after current I C activity is finished or enter IDLE state

immediately if no activity exists.

EnterIDLEstateaftercurrentUARTactivityisfinishedorenterIDLEstate

immediately if no activity exists.

UART

Parallel GPIO

PLL divider

PLL core

Enter IDLE state immediately.

Power-down state if set by software before IDLE

Clock Generator

EMIF

Oscillator

Enter IDLE mode after current DMA transfer or enter IDLE mode

immediately if no activity exists.

EMIF

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Functional Overview

3.10.4 Wake-Up Procedure

It is the user’s responsibility to ensure that there exists a valid wake-up procedure before entering idle mode.

Keep in mind that a hardware reset will restore all modules to their active state. All wake-up procedures are

described in the next sections.

3.10.4.1 CPU Domain Wake-up Procedure

The CPU domain can be taken out of idle though an enabled external interrupt or an NMI signal. External

interrupts can be enabled through the use of the IER0 and IER1 registers. Other modules, such as the EMIF

module, will be taken out of idle automatically when the CPU wakes up. Please see the wake-up procedures

for other modules for more information.

3.10.4.2 Master Port Domain (DMA/HPI) Wake-up Procedure

The 5502 DMA module and the HPI module can be taken out of idle simultaneously by executing the following

procedure.

1. Write ‘0’ to the MPI bit in ICR.

2. Execute the IDLE instruction.

3. DMA and HPI wake up.

It is also possible to wake up the DMA and HPI modules individually through the use of the Master Idle Control

Register. To wake up only the DMA or the HPI module, perform the following steps:

1. Write ‘0’ to the DMA bit or the HPI bit in MICR.

2. Selected module wakes up.

3.10.4.3 Peripheral Modules Wake-up Procedure

All 5502 peripherals can be taken out of idle simultaneously by executing the following procedure.

1. Write ‘0’ to the PERI bit in ICR.

2. Execute the IDLE instruction.

3. All idled peripherals wake up.

It is also possible to wake up individual peripherals through the use of the Peripheral Idle Control Register by

executing the following procedure.

1. Write ‘0’ to the idle control bit of peripheral(s) in PICR.

2. Idled peripherals with ‘0’ in PICR wake up.

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3.10.4.4 EMIF Module Wake-up Procedure

If both the CPU and the EMIF are in idle, then the EMIF will come out of idle when the CPU is taken out of

idle. The CPU can be taken out of idle through the use of an NMI or an enabled external interrupt. External

interrupts can be enabled through the IER0 and IER1 registers.

If the CPU is not in idle, then the EMIF can be taken out of idle through either of the following two procedures:

1. Write ‘0’ to the PERI bit in ICR.

2. Execute the IDLE instruction.

3. All idled peripherals, including the EMIF, wake up.

Or:

1. Write ‘0’ to the EMIF bit in PICR.

2. The EMIF module will wake up.

3.10.4.5 IDLE2 Mode Wake-up Procedure

The 5502 can be taken completely out of IDLE2 mode by executing the following procedure.

1. CPU wakes up from idle through NMI or enabled external interrupt.

2. Write ‘0’ to all bits in the ICR.

3. Execute the IDLE instruction.

4. All internal clocks are enabled and all modules come out of idle.

3.10.4.6 IDLE3 Mode Wake-up Procedure

The 5502 can be taken completely out of IDLE3 mode by executing the following procedure.

1. CPU wakes up from idle through NMI or enabled external interrupt.

2. Write ‘0’ to all bits in the ICR.

3. Execute the IDLE instruction.

4. All internal clocks are enabled and all modules come out of idle.

5. Write ‘0’ to the PLLPWRDN and PLLRST bits in PLLCSR.

6. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt.

7. Set the PLLEN bit in PLLCSR to ‘1’.

8. All internal clocks will now come from the PLL core.

NOTE: Step 3 can be modified to only wake up certain modules, see previous sections for

more information on the wake-up procedures for the 5502 modules.

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Functional Overview

3.10.4.7 IDLE3 Mode With Internal Oscillator Disabled Wake-up Procedure

The internal oscillator of the 5502 will be woken up along with the CLOCK module through an NMI or an

enabledexternalinterrupt. Thesource(INT0, INT1, INT2, INT3, orNMI)forthewake-upsignalcanbeselected

through the use of the WKEN register. The maskable external interrupts must be enabled through IER0 and

IER1 prior to setting the 5502 to Idle 3 mode.

The 5502 has internal circuitry that will count down a predetermined number of clock cycles (41,032 reference

clock cycles) to allow the oscillator input to become stable after waking up from power-down state or reset.

When waking up from idle mode, program flow will start after the stabilization period of the oscillator has

expired (41032 reference clock cycles).

To take the 5502 (including the internal oscillator) out of the idle 3 state, execute the following procedure:

1. External interrupt or NMI occurs (as specified in the WKEN register) and program flow begins after

41,032 reference clock cycles.

2. CPU wakes up.

3. Write ‘0’ to all bits in the ICR.

4. Execute the IDLE instruction.

5. All internal clocks are enabled and all modules come out of idle.

6. Write ‘0’ to the PLLPWRDN, PLLRST, and OSCPWRDN bits in PLLCSR.

7. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt.

8. Set the PLLEN bit in PLLCSR to ‘1’.

9. All internal clocks will now come from the PLL core.

NOTE: Step 2 can be modified to only wake up certain modules, see previous sections for

more information on the wake-up procedures for the 5502 modules.

3.10.4.8 Summary of Wake-up Procedures

Table 3–26 summarizes the wake-up procedures.

Table 3–26. Wake-Up Procedures

ICR

AFTER

WAKE-UP

ISTR

AFTER

WAKE-UP

ISTR

VALUE

CLOCK DOMAIN

STATUS

EXIT FROM IDLE

xxx0xxx0

xxx0xxx1

xxx11111

CPU – ON

Clock Generator – ON

Other – ON/OFF

1. DSP software modifies ICR

and executes “IDLE”

instruction

1. Modified value

1. Updated to ICR modified

value after “IDLE”

instruction

2. Reset

2. All “0”

CPU – OFF

Clock Generator – ON

Other – ON/OFF

1. Unmasked interrupt from

external or on-chip module

1. Not modified

1. CPUIS, CLKIS, and

EMIFIS/XPORTIS/IPORTIS

are set to “0”

2. Reset

2. All “0”

CPU – OFF

Clock Generator – OFF

Other – OFF

1. Unmasked interrupt from

external

1. Not modified

1. CPUIS, CLKIS, and

EMIFIS/XPORTIS/IPORTIS

are set to “0”

2. Reset

2. All “0”

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Functional Overview

3.10.5 Auto-Wakeup/Idle Function for McBSP and DMA

The 5502 has an Auto-wakeup/Idle function for McBSP to DMA to on-chip memory data transfers when the

DMA and the McBSP are both set to IDLE. In the case that the McBSP is set to external clock mode and the

McBSP and the DMA are set to idle, the McBSP and the DMA can wake up from IDLE state automatically if

the McBSP gets a new data transfer. The McBSP and the DMA enter the idle state automatically after data

transfer is complete. [The clock generator (PLL) should be active and the PLL core should not be in

power-down mode for the Auto-wakeup/Idle function to work.]

3.10.6 Clock State of Multiplexed Modules

The clock to the McBSP2, UART, and EMIF modules is disabled automatically when these modules are not

selected through the External Bus Selection Register (XBSR). Note that any accesses to disabled modules

will result in a bus error.

3.10.7 IDLE Control and Status Registers

The clock domains are controlled by the IDLE Configuration Register (ICR) that allows the user to place

different parts of the device in Idle mode. The IDLE Status Register (ISTR) reflects the portion of the device

that remains active. The peripheral domain is controlled by the Peripheral IDLE Control Register (PICR). The

Peripheral IDLE Status Register (PISTR) reflects the portion of the peripherals that are in the IDLE state. The

PLL Control/Status Register (PLLCSR) is used to power down the PLL core when the IDLE instruction is

executed.

Table 3–27. Clock Domain Memory-Mapped Registers

ADDRESS

0x0001

0x0002

0x9400

0x9401

0x9402

0x9403

REGISTER NAME

IDLE Configuration Register (ICR)

IDLE Status Register (ISTR)

Peripheral IDLE Control Register (PICR)

Peripheral IDLE Status Register (PISTR)

Master IDLE Control Register (MICR)

Master IDLE Status Register (MISR)

3.10.7.1 IDLE Configuration Register (ICR)

15

9

8

Reserved

IPORTI

R/W, 0

R, 0000000

7

6

5

4

3

2

1

0

MPORTI

R/W, 0

XPORTI

R/W, 0

EMIFI

R/W, 0

CLKI

R/W, 0

PERI

R/W, 0

ICACHEI

R/W, 0

MPI

CPUI

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–24. IDLE Configuration Register Layout (0x0001)

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Table 3–28. IDLE Configuration Register Bit Field Description

BIT NAME

Reserved

IPORTI

BIT NO.

15–9

8

ACCESS

R

RESET VALUE

DESCRIPTION

0000000

0

Reserved

IPORT idle control bit. The IPORT is used for all ICACHE transactions.

R/W

IPORTI = 0:

IPORTI = 1:

IPORT remains active after execution of an IDLE

instruction

IPORT is disabled after execution of an IDLE instruction

MPORTI

XPORTI

EMIFI

7

6

5

4

R/W

0

MPORT idle control bit. The MPORT is used for all DMA transactions.

MPORTI = 0:

MPORTI = 1:

MPORT remains active after execution of an IDLE

instruction

MPORT is disabled after execution of an IDLE

instruction

XPORT idle control bit. The XPORT is used for all I/O memory

transactions.

XPORTI = 0:

XPORTI = 1:

XPORT remains active after execution of an IDLE

instruction

XPORT is disabled after execution of an IDLE instruction

External Memory Interface (EMIF) idle control bit

EMIFI = 0:

EMIFI = 1:

EMIF module remains active after execution of an

IDLE instruction

EMIF module is disabled after execution of an IDLE

instruction

CLKI

Device clock generator idle control bit

CLKI = 0:

CLKI = 1:

Device clock generator module remains active after

execution of an IDLE instruction.

Device clock generator is disabled after execution of an

IDLE instruction. Disabling the clock generator provides

the lowest level of power reduction by stopping the

system clock. When CLKI is set to 1, the CPUI and DPI

bits will be set to 1 in order to ensure a proper

power-down mode.

PERI

3

2

1

0

R/W

0

Peripheral Idle control bit

PERI = 0:

PERI = 1:

All peripheral modules become/remain active after

execution of an IDLE instruction

All peripheral modules with 1 in PICR are disabled after

execution of an IDLE instruction

ICACHEI

ICACHE idle control bit

ICACHEI = 0:

ICACHEI = 1:

ICACHE module remains active after execution of an

IDLE instruction

ICACHE module is disabled after execution of an IDLE

instruction

MPI

Master peripheral (DMA and HPI) idle control bit

MPI = 0:

MPI = 1:

DMA and HPI modules remain active after execution of

an IDLE instruction

DMA and HPI modules are disabled after execution of

an IDLE instruction

CPUI

CPU idle control bit

CPUI = 0:

CPUI = 1:

CPU module remains active after execution of an IDLE

instruction

CPU module is disabled after execution of an IDLE

instruction

NOTE: For example, writing xxx000001b into the ICR does not indicate that the CPU domain is in IDLE mode; rather, it indicates that after the

IDLE instruction, the CPU domain will be in IDLE mode.

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3.10.7.2 IDLE Status Register (ISTR)

15

9

8

Reserved

IPORTIS

R, 0

R, 0000000

7

6

5

4

3

2

1

0

MPORTIS

R, 0

XPORTIS

R, 0

EMIFIS

R, 0

CLKIS

R, 0

PERIS

R, 0

ICACHEIS

R, 0

MPIS

R, 0

CPUIS

R, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–25. IDLE Status Register Layout (0x0002)

Table 3–29. IDLE Status Register Bit Field Description

BIT NAME

Reserved

IPORTIS

BIT NO.

15–9

8

ACCESS

RESET VALUE

DESCRIPTION

R

0000000

0

Reserved

IPORT idle status bit. The IPORT is used for all ICACHE transactions.

IPORTIS = 0:

IPORTIS = 1:

IPORT is active

IPORT is disabled

MPORTIS

XPORTIS

EMIFIS

CLKIS

7

6

5

4

3

2

1

0

R

0

MPORT idle status bit. The MPORT is used for all DMA transactions.

MPORTIS = 0: MPORT is active

MPORTIS = 1: MPORT is disabled

XPORT idle status bit. The XPORT is used for all I/O memory transactions.

XPORTIS = 0: XPORT is active

XPORTIS = 1: XPORT is disabled

External Memory Interface (EMIF) idle status bit

EMIFIS = 0:

EMIFIS = 1:

EMIF module is active

EMIF module is disabled

Device clock generator idle status bit

CLKIS = 0:

CLKIS = 1:

Device clock generator module is active

Device clock generator is disabled

PERIS

Peripheral idle status bit

PERIS = 0:

PERIS = 1:

All peripheral modules are active

All peripheral modules are disabled

ICACHEIS

MPIS

ICACHE idle status bit

ICACHEIS = 0: ICACHE module is active

ICACHEIS = 1: ICACHE module is disabled

DMA and HPI idle status bit

MPIS = 0:

MPIS = 1:

DMA and HPI modules are active

DMA and HPI modules are disabled

CPUIS

CPU idle status bit

CPUIS = 0:

CPUIS = 1:

CPU module is active

CPU module is disabled

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Functional Overview

3.10.7.3 Peripheral IDLE Control Register (PICR)

15

14

13

12

11

10

9

8

Reserved

R, 00

MISC

R/W, 0

EMIF

R/W, 0

BIOST

R/W, 0

WDT

R/W, 0

PIO

URT

R/W, 0

7

6

ID

5

IO

4

3

2

1

0

I2C

SP2

SP1

SP0

TIM1

R/W, 0

TIM0

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–26. Peripheral IDLE Control Register Layout (0x9400)

Table 3–30. Peripheral IDLE Control Register Bit Field Description

BIT NAME

Reserved

MISC

BIT NO.

ACCESS

R

RESET VALUE

DESCRIPTION

15–14

00

0

Reserved

MISC bit

†

13

R/W

MISC = 0:

MISC = 1:

Miscellaneous modules remain active when

ISTR.PERIS = 1 and IDLE instruction is executed.

MIscellaneous module is disabled when

ISTR.PERIS = 1 and IDLE instruction is executed.

Miscellaneous modules include the XBSR, TIMEOUT Error Register,

XBCR, Timer Signal Selection Register, CLKOUT Select Register,

and Clock Mode Control Register.

†

12

EMIF

BIOST

WDT

PIO

R/W

0

EMIF bit

EMIF = 0:

EMIF = 1:

EMIF module remains active when ISTR.PERIS = 1

and IDLE instruction is executed.

EMIF module is disabled when ISTR.PERIS = 1 and

IDLE instruction is executed.

†

11

10

BIOS timer bit

BIOST = 0: DSP/BIOS timer remains active when ISTR.PERIS = 1

and the IDLE instruction is executed.

BIOST = 1: DSP/BIOS timer is disabled when ISTR.PERIS = 1 and

the IDLE instruction is executed.

†

Watchdog timer bit

WDT = 0:

WDT = 1:

WDT remains active when ISTR.PERIS = 1

and the IDLE instruction is executed.

WDT is disabled when ISTR.PERIS = 1 and

the IDLE instruction is executed.

†

9

Parallel GPIO timer bit

PIO = 0:

PIO = 1:

Parallel GPIO remains active when ISTR.PERIS = 1

(ISTR.[3]) and the IDLE instruction is executed.

Parallel GPIO is disabled when ISTR.PERIS = 1 and

the IDLE instruction is executed.

†

If the peripheral is already in IDLE, setting PERIS (bit 3 of ISTR) to 0 and executing the IDLE instruction will wake up all peripherals, and PICR

bit settings will be ignored. If PERIS = 1, executing the IDLE instruction will wake up the peripheral if the PICR bit is 0.

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Table 3–30. Peripheral IDLE Control Register Bit Field Description (Continued)

BIT NAME

URT

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

†

8

†

7

†

6

†

5

†

4

†

3

†

2

†

1

†

0

R/W

0

UART timer bit

URT = 0:

URT = 1:

UART remains active when ISTR.PERIS = 1 and

the IDLE instruction is executed.

UART is disabled when ISTR.PERIS = 1 and the IDLE

instruction is executed.

I2C

R/W

0

I2C timer bit

I2C = 0:

2

I C remains active when ISTR.PERIS = 1 and

the IDLE instruction is executed.

I C is disabled when ISTR.PERIS = 1 and the IDLE

instruction is executed.

2

I2C = 1:

ID

ID timer bit

ID = 0:

ID remains active when ISTR.PERIS = 1 and the

IDLE instruction is executed.

ID is disabled when ISTR.PERIS = 1 and the IDLE

ID = 1:

instruction is executed.

IO

IO timer bit

IO = 0:

GPIO remains active when ISTR.PERIS = 1 and

the IDLE instruction is executed.

GPIO is disabled when ISTR.PERIS = 1 and the IDLE

IO = 1:

instruction is executed.

SP2

SP1

SP0

TIM1

TIM0

McBSP2 timer bit

SP2 = 0:

SP2 = 1:

McBSP2 remains active when ISTR.PERIS = 1

and the IDLE instruction is executed.

McBSP2 is disabled when ISTR.PERIS = 1 and the

IDLE instruction is executed.

McBSP1 timer bit

SP1 = 0:

SP1 = 1:

McBSP1 remains active when ISTR.PERIS = 1

and the IDLE instruction is executed.

McBSP1 is disabled when ISTR.PERIS = 1 and the

IDLE instruction is executed.

McBSP0 timer bit

SP0 = 0:

SP0 = 1:

McBSP0 remains active when ISTR.PERIS = 1

and the IDLE instruction is executed.

McBSP0 is disabled when ISTR.PERIS = 1 and the

IDLE instruction is executed.

TIMER1 timer bit

TIM1 = 0:

TIM1 = 1:

TIMER1 remains active when ISTR.PERIS = 1

and the IDLE instruction is executed.

TIMER1 is disabled when ISTR.PERIS = 1 and the

IDLE instruction is executed.

TIMER0 timer bit

TIM0 = 0:

TIM0 = 1:

TIMER0 remains active when ISTR.PERIS = 1

and the IDLE instruction is executed.

TIMER0 is disabled when ISTR.PERIS = 1 and the

IDLE instruction is executed.

†

If the peripheral is already in IDLE, setting PERIS (bit 3 of ISTR) to 0 and executing the IDLE instruction will wake up all peripherals, and PICR

bit settings will be ignored. If PERIS = 1, executing the IDLE instruction will wake up the peripheral if the PICR bit is 0.

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Functional Overview

3.10.7.4 Peripheral IDLE Status Register (PISTR)

15

14

13

12

11

10

9

8

Reserved

R, 00

MISC

R, 0

EMIF

R, 0

BIOST

R, 0

WDT

R, 0

PIO

R, 0

URT

R, 0

7

6

5

4

3

2

1

0

I2C

R, 0

ID

IO

SP2

R, 0

SP1

R, 0

SP0

R, 0

TIM1

R, 0

TIM0

R, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–27. Peripheral IDLE Status Register Layout (0x9401)

Table 3–31. Peripheral IDLE Status Register Bit Field Description

BIT NAME

Reserved

MISC

BIT NO.

15–14

13

ACCESS

RESET VALUE

DESCRIPTION

R

00

0

Reserved

MISC bit

MISC = 0:

MISC = 1:

Miscellaneous modules are active

Miscellaneous modules are disabled

Miscellaneous modules include the XBSR, TIMEOUT Error Register,

XBCR, Timer Signal Selection Register, CLKOUT Select Register,

and Clock Mode Control Register.

EMIF

BIOST

WDT

PIO

URT

I2C

12

11

10

9

R

0

EMIF bit

EMIF = 0:

EMIF = 1:

EMIF module is active

EMIF module is disabled

BIOS timer bit

BIOST = 0: DSP/BIOS timer is active

BIOST = 1: DSP/BIOS timer is disabled

Watchdog timer bit

WDT = 0:

WDT = 1:

WDT is active

WDT is disabled

Parallel GPIO timer bit

PIO = 0:

PIO = 1:

Parallel GPIO is active

Parallel GPIO is disabled

8

UART timer bit

URT = 0:

URT = 1:

UART is active

UART is disabled

7

I2C timer bit

2

I2C = 0:

I2C = 1:

I C is active

2

I C is disabled

ID

6

ID timer bit

ID = 0:

ID = 1:

ID is active

ID is disabled

IO

5

IO timer bit

IO = 0:

IO = 1:

GPIO is active

GPIO is disabled

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Table 3–31. Peripheral IDLE Status Register Bit Field Description (Continued)

BIT NAME

SP2

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

4

R

0

McBSP2 timer bit

SP2 = 0:

SP2 = 1:

McBSP2 is active

McBSP2 is disabled

SP1

3

2

1

0

R

0

McBSP1 timer bit

SP1 = 0:

SP1 = 1:

McBSP1 is active

McBSP1 is disabled

SP0

McBSP0 timer bit

SP0 = 0:

SP0 = 1:

McBSP0 is active

McBSP0 is disabled

TIM1

TIM0

TIMER1 timer bit

TIM1 = 0:

TIM1 = 1:

TIMER1 is active

TIMER1 is disabled

TIMER0 timer bit

TIM0 = 0:

TIM0 = 1:

TIMER0 is active

TIMER0 is disabled

3.10.7.5 Master IDLE Control Register (MICR)

15

8

Reserved

R, 00000000

7

2

1

0

Reserved

R, 000000

HPI

DMA

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–28. Master IDLE Control Register Layout (0x9402)

Table 3–32. Master IDLE Control Register Bit Field Description

BIT NAME

Reserved

HPI

BIT NO.

15–2

1

ACCESS

R

RESET VALUE

DESCRIPTION

00000000000000 Reserved

R/W

0

HPI bit

HPI = 0:

HPI = 1:

HPI remains active when ISTR.MPIS becomes 1

HPI is disabled when ISTR.MPIS becomes 1

DMA

0

R/W

DMA bit

DMA = 0:

DMA = 1:

DMA remains active when ISTR.MPIS becomes 1

DMA is disabled when ISTR.MPIS becomes 1

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3.10.7.6 Master IDLE Status Register (MISR)

15

8

Reserved

R, 00000000

7

2

1

0

Reserved

R, 000000

HPI

R, 0

DMA

R, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–29. Master IDLE Status Register Layout (0x9403)

Table 3–33. Master IDLE Status Register Bit Field Description

BIT NAME

Reserved

BIT NO.

15–2

1

ACCESS

RESET VALUE

00000000000000

0

DESCRIPTION

R

Reserved

HPI bit

HPI

HPI = 0:

HPI = 1:

HPI is active

HPI is in IDLE status

DMA

0

R

0

DMA bit

DMA = 0:

DMA = 1:

DMA is active

DMA is in IDLE status

3.11 General-Purpose I/O (GPIO)

The 5502 includes an 8-bit I/O port solely for general-purpose input and output. Several dual-purpose

(multiplexed) pins complement the dedicated GPIO pins. The following sections describe the 8-bit GPIO port

as well as the dual GPIO functions of the Parallel Port Mux and Host Port Mux pins.

3.11.1 General-Purpose I/O Port

The general-purpose I/O port consists of eight individually bit-selectable I/O pins GPIO0 (LSB) through GPIO7

(MSB). The I/O port is controlled using two registers—IODIR and IODATA—that can be accessed by the CPU

or by the DMA, via the peripheral bus controller. The General-Purpose I/O Direction Register (IODIR) is

mapped at address 0x3400, and the General-Purpose I/O Data Register (IODATA) is mapped at address

0x3401.

The GPIO3 and GPIO5 pins are multiplexed with the CLKX2 and FSX2 signals through the SP0 and SP2 pins,

respectively. The function of the SP0 and SP2 pins is determined by the state of the GPIO7 pin during reset.

The SP0 and SP2 pins are set to GPIO3 and GPIO5, respectively, if GPIO7 is low during reset. The SP0 and

SP2 pins are set to CLKX2 and FSX2, respectively, if GPIO7 is high during reset. The function of the SP0 and

SP2 pins will be set once the device is taken out of reset (RESET pin transitions from a low to a high state).

Figure 3–30 and Figure 3–31 show the bit layout of IODIR and IODATA, respectively. Table 3–34 and

Table 3–35 describe the bit fields of these registers.

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3.11.1.1 General-Purpose I/O Direction Register (IODIR)

15

8

Reserved

R, 00000000

7

6

5

4

3

2

1

0

IO7DIR

R/W, 0

IO6DIR

R/W, 0

IO5DIR

R/W, 0

IO4DIR

R/W, 0

IO3DIR

R/W, 0

IO2DIR

R/W, 0

IO1DIR

R/W, 0

IO0DIR

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–30. GPIO Direction Register Layout (0x3400)

Table 3–34. GPIO Direction Register Bit Field Description

†

BIT NAME

Reserved

IOxDIR

BIT NO.

15–8

ACCESS

R

RESET VALUE

00000000

DESCRIPTION

Reserved

Data direction bits that configure the GPIO pins as inputs or outputs.

7–0

R/W

00000000

IOxDIR = 0:

IOxDIR = 1:

Configure corresponding GPIO pin as an input

Configure corresponding GPIO pin as an output

†

x = value from 0 to 7

3.11.1.2 General-Purpose I/O Data Register (IODATA)

15

8

Reserved

R, 00000000

7

6

5

4

3

2

1

0

IO7D

IO6D

IO5D

IO4D

IO3D

IO2D

IO1D

IO0D

R/W, pin

LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.

Figure 3–31. GPIO Data Register Layout (0x3401)

†

Table 3–35. GPIO Data Register Bit Field Description

BIT NAME

Reserved

IOxD

BIT NO.

15–8

ACCESS

R

RESET VALUE

DESCRIPTION

00000000

Reserved

7–0

R/W

Depends on the signal level on Data bits that are used to control the level of the I/O

the corresponding I/O pin

pins configured as outputs and to monitor the level of

the I/O pins configured as inputs.

If IOxDIR = 0, then:

IOxD = 0:

IOxD = 1:

Corresponding GPIO pin is read as a low

Corresponding GPIO pin is read as a

high

If IOxDIR = 1, then:

IOxD = 0:

IOxD = 1:

Set corresponding GPIO pin to low

Set corresponding GPIO pin to high

†

x = value from 0 to 7

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3.11.2 Parallel Port General-Purpose I/O (PGPIO)

Four address pins (A[21:18]), 16 data pins (D[31:16]), 16 control signals (C[15:0]), 8 host data pins (HD[7:0]),

and 2 HPI control pins (HC0, HC1) can be individually enabled as PGPIO when the Parallel/Host Port Mux

Mode bit field of the External Bus Selection Register (XBSR) is cleared for non-multiplexed HPI mode (see

Table 3–36). These pins are controlled by three sets of registers: the PGPIO enable registers, the PGPIO

direction registers, and the PGPIO data registers.

•

The PGPIO enable registers PGPIOEN0–PGPIOEN2 (see Figure 3–32, Figure 3–35, and Figure 3–38)

determine if the pin serves as PGPIO or if it is placed in high-impedance state.

The PGPIO direction registers PGPIODIR0–PGPIODIR2 (see Figure 3–33, Figure 3–36, and

Figure 3–39) determine if the pin is an input or output.

The PGPIO data registers PGPIODAT0–PGPIODAT2 (see Figure 3–34, Figure 3–37, and Figure 3–40)

store the value read or written externally.

NOTE: The enable registers PGPIOENn cannot override the External Bus Selection Register

(XBSR) setting.

Table 3–36. TMS320VC5502 PGPIO Cross-Reference

PARALLEL/HOST PORT MUX MODE = 0

(HPI NON-MULTIPLEX)

PARALLEL/HOST PORT MUX MODE = 1

(FULL EMIF)

EMIF Address Bus

PGPIO[3:0]

EMIF Data Bus

PGPIO[19:4]

EMIF Control Bus

PGPIO20

A[21:18]

D[31:16]

EMIF.A[21:18]

EMIF.D[31:16]

C0

C1

EMIF.ARE/SADS/SDCAS/SRE

EMIF.AOE/SOE/SDRAS

EMIF.AWE/SWE/SDWE

EMIF.ARDY

PGPIO21

C2

PGPIO22

C3

PGPIO23

C4

PGPIO24

EMIF.CE0

C5

PGPIO25

EMIF.CE1

C6

PGPIO26

EMIF.CE2

C7

PGPIO27

EMIF.CE3

C8

PGPIO28

EMIF.BE0

C9

PGPIO29

EMIF.BE1

C10

C11

C12

C13

C14

C15

PGPIO30

EMIF.BE2

PGPIO31

EMIF.BE3

PGPIO32

EMIF.SDCKE

EMIF.SOE3

PGPIO33

PGPIO34

EMIF.HOLD

PGPIO35

EMIF.HOLDA

HPI Data Bus

PGPIO[43:36]

HPI Control Bus

PGPIO44

HD[7:0]

HPI.HD[7:0]

HC0

HC1

HPI.HAS

HPI.HBIL

PGPIO45

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3.11.2.1 Parallel GPIO Enable Register 0 (PGPIOEN0)

15

14

13

12

11

10

9

8

IO15EN

IO14EN

IO13EN

IO12EN

IO11EN

IO10EN

IO9EN

IO8EN

R/W, 0

7

R/W, 0

6

R/W, 0

5

R/W, 0

4

R/W, 0

3

R/W, 0

2

R/W, 0

1

R/W, 0

0

IO7EN

R/W, 0

IO6EN

R/W, 0

IO5EN

R/W, 0

IO4EN

R/W, 0

IO3EN

R/W, 0

IO2EN

R/W, 0

IO1EN

R/W, 0

IO0EN

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–32. Parallel GPIO Enable Register 0 Layout (0x4400)

†

Table 3–37. Parallel GPIO Enable Register 0 Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

IOxEN

15–0

R/W

0000000000000000 Enable or disable GPIO function of the corresponding I/O pins.

See Table 3–36, TMS320VC5502 PGPIO Cross-Reference.

IOxEN = 0:

IOxEN = 1:

GPIO function of corresponding signal is

disabled, i.e., the pin goes into a high-impedance state.

GPIO function of corresponding signal is

enabled, i.e., the signal supports its GPIO function.

†

x = value from 0 to 15

3.11.2.2 Parallel GPIO Direction Register 0 (PGPIODIR0)

15

14

13

12

11

10

9

8

IO15DIR

IO14DIR

IO13DIR

IO12DIR

IO11DIR

IO10DIR

IO9DIR

IO8DIR

R/W, 0

7

R/W, 0

6

R/W, 0

5

R/W, 0

4

R/W, 0

3

R/W, 0

2

R/W, 0

1

R/W, 0

0

IO7DIR

R/W, 0

IO6DIR

R/W, 0

IO5DIR

R/W, 0

IO4DIR

R/W, 0

IO3DIR

R/W, 0

IO2DIR

R/W, 0

IO1DIR

R/W, 0

IO0DIR

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–33. Parallel GPIO Direction Register 0 Layout (0x4401)

Table 3–38. Parallel GPIO Direction Register 0 Bit Field Description

†

BIT NAME

IOxDIR

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

15–0

R/W

0000000000000000 Data direction bits that configure corresponding I/O pins either as

inputs or outputs. See Table 3–36, TMS320VC5502 PGPIO

Cross-Reference.

IOxDIR = 0:

IOxDIR = 1:

Configure corresponding pin as an input.

Configure corresponding pin as an output.

†

x = value from 0 to 15

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3.11.2.3 Parallel GPIO Data Register 0 (PGPIODAT0)

15

14

13

12

11

10

9

8

IO15DAT

IO14DAT

IO13DAT

IO12DAT

IO11DAT

IO10DAT

IO9DAT

IO8DAT

R/W, pin

7

R/W, pin

6

R/W, pin

5

R/W, pin

4

R/W, pin

3

R/W, pin

2

R/W, pin

1

R/W, pin

0

IO7DAT

R/W, pin

IO6DAT

R/W, pin

IO5DAT

R/W, pin

IO4DAT

R/W, pin

IO3DAT

R/W, pin

IO2DAT

R/W, pin

IO1DAT

R/W, pin

IO0DAT

R/W, pin

LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.

Figure 3–34. Parallel GPIO Data Register 0 Layout (0x4402)

†

Table 3–39. Parallel GPIO Data Register 0 Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

IOxDAT

15–0

R/W

Depends on the signal level on Data bits that are used to control the level of the

the corresponding I/O pin

corresponding I/O pins configured as output pins and to

monitor the level of the corresponding I/O pins configured

as input pins. See Table 3–36, TMS320VC5502 PGPIO

Cross-Reference.

If IOxDIR = 0, then:

IOxDAT = 0:

IOxDAT = 1:

Corresponding I/O pin is read as a low

Corresponding I/O pin is read as a high

If IOxDIR = 1, then:

IOxDAT = 0:

IOxDAT = 1:

Set corresponding I/O pin to low

Set corresponding I/O pin to high

†

x = value from 0 to 15

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3.11.2.4 Parallel GPIO Enable Register 1 (PGPIOEN1)

15

14

13

12

11

10

9

8

IO31EN

IO30EN

IO29EN

IO28EN

IO27EN

IO26EN

IO25EN

IO24EN

R/W, 0

7

R/W, 0

6

R/W, 0

5

R/W, 0

4

R/W, 0

3

R/W, 0

2

R/W, 0

1

R/W, 0

0

IO23EN

R/W, 0

IO22EN

R/W, 0

IO21EN

R/W, 0

IO20EN

R/W, 0

IO19EN

R/W, 0

IO18EN

R/W, 0

IO17EN

R/W, 0

IO16EN

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–35. Parallel GPIO Enable Register 1 Layout (0x4403)

Table 3–40. Parallel GPIO Enable Register 1 Bit Field Description

†

BIT NAME

IOxEN

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

15–0

R/W

0000000000000000 Enable or disable GPIO function of the corresponding I/O pins.

See Table 3–36, TMS320VC5502 PGPIO Cross-Reference.

IOxEN = 0:

IOxEN = 1:

GPIO function of corresponding signal is

disabled, i.e., the pin goes into a high-impedance

state.

GPIO function of corresponding signal is

enabled, i.e., the signal supports its GPIO function.

†

x = value from 16 to 31

3.11.2.5 Parallel GPIO Direction Register 1 (PGPIODIR1)

15

14

13

12

11

10

9

8

IO31DIR

IO30DIR

IO29DIR

IO28DIR

IO27DIR

IO26DIR

IO25DIR

IO24DIR

R/W, 0

7

R/W, 0

6

R/W, 0

5

R/W, 0

4

R/W, 0

3

R/W, 0

2

R/W, 0

1

R/W, 0

0

IO23DIR

R/W, 0

IO22DIR

R/W, 0

IO21DIR

R/W, 0

IO20DIR

R/W, 0

IO19DIR

R/W, 0

IO18DIR

R/W, 0

IO17DIR

R/W, 0

IO16DIR

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–36. Parallel GPIO Direction Register 1 Layout (0x4404)

Table 3–41. Parallel GPIO Direction Register 1 Bit Field Description

†

BIT NAME

IOxDIR

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

15–0

R/W

0000000000000000 Data direction bits that configure corresponding I/O pins either as

inputs or outputs. See Table 3–36, TMS320VC5502 PGPIO

Cross-Reference.

IOxDIR = 0:

IOxDIR = 1:

Configure corresponding pin as an input.

Configure corresponding pin as an output.

†

x = value from 16 to 31

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3.11.2.6 Parallel GPIO Data Register 1 (PGPIODAT1)

15

14

13

12

11

10

9

8

IO31DAT

IO30DAT

IO29DAT

IO28DAT

IO27DAT

IO26DAT

IO25DAT

IO24DAT

R/W, pin

7

R/W, pin

6

R/W, pin

5

R/W, pin

4

R/W, pin

3

R/W, pin

2

R/W, pin

1

R/W, pin

0

IO23DAT

R/W, pin

IO22DAT

R/W, pin

IO21DAT

R/W, pin

IO20DAT

R/W, pin

IO19DAT

R/W, pin

IO18DAT

R/W, pin

IO17DAT

R/W, pin

IO16DAT

R/W, pin

LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.

Figure 3–37. Parallel GPIO Data Register 1 Layout (0x4405)

†

Table 3–42. Parallel GPIO Data Register 1 Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

IOxDAT

15–0

R/W

Depends on the signal level on Data bits used to control the level of the corresponding I/O

the corresponding I/O pin

pins configured as output pins and to monitor the level of the

corresponding I/O pins configured as input pins.

See Table 3–36, TMS320VC5502 PGPIO Cross-Reference.

If IOxDIR = 0, then:

IOxDAT = 0:

IOxDAT = 1:

Corresponding I/O pin is read as a low

Corresponding I/O pin is read as a high

If IOxDIR = 1, then:

IOxDAT = 0:

IOxDAT = 1:

Set corresponding I/O pin to low

Set corresponding I/O pin to high

†

x = value from 16 to 31

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3.11.2.7 Parallel GPIO Enable Register 2 (PGPIOEN2)

15

14

13

12

11

10

9

8

Reserved

R/W, 00

IO45EN

IO44EN

IO43EN

IO42EN

IO41EN

IO40EN

R/W, 0

5

R/W, 0

4

R/W, 0

3

R/W, 0

2

R/W, 0

1

R/W, 0

0

7

6

IO39EN

R/W, 0

IO38EN

R/W, 0

IO37EN

R/W, 0

IO36EN

R/W, 0

IO35EN

R/W, 0

IO34EN

R/W, 0

IO33EN

R/W, 0

IO32EN

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–38. Parallel GPIO Enable Register 2 Layout (0x4406)

Table 3–43. Parallel GPIO Enable Register 2 Bit Field Description

†

BIT NAME

Reserved

IOxEN

BIT NO.

15–14

13–0

ACCESS

R/W

RESET VALUE

DESCRIPTION

00

Reserved

R/W

00000000000000 Enable or disable GPIO function of the corresponding I/O pins.

See Table 3–36, TMS320VC5502 PGPIO Cross-Reference.

IOxEN = 0:

IOxEN = 1:

GPIO function of corresponding signal is

disabled, i.e., the pin goes into a high-impedance

state.

GPIO function of corresponding signal is

enabled, i.e., the signal supports its GPIO function.

†

x = value from 32 to 45

3.11.2.8 Parallel GPIO Direction Register 2 (PGPIODIR2)

15

14

13

12

11

10

9

8

Reserved

R/W, 00

IO45DIR

IO44DIR

IO43DIR

IO42DIR

IO41DIR

IO40DIR

R/W, 0

5

R/W, 0

4

R/W, 0

3

R/W, 0

2

R/W, 0

1

R/W, 0

0

7

6

IO39DIR

R/W, 0

IO38DIR

R/W, 0

IO37DIR

R/W, 0

IO36DIR

R/W, 0

IO35DIR

R/W, 0

IO34DIR

R/W, 0

IO33DIR

R/W, 0

IO32DIR

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–39. Parallel GPIO Direction Register 2 Layout (0x4407)

Table 3–44. Parallel GPIO Direction Register 2 Bit Field Description

†

BIT NAME

Reserved

IOxDIR

BIT NO.

15–14

13–0

ACCESS

R/W

RESET VALUE

DESCRIPTION

00

Reserved

R/W

00000000000000 Data direction bits that configure corresponding I/O pins either as

inputs or outputs. See Table 3–36, TMS320VC5502 PGPIO Cross-

Reference.

IOxDIR = 0:

IOxDIR = 1:

Configure corresponding pin as an input.

Configure corresponding pin as an output.

†

x = value from 32 to 45

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Functional Overview

3.11.2.9 Parallel GPIO Data Register 2 (PGPIODAT2)

15

14

13

12

11

10

9

8

Reserved

R/W, 00

IO45DAT

IO44DAT

IO43DAT

IO42DAT

IO41DAT

IO40DAT

R/W, pin

5

R/W, pin

4

R/W, pin

3

R/W, pin

2

R/W, pin

1

R/W, pin

0

7

6

IO39DAT

R/W, pin

IO38DAT

R/W, pin

IO37DAT

R/W, pin

IO36DAT

R/W, pin

IO35DAT

R/W, pin

IO34DAT

R/W, pin

IO33DAT

R/W, pin

IO32DAT

R/W, pin

LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.

Figure 3–40. Parallel GPIO Data Register 2 Layout (0x4408)

†

Table 3–45. Parallel GPIO Data Register 2 Bit Field Description

BIT NAME

Reserved

IOxDAT

BIT NO.

15–14

13–0

ACCESS

R/W

RESET VALUE

DESCRIPTION

00

Reserved

R/W

Depends on the signal level on Data bits used to control the level of the I/O pins

the corresponding I/O pin

configured as output pins, and to monitor the level of the

corresponding I/O pins configured as input pins.

See Table 3–36, TMS320VC5502 PGPIO Cross-

Reference.

If IOxDIR = 0, then:

IOxDAT = 0:

IOxDAT = 1:

Corresponding I/O pin is read as a low

Corresponding I/O pin is read as a high

If IOxDIR = 1, then:

IOxDAT = 0:

IOxDAT = 1:

Set corresponding I/O pin to low

Set corresponding I/O pin to high

†

x = value from 32 to 45

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3.12 External Bus Control Register

The External Bus Control Register is used to disable/enable the bus pullups, pulldowns, and bus holders of

the 5502 pins. Table 3–46 lists which 5502 pins have pullups, pulldowns, and bus holders, and which bit on

the XBCR enables/disables that feature. Please note that for pins with dual functionality (e.g., HC0, HC1, C0,

etc.), the bus holder, pullup, and pulldown feature of each pin can be enabled or disabled regardless of the

function of the pin at the time.

Table 3–46. Pins With Pullups, Pulldowns, and Bus Holders

XBCR CONTROL BIT

TCK

FEATURE

Pullup

TDI

Pullup

TEST

TMS

TRST

EMU1/OFF

EMU0

NMI/WDTOUT

HC0

Pullup

Pulldown

Pullup

EMU

WDT

Pullup

HC

HD

HC1

Pulldown

Bus Holder

Pullup

HD[7:0]

C0

C1

C2

C3

C4

Bus Holder

Pullup

C5

C6

C7

PC

C8

C9

C10

C11

C12

C13

C14

C15

Bus Holder

PD

PA

D[31:0]

A[21:2]

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3.12.1 External Bus Control Register (XBCR)

15

8

Reserved

R, 00000000

7

6

5

4

3

2

1

0

EMU

R/W, 0

TEST

R/W, 0

WDT

R/W, 0

HC

HD

PC

PD

PA

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–41. External Bus Control Register Layout (0x8800)

Table 3–47. External Bus Control Register Bit Field Description

BIT NAME

Reserved

EMU

BIT NO.

15–8

7

ACCESS

R

RESET VALUE

DESCRIPTION

00000000

0

Reserved

EMU bit

R/W

EMU = 0: Pullups on EMU1 and EMU0 pins are enabled.

EMU = 1: Pullups on EMU1 and EMU0 pins are disabled.

TEST

6

R/W

0

TEST bit

TEST = 0: Pullups/pulldowns on test pins are enabled

(does not include EMU1 and EMU0 pins)

TEST = 1: Pullups/pulldowns on test pins are disabled

(does not include EMU1 and EMU0 pins)

WDT

HC

5

4

R/W

0

WDT bit

WDT = 0: Pullup on NMI/WDTOUT pin is enabled

WDT = 1: Pullup on NMI/WDTOUT pin is disabled

HPI control signal bit

HC = 0:

HC = 1:

Pullups/pulldowns on HPI control pins (HC0 and HC1)

are enabled

Pullups/pulldowns on HPI control pins (HC0 and HC1)

are disabled

HD

PC

PD

PA

3

2

1

0

R/W

0

HPI data bus bit

HD = 0:

HD = 1:

Bus holders on HPI data bus (pins HD[7:0]) are enabled

Bus holders on HPI data bus (pins HD[7:0]) are disabled

EMIF control signals

PC = 0:

PC = 1:

Bus holders and pullups on EMIF control pins are enabled

Bus holders and pullups on EMIF control pins are disabled

EMIF data bus signals

PD = 0:

PD = 1:

Bus holders on EMIF data bus (pins D[31:0]) are enabled

Bus holders on EMIF data bus (pins D[31:0]) are disabled

EMIF address bus signals

PA = 0:

PA = 1:

Bus holders on EMIF address bus (pins A[21:2]) are

enabled

Bus holders on EMIF address bus (pins A[21:2]) are

disabled

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3.13 Internal Ports and System Registers

The5502includesthreeinternalportsthatinterfacetheCPUcorewiththeperipheralmodules. Althoughthese

ports cannot be directly controlled by user code, the registers associated with each port can be used to monitor

a number of error conditions that could be generated through illegal operation of the 5502. The port registers

are described in the following sections.

The 5502 also includes two registers that can be used to monitor and control several aspects of the interface

between the CPU and the system-level peripherals, these registers are also described in the following

sections.

3.13.1 XPORT Interface

The XPORT interfaces the CPU core to all peripheral modules. The XPORT will generate bus errors for invalid

accesses to any registers that fall under the ranges shown in Table 3–48. The INTERREN bit of the XPORT

Configuration Register (XCR) controls the bus error feature of the XPORT. The INTERR bit of the XPORT Bus

Error Register (XERR) is set to “1” when an error occurs during an access to a register listed in Table 3–48.

The EBUS and DBUS bits can be used to distinguish whether the error occurred during a write or read access.

Table 3–48. I/O Addresses Under Scope of XPORT

I/O ADDRESS RANGE

0x0000–0x03FF

0x1400–0x17FF

0x2000–0x23FF

The PERITO bit of the XERR is used to indicate that a CPU, DMA, or HPI access to a disabled/idled peripheral

module has generated a time-out error. The time-out error feature is enabled through the PERITOEN bit of

the Time-Out Control Register (TOCR). A time-out error is generated when 512 clock cycles pass without a

response from the peripheral register.

The XPORT can be placed into idle by setting the XPORTI bit of the Idle Control Register (ICR) and executing

the IDLE instruction. When the XPORT is in idle, it will stop accepting new peripheral module requests and

it will also not check for internal I/O bus errors. If there is a request from the CPU core or a peripheral module,

the XPORT will not respond and hang. The ICR register will generate a bus error if the XPORT is idled without

the CPU or Master Port domains being in idle mode.

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Functional Overview

3.13.1.1 XPORT Configuration Register (XCR)

The XPORT Configuration Register bit layout is shown in Figure 3–42 and the bits are described in

Table 3–49.

15

14

8

INTERREN

R/W, 1

Reserved

R, 0000000

7

0

Reserved

R, 00000000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–42. XPORT Configuration Register Layout (0x0100)

Table 3–49. XPORT Configuration Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

INTERREN

15

R/W

1

INTERREN bit

INTERREN = 0: The XPORT will not generate a bus error for

invalid accesses to registers listed in Table 3–48.

Note that any invalid accesses to these registers

will hang the pipeline.

INTERREN = 1: The XPORT will generate a bus error for invalid

†

accesses to registers listed in Table 3–48. Note

that when a bus error occurs, any data returned

by the read instruction will not be valid.

Reserved

14–0

R

000000000000000

Reserved

†

This feature will not work if the XPORT is placed in idle through the ICR. However, a bus error will be generated if the XPORT is placed in idle

without the CPU being in idle.

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3.13.1.2 XPORT Bus Error Register (XERR)

The XPORT Bus Error Register bit layout is shown in Figure 3–43 and the bits are described in Table 3–50.

15

INTERR

R, 0

14

13

12

PERITO

R, 0

11

8

Reserved

R, 00

Reserved

R, 0000

7

5

4

3

2

0

Reserved

R, 000

EBUS

R, 0

DBUS

R, 0

Reserved

R, 000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–43. XPORT Bus Error Register Layout (0x0102)

Table 3–50. XPORT Bus Error Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

INTERR

15

R

0

INTERR bit

INTERR = 0:

INTERR = 1:

No error

An error occurred during an access to one of the

registers listed in Table 3–48.

Reserved

PERITO

14–13

R

00

0

Reserved

12

PERITO bit

PERITO = 0:

PERITO = 1:

No error

A time-out error occurred during an access to a

peripheral register.

Reserved

EBUS

11–5

R

0000000

0

Reserved

†

4

EBUS error bit

EBUS = 0:

EBUS = 1:

No error

An error occurred during an EBUS access (write) to

one of the registers listed in Table 3–48.

†

DBUS

3

R

0

DBUS error bit

DBUS = 0:

DBUS = 1:

No error

An error occurred during a DBUS access (read) to

one of the registers listed in Table 3–48.

Reserved

2–0

R

000

Reserved

†

See the TMS320C55x DSP CPU Reference Guide (literature number SPRU371) for more information on the D-bus and E-bus.

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Functional Overview

3.13.2 DPORT Interface

The DPORT interfaces the CPU to the EMIF module. The DPORT is capable of enabling write posting on the

EMIF module. Write posting prevents stalls to the CPU during external memory writes. Two write posting

registers, which are freely associated with E and F bus writes, exist within the DPORT and are used to store

the write address and data so that writes can be zero wait state for the CPU. External memory writes will not

generate stalls to the CPU unless the two write posting registers are filled. Write posting is enabled by setting

the WPE bit of the DCR to 1.

The EMIFTO bit of the DERR is used to indicate that a CPU, DMA, HPI, or IPORT access to external memory

has generated a time-out error. The time-out error feature is enabled through the EMIFTOEN bit of the

Time-Out Control Register (TOCR). This function is not recommended during normal operation of the 5502.

The DPORT can be placed into idle through the EMIFI bit of the Idle Control Register (ICR) and executing the

IDLE instruction. When the DPORT is in idle, it will stop accepting new EMIF requests. If there is a request

from the CPU or the EMIF, the DPORT will not respond and hang. The ICR register will generate a bus error

if the DPORT is idled without the CPU or Master Port domains being in idle.

3.13.2.1 DPORT Configuration Register (DCR)

The DPORT Configuration Register bit layout is shown in Figure 3–44 and the bits are described in

Table 3–51.

15

8

Reserved

R, 00000000

7

6

0

WPE

R/W, 0

Reserved

R, 0000000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–44. DPORT Configuration Register Layout (0x0200)

†

Table 3–51. DPORT Configuration Register Bit Field Description

BIT NAME

Reserved

WPE

BIT NO.

15–8

7

ACCESS

R

RESET VALUE

DESCRIPTION

00000000

0

Reserved

†

R/W

Write Posting Enable bit

WPE = 0:

WPE = 1:

Write posting disabled

Write posting enabled

Reserved

6–0

R

0000000

Reserved

†

Write posting should not be enabled or disabled while the EMIF is conducting a transaction with external memory.

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3.13.2.2 DPORT Bus Error Register (DERR)

The DPORT Bus Error Register bit layout is shown in Figure 3–45 and the bits are described in Table 3–52.

15

13

12

EMIFTO

R, 0

11

8

Reserved

R, 000

Reserved

R, 0000

7

0

Reserved

R, 00000000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–45. DPORT Bus Error Register Layout (0x0202)

Table 3–52. DPORT Bus Error Register Bit Field Description

BIT NAME

Reserved

EMIFTO

BIT NO.

15–13

12

ACCESS

RESET VALUE

DESCRIPTION

R

000

0

Reserved

EMIFTO bit

EMIFTO = 0:

EMIFTO = 1:

No error

Error 1 error

Reserved

11–0

R

000000000000

Reserved

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Functional Overview

3.13.3 IPORT Interface

The IPORT interfaces the I-Cache to the EMIF module. The ICACHETO bit of the IPORT Bus Error Register

(IERR) can be used to determine if a time-out error has occurred during an ICACHE access to external

memory. Thetime-outfeatureisenabledthroughtheEMIFTOENbitoftheTime-OutControlRegister(TOCR).

The IPORT can be placed into idle through the IPORTI bit of the Idle Control Register (ICR) and executing

the IDLE instruction. The IPORT will go into idle when there are no new requests from the ICACHE. When

the IPORT is in idle, it will stop accepting new requests from the CPU, it is important that the program flow not

use external memory in this case. If there are requests from the CPU, the IPORT will not respond and hang.

The ICR register will generate a bus error if the IPORT is idled without the CPU domain being in idle.

3.13.3.1 IPORT Bus Error Register (IERR)

The IPORT Bus Error Register bit layout is shown in Figure 3–46 and the bits are described in Table 3–53.

15

13

12

ICACHETO

R, 0

11

8

0

Reserved

R, 000

Reserved

R, 0000

7

Reserved

R, 00000000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–46. IPORT Bus Error Register Layout (0x0302)

Table 3–53. IPORT Bus Error Register Bit Field Description

BIT NAME

Reserved

BIT NO.

15–13

12

ACCESS

RESET VALUE

DESCRIPTION

R

000

0

Reserved

ICACHETO

ICACHETO bit

ICACHETO = 0:

ICACHETO = 1:

No error

A time-out error occurred during an ICACHE

access to external memory.

Reserved

11–0

R

000000000000

Reserved

†

See the TMS320C55x DSP CPU Reference Guide (literature number SPRU371) for more information on the P-bus.

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3.13.4 System Configuration Register (CONFIG)

The System Configuration Register can be used to determine the operational state of the ICACHE. If the

ICACHE is not functioning, the CACHEPRES bit of the CONFIG register will be cleared. If the ICACHE is

functioning normally, this bit will be set.

TheSystemConfigurationRegisterbitlayoutisshowninFigure3–47andthebitsaredescribedinTable 3–54.

15

8

Reserved

R, 10000010

7

6

5

4

3

0

Reserved

R, 00

CACHEPRES

R, 0

Reserved

R, 0000

†

RW, 0

LEGEND: R = Read, W = Write, n = value at reset

†

This Reserved bit must be kept as zero during any writes to CONFIG.

Figure 3–47. System Configuration Register Layout (0x07FD)

Table 3–54. System Configuration Register Bit Field Description

BIT NAME

BIT NO.

15–6

5

ACCESS

RESET VALUE

1000001000

0

DESCRIPTION

Reserved

R

Reserved

CACHEPRES

ICACHE present

CACHEPRES = 0: ICACHE is not functioning

CACHEPRES = 1: ICACHE is enabled and working

†

Reserved

4

R/W

R

0

Reserved

3–0

0000

†

This Reserved bit must be kept as zero during any writes to CONFIG.

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Functional Overview

3.13.5 Time-Out Control Register (TOCR)

The Time-Out Control Register can be used to select whether or not a time-out error is generated when an

access to a disabled/idled peripheral module occurs. If the CPU or DMA access a disabled/idle peripheral

module and 512 CPU clock cycles pass without an acknowledgement from the peripheral module, then a

time-out error will be sent to the corresponding module if bit 1 in the Time-Out Control Register is set. A

time-out error will generate a CPU bus error that can be serviced through software by using the bus error

interrupt (BERR) (see Section 3.16, Interrupts, for more information on interrupts). If the DMA gets a time-out

error, it will set the TIMEOUT bit in the DMA Status Register (DMACSR) and generate a time-out error that

can be serviced through software by the CPU [see the TMS320VC5501/5502 DSP Direct Memory Access

(DMA) Controller Reference Guide (literature number SPRU613) for more information on using this feature

of the DMA].

The Time-Out Control Register can also be used to select whether or not a time-out error is generated when

a memory access through the EMIF module stalls for more than 512 CPU clock cycles. It is recommended

that this feature not be used for it can cause unexpected results.

15

8

Reserved

R, 00000000

7

2

1

0

Reserved

R, 000000

EMIFTOEN

R/W, 0

PERITOEN

R/W, 1

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–48. Time-Out Control Register Layout (0x9000)

Table 3–55. Time-Out Control Register Bit Field Description

BIT NAME

Reserved

BIT NO.

15–2

1

ACCESS

R

RESET VALUE

DESCRIPTION

00000000000000 Reserved

EMIFTOEN

R/W

0

EMIF time-out control bit

EMIFTOEN = 0:

A time-out error is not generated when an EMIF

access stalls for more than 512 CPU clock

cycles.

EMIFTOEN = 1:

A time-out error is generated when an EMIF

access stalls for more than 512 CPU clock

cycles.

PERITOEN

0

R/W

1

Peripheral module time-out control bit

PERITOEN = 0:

A time-out error is not generated when a CPU

access to a disabled/idle peripheral module

stalls for more than 512 CPU clock cycles.

A time-out error is generated when a CPU

access to a disabled/idle peripheral module

stalls for more than 512 CPU clock cycles.

PERITOEN = 1:

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Functional Overview

3.14 CPU Memory-Mapped Registers

The 5502 has 78 memory-mapped CPU registers that are mapped in data memory space address 0h to 4Fh.

Table 3–56 provides a list of the CPU memory-mapped registers (MMRs) available. The corresponding

TMS320C54x (C54x ) CPU registers are also indicated where applicable.

Table 3–56. CPU Memory-Mapped Registers

C55X

C54X

REGISTER

WORD ADDRESS

(HEX)

C55X REGISTER DESCRIPTION

BIT FIELD

REGISTER

IER

IFR

–

IER0

IFR0

ST0_55

ST1_55

ST3_55

–

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

Interrupt Enable Register 0

[15–0]

[31–16]

[39–32]

[15–0]

[31–16]

[39–32]

[15–0]

[7–0]

Interrupt Flag Register 0

Status Register 0

–

Status Register 1

–

Status Register 3

–

Reserved

ST0

ST1

AL

ST0

Status Register 0 (protected address for C54x code)

Status Register 1 (protected address for C54x code)

ST1

AC0L

AC0H

AC0G

AC1L

AC1H

AC1G

T3

AH

AG

BL

Accumulator 0

Accumulator 1

BH

BG

TREG

TRN

AR0

AR1

AR2

AR3

AR4

AR5

AR6

AR7

SP

BK

BRC

RSA

REA

PMST

XPC

–

Temporary Register 3

TRN0

AR0

Transition Register 0

Auxiliary Register 0

AR1

Auxiliary Register 1

AR2

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

Auxiliary Register 2

AR3

Auxiliary Register 3

AR4

Auxiliary Register 4

AR5

Auxiliary Register 5

AR6

Auxiliary Register 6

AR7

Auxiliary Register 7

SP

Data Stack Pointer

BK03

BRC0

RSA0L

REA0L

PMST

XPC

–

Circular Buffer Size Register for AR[0–3]

Block Repeat Counter 0

Low Part of Block Repeat Start Address Register 0

Low Part of Block Repeat End Address Register 0

Status Register 3 (protected address for C54x code)

Program Counter Extension Register for C54x code

Reserved

[15–0]

[31–16]

[39–32]

–

T0

Temporary Register 0

–

T1

Temporary Register 1

–

T2

Temporary Register 2

–

T3

Temporary Register 3

–

AC2L

AC2H

AC2G

Accumulator 2

–

TMS320C54x and C54x are trademarks of Texas Instruments.

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Functional Overview

Table 3–56. CPU Memory-Mapped Registers (Continued)

C55X

C54X

REGISTER

WORD ADDRESS

C55X REGISTER DESCRIPTION

(HEX)

BIT FIELD

REGISTER

–

CDP

AC3L

AC3H

AC3G

DPH

27

28

29

2A

2B

Coefficient Data Pointer

Accumulator 3

[15–0]

[31–16]

[39–32]

[6–0]

High Part of the Extended Data Page Register

(XDP = DPH:DP)

–

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

Reserved

[6–0]

–

Reserved

DP

Data Page Register

[15–0]

[8–0]

PDP

Peripheral Data Page Register

BK47

BKC

Circular Buffer Size Register for AR[4–7]

Circular Buffer Size Register for CDP

Circular Buffer Start Address Register for AR[0–1]

Circular Buffer Start Address Register for AR[2–3]

Circular Buffer Start Address Register for AR[4–5]

Circular Buffer Start Address Register for AR[6–7]

Circular Buffer Start Address Register for CDP

[15–0]

BSA01

BSA23

BSA45

BSA67

BSAC

BIOS

Data Page Pointer Storage Location for 128-word Data Table

Transition Register 1

[15–0]

[23–16]

[15–0]

[23–16]

[15–0]

[23–16]

[15–0]

[23–16]

[15–0]

[6–0]

TRN1

BRC1

BRS1

CSR

Block Repeat Counter 1

BRC1 Save Register

Computed Single Repeat Register

Block Repeat Start Address Register 0

RSA0H

RSA0L

REA0H

REA0L

RSA1H

RSA1L

REA1H

REA1L

RPTC

IER1

Block Repeat End Address Register 0

Block Repeat Start Address Register 1

Block Repeat End Address Register 1

Single Repeat Counter

Interrupt Enable Register 1

Interrupt Flag Register 1

Debug Interrupt Enable Register 0

Interrupt Vector Pointer

Status Register 2

IFR1

DBIER0

DBIER1

IVPD

IVPH

ST2_55

SSP

System Stack Pointer

SP

Data Stack Pointer

SPH

High Part of the Extended Stack Pointers

(XSP = SPH:SP, XSSP = SPH:SSP)

–

CDPH

4F

High Part of the Extended Coefficient Data Pointer

(XCDP = CDPH:CDP)

[6–0]

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Functional Overview

3.15 Peripheral Registers

Each 5502 device has a set of memory-mapped registers associated with peripherals as listed in Table 3–57

through Table 3–76. Some registers use less than 16 bits. When reading these registers, unused bits are

always read as 0.

Table 3–57. Peripheral Bus Controller Configuration Registers

†

WORD ADDRESS

0x0000

REGISTER NAME

CMR

DESCRIPTION

Control Mode Register

RESET VALUE

1111 1110 1001 0011

0x0001

ICR

Idle Configuration Register

Idle Status Register

0000 0000 0000 0000

0x0002

ISTR

0x0003 to 0x000E

0x000F

Reserved

BOOT_MOD

Reserved

XCR

Boot Mode Register (read only)

Value of GPIO[2:0] at reset

0x0010

0x0011

0x0100

XPORT Configuration Register

XPORT Bus Error Register

DPORT Configuration Register

DPORT Bus Error Register

IPORT Bus Error Register

1000 0000 0000 0000

0000 0000 0000 0000

1000 0010 0000 0000

0x0102

XERR

0x0200

DCR

0x0202

DERR

0x0302

IERR

0x07FD

CONFIG

System Configuration Register

†

x denotes a “don’t care.”

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Functional Overview

Table 3–58. External Memory Interface Registers

†

WORD ADDRESS

0x0800

0x0801

0x0802

0x0803

0x0804

0x0805

0x0806

0x0807

0x0808

0x0809

0x080A

0x080B

0x080C

0x080D

0x080E

0x080F

0x0810

0x0811

0x0812

:

REGISTER NAME

DESCRIPTION

EMIF Global Control Register 1

EMIF Global Control Register 2

EMIF CE1 Space Control Register 1

EMIF CE1 Space Control Register 2

EMIF CE0 Space Control Register 1

EMIF CE0 Space Control Register 2

Reserved

RESET VALUE

0010 0111 0111 1100

0000 0000 0000 1001

1111 1111 0001 1111

1111 1111 1111 1111

1111 1111 0000 0011

1111 1111 1111 1111

EGCR1

EGCR2

CE1_1

CE1_2

CE0_1

CE0_2

–

Reserved

CE2_1

CE2_2

CE3_1

CE3_2

SDC1

SDC2

SDRC1

SDRC2

SDX1

SDX2

–

EMIF CE2 Space Control Register 1

EMIF CE2 Space Control Register 2

EMIF CE3 Space Control Register 1

EMIF CE3 Space Control Register 2

EMIF SDRAM Control Register 1

EMIF SDRAM Control Register 2

EMIF SDRAM Refresh Control Register 1

EMIF SDRAM Refresh Control Register 2

EMIF SDRAM Extension Register 1

EMIF SDRAM Extension Register 2

Reserved

1111 1111 1111 0011

1111 1111 1111 1111

1111 1111 1111 0011

1111 1111 1111 1111

1111 0000 0000 0000

0000 0011 0100 1000

1100 0101 1101 1100

0000 0000 0101 1101

0101 1111 1101 1111

0000 0000 0001 0111

–

:

0x0821

0x0822

0x0823

0x0824

0x0825

0x0826

0x0827

0x0828

0x0829

0x082A

0x082B

0x082C

:

–

Reserved

CE1_SC1

CE1_SC2

CE0_SC1

CE0_SC2

–

EMIF CE1 Secondary Control Register 1

EMIF CE1 Secondary Control Register 2

EMIF CE0 Secondary Control Register 1

EMIF CE0 Secondary Control Register 2

Reserved

0000 0000 0000 0010

0000 0000 0000 0000

0000 0000 0000 0010

0000 0000 0000 0000

–

Reserved

CE2_SC1

CE2_SC2

CE3_SC1

CE3_SC2

–

EMIF CE2 Secondary Control Register 1

EMIF CE2 Secondary Control Register 2

EMIF CE3 Secondary Control Register 1

EMIF CE3 Secondary Control Register 2

Reserved

0000 0000 0000 0010

0000 0000 0000 0000

0000 0000 0000 0010

0000 0000 0000 0000

–

:

0x0839

–

Reserved

†

x denotes a “don’t care.”

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April 2001 – Revised June 2003

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Functional Overview

Table 3–59. DMA Configuration Registers

WORD ADDRESS

REGISTER NAME

DESCRIPTION

RESET VALUE

GLOBAL REGISTER

0x0E00

0x0E01

DMA_GCR(2:0)

DMA_GTCR(3:0)

DMA Global Control Register

DMA Global Timeout Control Register

CHANNEL #0 REGISTERS

000

0000

0x0C00

DMA_CSDP0

DMA Channel 0 Source Destination Parameters

Register

0000 0000 0000 0000

0x0C01

0x0C02

0x0C03

0x0C04

DMA_CCR0(15:0)

DMA_CICR0(5:0)

DMA_CSR0(6:0)

DMA_CSSA_L0

DMA Channel 0 Control Register

DMA Channel 0 Interrupt Control register

DMA Channel 0 Status register

0000 0000 0000 0000

0000 0001 1000 0011

00 0000

DMA Channel 0 Source Start Address, lower bits,

register

Undefined

0x0C05

0x0C06

0x0C07

DMA_CSSA_U0

DMA_CDSA_L0

DMA_CDSA_U0

DMA Channel 0 Source Start Address, upper bits,

register

Undefined

DMA Channel 0 Source Destination Address, lower

bits, register

DMA Channel 0 Source Destination Address, upper

bits, register

0x0C08

0x0C09

0x0C0A

0x0C0B

0x0C0C

0x0C0D

0x0C0E

0x0C0F

DMA_CEN0

DMA_CFN0

DMA_CSFI0

DMA_CSEI0

DMA_CSAC0

DMA_CDAC0

DMA_CDEI0

DMA_CDFI0

DMA Channel 0 Element Number register

DMA Channel 0 Frame Number register

Undefined

DMA Channel 0 Source Frame Index register

DMA Channel 0 Source Element Index register

DMA Channel 0 Source Address Counter register

DMA Channel 0 Destination Address Counter register

DMA Channel 0 Destination Element Index register

DMA Channel 0 Destination Frame Index register

CHANNEL #1 REGISTERS

0x0C20

DMA_CSDP1

DMA Channel 1 Source Destination Parameters

Register

0000 0000 0000 0000

0x0C21

0x0C22

0x0C23

0x0C24

DMA_CCR1(15:0)

DMA_CICR1(5:0)

DMA_CSR1(6:0)

DMA_CSSA_L1

DMA Channel 1 Control Register

DMA Channel 1 Interrupt Control register

DMA Channel 1 Status register

0000 0000 0000 0000

0000 0001 1000 0011

00 0000

DMA Channel 1 Source Start Address, lower bits,

register

Undefined

0x0C25

0x0C26

0x0C27

DMA_CSSA_U1

DMA_CDSA_L1

DMA_CDSA_U1

DMA Channel 1 Source Start Address, upper bits,

register

Undefined

DMA Channel 1 Source Destination Address, lower

bits, register

DMA Channel 1 Source Destination Address, upper

bits, register

0x0C28

0x0C29

0x0C2A

0x0C2B

0x0C2C

0x0C2D

0x0C2E

0x0C2F

DMA_CEN1

DMA_CFN1

DMA_CSFI1

DMA_CSEI1

DMA_CSAC1

DMA_CDAC1

DMA_CDEI1

DMA_CDFI1

DMA Channel 1 Element Number register

Undefined

DMA Channel 1 Frame Number register

DMA Channel 1 Source Frame Index register

DMA Channel 1 Source Element Index register

DMA Channel 1 Source Address Counter register

DMA Channel 1 Destination Address Counter register

DMA Channel 1 Destination Element Index register

DMA Channel 1 Destination Frame Index register

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Table 3–59. DMA Configuration Registers (Continued)

WORD ADDRESS

REGISTER NAME

DESCRIPTION

RESET VALUE

CHANNEL #2 REGISTERS

0x0C40

DMA_CSDP2

DMA Channel 2 Source Destination Parameters

Register

0000 0000 0000 0000

0x0C41

0x0C42

0x0C43

0x0C44

DMA_CCR2(15:0)

DMA_CICR2(5:0)

DMA_CSR2(6:0)

DMA_CSSA_L2

DMA Channel 2 Control Register

DMA Channel 2 Interrupt Control register

DMA Channel 2 Status register

0000 0000 0000 0000

0000 0001 1000 0011

00 0000

DMA Channel 2 Source Start Address, lower bits,

register

Undefined

0x0C45

0x0C46

0x0C47

DMA_CSSA_U2

DMA_CDSA_L2

DMA_CDSA_U2

DMA Channel 2 Source Start Address, upper bits,

register

Undefined

DMA Channel 2 Source Destination Address, lower

bits, register

DMA Channel 2 Source Destination Address, upper

bits, register

0x0C48

0x0C49

0x0C4A

0x0C4B

0x0C4C

0x0C4D

0x0C4E

0x0C4F

DMA_CEN2

DMA_CFN2

DMA_CSFI2

DMA_CSEI2

DMA_CSAC2

DMA_CDAC2

DMA_CDEI2

DMA_CDFI2

DMA Channel 2 Element Number register

DMA Channel 2 Frame Number register

Undefined

DMA Channel 2 Source Frame Index register

DMA Channel 2 Source Element Index register

DMA Channel 2 Source Address Counter register

DMA Channel 2 Destination Address Counter register

DMA Channel 2 Destination Element Index register

DMA Channel 2 Destination Frame Index register

CHANNEL #3 REGISTERS

0x0C60

DMA_CSDP3

DMA Channel 3 Source Destination Parameters

Register

0000 0000 0000 0000

0x0C61

0x0C62

0x0C63

0x0C64

DMA_CCR3(15:0)

DMA_CICR3(5:0)

DMA_CSR3(6:0)

DMA_CSSA_L3

DMA Channel 3 Control Register

DMA Channel 3 Interrupt Control register

DMA Channel 3 Status register

0000 0000 0000 0000

0000 0001 1000 0011

00 0000

DMA Channel 3 Source Start Address, lower bits,

register

Undefined

0x0C65

0x0C66

0x0C67

DMA_CSSA_U3

DMA_CDSA_L3

DMA_CDSA_U3

DMA Channel 3 Source Start Address, upper bits,

register

Undefined

DMA Channel 3 Source Destination Address, lower

bits, register

DMA Channel 3 Source Destination Address, upper

bits, register

0x0C68

0x0C69

0x0C6A

0x0C6B

0x0C6C

0x0C6D

0x0C6E

0x0C6F

DMA_CEN3

DMA_CFN3

DMA_CSFI3

DMA_CSEI3

DMA_CSAC3

DMA_CDAC3

DMA_CDEI3

DMA_CDFI3

DMA Channel 3 Element Number register

Undefined

DMA Channel 3 Frame Number register

DMA Channel 3 Source Frame Index register

DMA Channel 3 Source Element Index register

DMA Channel 3 Source Address Counter register

DMA Channel 3 Destination Address Counter register

DMA Channel 3 Destination Element Index register

DMA Channel 3 Destination Frame Index register

97

April 2001 – Revised June 2003

SPRS166D

Functional Overview

Table 3–59. DMA Configuration Registers (Continued)

WORD ADDRESS

REGISTER NAME

DESCRIPTION

RESET VALUE

CHANNEL #4 REGISTERS

0x0C80

DMA_CSDP4

DMA Channel 4 Source Destination Parameters

Register

0000 0000 0000 0000

0x0C81

0x0C82

0x0C83

0x0C84

DMA_CCR4(15:0)

DMA_CICR4(5:0)

DMA_CSR4(6:0)

DMA_CSSA_L4

DMA Channel 4 Control Register

DMA Channel 4 Interrupt Control register

DMA Channel 4 Status register

0000 0000 0000 0000

0000 0001 1000 0011

00 0000

DMA Channel 4 Source Start Address, lower bits,

register

Undefined

0x0C85

0x0C86

0x0C87

DMA_CSSA_U4

DMA_CDSA_L4

DMA_CDSA_U4

DMA Channel 4 Source Start Address, upper bits,

register

Undefined

DMA Channel 4 Source Destination Address, lower

bits, register

DMA Channel 4 Source Destination Address, upper

bits, register

0x0C88

0x0C89

0x0C8A

0x0C8B

0x0C8C

0x0C8D

0x0C8E

0x0C8F

DMA_CEN4

DMA_CFN4

DMA_CSFI4

DMA_CSEI4

DMA_CSAC4

DMA_CDAC4

DMA_CDEI4

DMA_CDFI4

DMA Channel 4 Element Number register

DMA Channel 4 Frame Number register

Undefined

DMA Channel 4 Source Frame Index register

DMA Channel 4 Source Element Index register

DMA Channel 4 Source Address Counter register

DMA Channel 4 destination Address Counter register

DMA Channel 4 Destination Element Index register

DMA Channel 4 Destination Frame Index register

CHANNEL #5 REGISTERS

0x0CA0

DMA_CSDP5

DMA Channel 5 Source Destination Parameters

Register

0000 0000 0000 0000

0x0CA1

0x0CA2

0x0CA3

0x0CA4

DMA_CCR5(15:0)

DMA_CICR5(5:0)

DMA_CSR5(6:0)

DMA_CSSA_L5

DMA Channel 5 Control Register

DMA Channel 5 Interrupt Control register

DMA Channel 5 Status register

0000 0000 0000 0000

0000 0001 1000 0011

00 0000

DMA Channel 5 Source Start Address, lower bits,

register

Undefined

0x0CA5

0x0CA6

0x0CA7

DMA_CSSA_U5

DMA_CDSA_L5

DMA_CDSA_U5

DMA Channel 5 Source Start Address, upper bits,

register

Undefined

DMA Channel 5 Source Destination Address, lower

bits, register

DMA Channel 5 Source Destination Address, upper

bits, register

0x0CA8

0x0CA9

0x0CAA

0x0CAB

0x0CAC

0x0CAD

0x0CAE

0x0CAF

DMA_CEN5

DMA_CFN5

DMA_CSFI5

DMA_CSEI5

DMA_CSAC5

DMA_CDAC5

DMA_CDEI5

DMA_CDFI5

DMA Channel 5 Element Number register

Undefined

DMA Channel 5 Frame Number register

DMA Channel 5 Source Frame Index register

DMA Channel 5 Source Element Index register

DMA Channel 5 Source Address Counter register

DMA Channel 5 Destination Address Counter register

DMA Channel 5 Destination Element Index register

DMA Channel 5 Destination Frame Index register

98

SPRS166D

April 2001 – Revised June 2003

Functional Overview

Table 3–60. Instruction Cache Registers

WORD ADDRESS

0x1400

REGISTER NAME

DESCRIPTION

ICGC

ICache Global Control Register

0x1401

0x1402

0x1403

ICFLARL

ICFLARH

ICWMC

ICache Flush Line Address Register Low Part

ICache Flush Line Address Register High Part

ICache N-Way Control Register

†

Table 3–61. Trace FIFO

WORD ADDRESS

REGISTER NAME

DESCRIPTION

Trace Register Discontinuity Section

0x2000 – 0x203F

0x2040 – 0x204F

0x2050

TRC00 – TRC63

TRC64 – TRC79

TRC_LPCOFFSET1

TRC_LPCOFFSET2

TRC_PTR

Trace Register Last PC Section

Trace LPC Offset Register 1

Trace LPC Offset Register 2

Trace Pointer Register

0x2051

0x2052

0x2053

TRC_CNTL

Trace Control Register

0x2054

TRC_ID

Trace ID Register

†

The Trace FIFO registers are used by the emulator only and do not require any intervention from the user.

Table 3–62. Timer Signal Selection Register

WORD ADDRESS

REGISTER NAME

TSSR

DESCRIPTION

RESET VALUE

0x8000

Timer Signal Selection Register

0000 0000 0000 0000

Table 3–63. Timers

DESCRIPTION

WORD ADDRESS

0x1000

0x1001

0x1002

0x1003

0x1004

0x1005

0x1006

0x1007

0x1008

0x1009

0x100A

0x100B

0x100C

0x100D

0x100E

0x100F

0x1010

0x1011

0x1012

0x2400

0x2401

0x2402

0x2403

0x2404

0x2405

REGISTER NAME

GPTPID1_0

GPTPID2_0

GPTEMU_0

GPTCLK_0

RESET VALUE

0000 0111 0000 0001

0000 0000 0000 0001

0000 0000 0000 0000

0000 0111 0000 0001

0000 0000 0000 0001

0000 0000 0000 0000

Peripheral ID register 1, Timer #0

Peripheral ID register 2, Timer #0

Emulation Management Register, Timer #0

Timer Clock Speed Register, Timer #0

GPIO Interrupt Control Register, Timer #0

GPIO Enable Register, Timer #0

GPIO Data Register, Timer #0

GPTGPINT_0

GPTGPEN_0

GPTGPDAT_0

GPTGPDIR_0

GPTCNT1_0

GPTCNT2_0

GPTCNT3_0

GPTCNT4_0

GPTPRD1_0

GPTPRD2_0

GPTPRD3_0

GPTPRD4_0

GPTCTL1_0

GPTCTL2_0

GPTGCTL1_0

GPTPID1_1

GPTPID2_1

GPTEMU_1

GPTCLK_1

GPIO Direction Register, Timer #0

Timer Counter 1 Register, Timer #0

Timer Counter 2 Register, Timer #0

Timer Counter 3 Register, Timer #0

Timer Counter 4 Register, Timer #0

Period Register 1, Timer #0

Period Register 2, Timer #0

Period Register 3, Timer #0

Period Register 4, Timer #0

Timer Control Register 1, Timer #0

Timer Control Register 2, Timer #0

Global Timer Control Register 1, Timer #0

Peripheral ID register 1, Timer #1

Peripheral ID register 2, Timer #1

Emulation Management Register, Timer #1

Timer Clock Speed Register, Timer #1

GPIO Interrupt Control Register, Timer #1

GPIO Enable Register, Timer #1

GPTGPINT_1

GPTGPEN_1

99

April 2001 – Revised June 2003

SPRS166D

Functional Overview

Table 3–63. Timers (Continued)

DESCRIPTION

WORD ADDRESS

0x2406

0x2407

0x2408

0x2409

0x240A

0x240B

0x240C

0x240D

0x240E

0x240F

0x2410

0x2411

0x2412

0x4000

0x4001

0x4002

0x4003

0x4004

0x4005

0x4006

0x4007

0x4008

0x4009

0x400A

0x400B

0x400C

0x400D

0x400E

0x400F

0x4010

0x4011

0x4012

0x4014

0x4015

REGISTER NAME

GPTGPDAT_1

GPTGPDIR_1

GPTCNT1_1

GPTCNT2_1

GPTCNT3_1

GPTCNT4_1

GPTPRD1_1

GPTPRD2_1

GPTPRD3_1

GPTPRD4_1

GPTCTL1_1

GPTCTL2_1

GPTGCTL1_1

WDTPID1

RESET VALUE

0000 0000 0000 0000

0000 0111 0000 0001

0000 0000 0000 0001

0000 0000 0000 0000

0000 0001 0000 1000

0000 0000 0000 0000

1111 1111 0000 0000

0000 0000 0000 0000

GPIO Data Register, Timer #1

GPIO Direction Register, Timer #1

Timer Counter 1 Register, Timer #1

Timer Counter 2 Register, Timer #1

Timer Counter 3 Register, Timer #1

Timer Counter 4 Register, Timer #1

Period Register 1, Timer #1

Period Register 2, Timer #1

Period Register 3, Timer #1

Period Register 4, Timer #1

Timer Control Register 1, Timer #1

Timer Control Register 2, Timer #1

Global Timer Control Register 1, Timer #1

Peripheral ID register 1, Watchdog Timer

Peripheral ID register 2, Watchdog Timer

Emulation Management Register, Watchdog Timer

Timer Clock Speed Register, Watchdog Timer

GPIO Interrupt Control Register, Watchdog Timer

GPIO Enable Register, Watchdog Timer

GPIO Data Register, Watchdog Timer

GPIO Direction Register, Watchdog Timer

Timer Counter 1 Register, Watchdog Timer

Timer Counter 2 Register, Watchdog Timer

Timer Counter 3 Register, Watchdog Timer

Timer Counter 4 Register, Watchdog Timer

Period Register 1, Watchdog Timer

Period Register 2, Watchdog Timer

Period Register 3, Watchdog Timer

Period Register 4, Watchdog Timer

Timer Control Register 1, Watchdog Timer

Timer Control Register 2, Watchdog Timer

Global Timer Control Register 1, Watchdog Timer

WD Timer Control Register 1, Watchdog Timer

WD Timer Control Register 2, Watchdog Timer

WDTPID2

WDTEMU

WDTCLK

WDTGPINT

WDTGPEN

WDTGPDAT

WDTGPDIR

WDTCNT1

WDTCNT2

WDTCNT3

WDTCNT4

WDTPRD1

WDTPRD2

WDTPRD3

WDTPRD4

WDTCTL1

WDTCTL2

WDTGCTL1

WDTWCTL1

WDTWCTL2

100

SPRS166D

April 2001 – Revised June 2003

Functional Overview

Table 3–64. Multichannel Serial Port #0

WORD ADDRESS

0x2800

0x2801

0x2802

0x2803

0x2804

0x2805

0x2806

0x2807

0x2808

0x2809

0x280A

0x280B

0x280C

0x280D

0x280E

0x280F

0x2810

0x2811

0x2812

0x2813

0x2814

0x2815

0x2816

0x2817

0x2818

0x2819

0x281A

0x281B

0x281C

0x281D

0x281E

0x281F

REGISTER NAME

DESCRIPTION

RESET VALUE

0000 0000 0000 0000

0000 0000 0000 0001

0010 0000 0000 0000

0000 0000 0000 0000

DRR1_0

DRR2_0

DXR1_0

DXR2_0

SPCR1_0

SPCR2_0

RCR1_0

RCR2_0

XCR1_0

XCR2_0

SRGR1_0

SRGR2_0

MCR1_0

MCR2_0

RCERA_0

RCERB_0

XCERA_0

XCERB_0

PCR0

Data Receive Register 1, McBSP #0

Data Receive Register 2, McBSP #0

Data Transmit Register 1, McBSP #0

Data Transmit Register 2, McBSP #0

Serial Port Control Register 1, McBSP #0

Serial Port Control Register 2, McBSP #0

Receive Control Register 1, McBSP #0

Receive Control Register 2, McBSP #0

Transmit Control Register 1, McBSP #0

Transmit Control Register 2, McBSP #0

Sample Rate Generator Register 1, McBSP #0

Sample Rate Generator Register 2, McBSP #0

Multichannel Control Register 1, McBSP #0

Multichannel Control Register 2, McBSP #0

Receive Channel Enable Register Partition A, McBSP #0

Receive Channel Enable Register Partition B, McBSP #0

Transmit Channel Enable Register Partition A, McBSP #0

Transmit Channel Enable Register Partition B, McBSP #0

Pin Control Register, McBSP #0

Reserved

RCERC_0

RCERD_0

XCERC_0

XCERD_0

RCERE_0

RCERF_0

XCERE_0

XCERF_0

RCERG_0

RCERH_0

XCERG_0

XCERH_0

Receive Channel Enable Register Partition C, McBSP #0

Receive Channel Enable Register Partition D, McBSP #0

Transmit Channel Enable Register Partition C, McBSP #0

Transmit Channel Enable Register Partition D, McBSP #0

Receive Channel Enable Register Partition E, McBSP #0

Receive Channel Enable Register Partition F, McBSP #0

Transmit Channel Enable Register Partition E, McBSP #0

Transmit Channel Enable Register Partition F, McBSP #0

Receive Channel Enable Register Partition G, McBSP #0

Receive Channel Enable Register Partition H, McBSP #0

Transmit Channel Enable Register Partition G, McBSP #0

Transmit Channel Enable Register Partition H, McBSP #0

0000 0000 0000 0000

101

April 2001 – Revised June 2003

SPRS166D

Functional Overview

Table 3–65. Multichannel Serial Port #1

WORD ADDRESS

0x2C00

0x2C01

0x2C02

0x2C03

0x2C04

0x2C05

0x2C06

0x2C07

0x2C08

0x2C09

0x2C0A

0x2C0B

0x2C0C

0x2C0D

0x2C0E

0x2C0F

0x2C10

0x2C11

0x2C12

0x2C13

0x2C14

0x2C15

0x2C16

0x2C17

0x2C18

0x2C19

0x2C1A

0x2C1B

0x2C1C

0x2C1D

0x2C1E

0x2C1F

REGISTER NAME

DRR1_1

DESCRIPTION

RESET VALUE

0000 0000 0000 0000

0000 0000 0000 0001

0010 0000 0000 0000

0000 0000 0000 0000

Data Receive Register 1, McBSP #1

DRR2_1

DXR1_1

DXR2_1

SPCR1_1

SPCR2_1

RCR1_1

RCR2_1

XCR1_1

XCR2_1

SRGR1_1

SRGR2_1

MCR1_1

MCR2_1

RCERA_1

RCERB_1

XCERA_1

XCERB_1

PCR1

Data Receive Register 2, McBSP #1

Data Transmit Register 1, McBSP #1

Data Transmit Register 2, McBSP #1

Serial Port Control Register 1, McBSP #1

Serial Port Control Register 2, McBSP #1

Receive Control Register 1, McBSP #1

Receive Control Register 2, McBSP #1

Transmit Control Register 1, McBSP #1

Transmit Control Register 2, McBSP #1

Sample Rate Generator Register 1, McBSP #1

Sample Rate Generator Register 2, McBSP #1

Multichannel Register 1, McBSP #1

Multichannel Register 2, McBSP #1

Receive Channel Enable Register Partition A, McBSP #1

Receive Channel Enable Register Partition B, McBSP #1

Transmit Channel Enable Register Partition A, McBSP #1

Transmit Channel Enable Register Partition B, McBSP #1

Pin Control Register, McBSP #1

Reserved

RCERC_1

RCERD_1

XCERC_1

XCERD_1

RCERE_1

RCERF_1

XCERE_1

XCERF_1

RCERG_1

RCERH_1

XCERG_1

XCERH_1

Receive Channel Enable Register Partition C, McBSP #1

Receive Channel Enable Register Partition D, McBSP #1

Transmit Channel Enable Register Partition C, McBSP #1

Transmit Channel Enable Register Partition D, McBSP #1

Receive Channel Enable Register Partition E, McBSP #1

Receive Channel Enable Register Partition F, McBSP #1

Transmit Channel Enable Register Partition E, McBSP #1

Transmit Channel Enable Register Partition F, McBSP #1

Receive Channel Enable Register Partition G, McBSP #1

Receive Channel Enable Register Partition H, McBSP #1

Transmit Channel Enable Register Partition G, McBSP #1

Transmit Channel Enable Register Partition H, McBSP #1

0000 0000 0000 0000

102

SPRS166D

April 2001 – Revised June 2003

Functional Overview

Table 3–66. Multichannel Serial Port #2

WORD ADDRESS

0x3000

0x3001

0x3002

0x3003

0x3004

0x3005

0x3006

0x3007

0x3008

0x3009

0x300A

0x300B

0x300C

0x300D

0x300E

0x300F

0x3010

0x3011

0x3012

0x3013

0x3014

0x3015

0x3016

0x3017

0x3018

0x3019

0x301A

0x301B

0x301C

0x301D

0x301E

0x301F

REGISTER NAME

DESCRIPTION

RESET VALUE

0000 0000 0000 0000

0000 0000 0000 0001

0010 0000 0000 0000

0000 0000 0000 0000

DRR1_2

DRR2_2

DXR1_2

DXR2_2

SPCR1_2

SPCR2_2

RCR1_2

RCR2_2

XCR1_2

XCR2_2

SRGR1_2

SRGR2_2

MCR1_2

MCR2_2

RCERA_2

RCERB_2

XCERA_2

XCERB_2

PCR2

Data Receive Register 1, McBSP #2

Data Receive Register 2, McBSP #2

Data Transmit Register 1, McBSP #2

Data Transmit Register 2, McBSP #2

Serial Port Control Register 1, McBSP #2

Serial Port Control Register 2, McBSP #2

Receive Control Register 1, McBSP #2

Receive Control Register 2, McBSP #2

Transmit Control Register 1, McBSP #2

Transmit Control Register 2, McBSP #2

Sample Rate Generator Register 1, McBSP #2

Sample Rate Generator Register 2, McBSP #2

Multichannel Register 1, McBSP #2

Multichannel Register 2, McBSP #2

Receive Channel Enable Register Partition A, McBSP #2

Receive Channel Enable Register Partition B, McBSP #2

Transmit Channel Enable Register Partition A, McBSP #2

Transmit Channel Enable Register Partition B, McBSP #2

Pin Control Register, McBSP #2

Reserved

RCERC_2

RCERD_2

XCERC_2

XCERD_2

RCERE_2

RCERF_2

XCERE_2

XCERF_2

RCERG_2

RCERH_2

XCERG_2

XCERH_2

Receive Channel Enable Register Partition C, McBSP #2

Receive Channel Enable Register Partition D, McBSP #2

Transmit Channel Enable Register Partition C, McBSP #2

Transmit Channel Enable Register Partition D, McBSP #2

Receive Channel Enable Register Partition E, McBSP #2

Receive Channel Enable Register Partition F, McBSP #2

Transmit Channel Enable Register Partition E, McBSP #2

Transmit Channel Enable Register Partition F, McBSP #2

Receive Channel Enable Register Partition G, McBSP #2

Receive Channel Enable Register Partition H, McBSP #2

Transmit Channel Enable Register Partition G, McBSP #2

Transmit Channel Enable Register Partition H, McBSP #2

0000 0000 0000 0000

103

April 2001 – Revised June 2003

SPRS166D

Functional Overview

Table 3–67. HPI

†

RESET VALUE

WORD ADDRESS

0xA000

REGISTER NAME

PID LSW

DESCRIPTION

PID [15:0]

PID [31:16]

—

0xA001

PID MSW

0xA002

HPWREMU

Power and Emulation Management Register

Reserved

0000 0000 0000 0000

0xA003

0xA004

HGPIOINT1

HGPIOINT2

HGPIOEN

General-Purpose I/O Interrupt Control Register 1

General-Purpose I/O Interrupt Control Register 2

General-Purpose I/O Enable Register

Reserved

0000 0000 0000 0000

0xA005

0xA006

0xA007

0xA008

HGPIODIR1

HGPIODAT1

HGPIODIR2

HGPIODAT2

HGPIODIR3

HGPIODAT3

HPIC

General-Purpose I/O Direction Register 1

Reserved

0000 0000 0000 0000

xxxx xxxx xxxx xxxx

0000 0000 0000 0000

xxxx xxxx xxxx xxxx

0000 0000 0000 0000

xxxx xxxx xxxx xxxx

0000 0000 0000 1000

xxxx xxxx xxxx xxxx

0xA009

0xA00A

General-Purpose I/O Data Register 1

Reserved

0xA00B

0xA00C

General-Purpose I/O Direction Register 2

Reserved

0xA00D

0xA00E

General-Purpose I/O Data Register 2

Reserved

0xA00F

0xA010

General-Purpose I/O Direction Register 3

Reserved

0xA011

0xA012

General-Purpose I/O Data Register 3

Reserved

0xA013 – 0xA017

0xA018

Host Port Control Register

Reserved

0xA019

0xA01A

HPIAW

Host Port Write Address Register

Reserved

0xA01B

0xA01C

HPIAR

Host Port Read Address Register

Reserved

0xA01D – 0xA020

†

x denotes a “don’t care.”

Table 3–68. GPIO

†

WORD ADDRESS

REGISTER NAME

DESCRIPTION

General-purpose I/O Direction Register

General-purpose I/O Data Register

Parallel GPIO Enable Register 0

Parallel GPIO Direction Register 0

Parallel GPIO Data Register 0

Parallel GPIO Enable Register 1

Parallel GPIO Direction Register 1

Parallel GPIO Data Register 1

Parallel GPIO Enable Register 2

Parallel GPIO Direction Register 2

Parallel GPIO Data Register 2

RESET VALUE

0000 0000 0000 0000

0000 0000 xxxx xxxx

0000 0000 0000 0000

0x3400

0x3401

0x4400

0x4401

0x4402

0x4403

0x4404

0x4405

0x4406

0x4407

0x4408

IODIR

IODATA

PGPIOEN0

PGPIODIR0

PGPIODAT0

PGPIOEN1

PGPIODIR1

PGPIODAT1

PGPIOEN2

PGPIODIR2

PGPIODAT2

†

x denotes a “don’t care.”

104

SPRS166D

April 2001 – Revised June 2003

Functional Overview

Table 3–69. Device Revision ID

†

WORD ADDRESS

0x3800 – 0x3803

0x3804

REGISTER NAME

Die ID

DESCRIPTION

Die ID

RESET VALUE

Chip ID (LSW)

Chip ID (MSW)

Sub ID

Defines F# 3LS digits and PG rev

Defines F# 3MS digits

Defines subsytem ID

1001 0100 0110 0001

0000 0111 0101 0001

0x3805

‡

0x3806

0000 0000 0000 0000

0101 0101 0000 0010 (5502h)

0x3807

Cat ID

Defines catalog device

†

‡

x denotes a “don’t care.”

Denotes single core

2

Table 3–70. I C

†

WORD ADDRESS

REGISTER NAME

DESCRIPTION

RESET VALUE

0000 0000 0000 0000

0000 0100 0001 0000

0000 0000 0000 0000

0000 0011 1111 1111

0000 0000 0000 0000

xxxx xxxx xxxx xxxx

0000 0000 0000 0000

–

‡

2

I C Own Address Register

0x3C00

0x3C01

0x3C02

0x3C03

0x3C04

0x3C05

0x3C06

0x3C07

0x3C08

0x3C09

0x3C0A

0x3C0B

0x3C0C

0x3C0D

0x3C0E

–

I2COAR

I2CIER

I2CSTR

2

I C Interrupt Enable Register

2

I C Status Register

2

I C Clock Low-Time Divider Register

I2CCLKL

I2CCLKH

I2CCNT

I2CDRR

I2CSAR

I2CDXR

I2CMDR

I2CISRC

I2CGPIO

I2CPSC

PID1

2

I C Clock High-Time Divider Register

2

I C Data Count

2

I C Data Receive Register

2

I C Slave Address Register

2

I C Data Transmit Register

2

I C Mode Register

2

I C Interrupt Source Register

2

I C General-Purpose Register (Not supported)

2

I C Prescaler Register

2

I C Peripheral ID Register 1

2

PID2

I C Peripheral ID Register 2

–

2

I2CXSR

I2CRSR

I C Transmit Shift Register

–

2

–

I C Receive Shift Register

–

†

‡

x denotes a “don’t care.”

2

Specifiesaunique5502I Caddress. Thisregisterisfullyprogrammableinboth7-bitand10-bitmodesandmustbesetbytheprogrammer.When

this device is used in conjunction with another I C device, it must be programmed to the I C slave address (01011A A A ) allocated by Philips

2 1 0

Semiconductor for the 5502. A , A , and A are programmable address bits.

2

1

0

105

April 2001 – Revised June 2003

SPRS166D

Functional Overview

Table 3–71. UART

†

WORD ADDRESS

REGISTER NAME

URRBR/

URTHR/

DESCRIPTION

RESET VALUE

0x9C00

Receive Buffer Register

Transmit Holding Register

Divisor Latch LSB Register

xxxx xxxx

‡

URDLL

0x9C01

0x9C02

URIER/

URDLM

Interrupt Enable Register

Divisor Latch MSB Register

0000 0000

§

URIIR/

Interrupt Identification Register

FIFO Control Register

0000 0001

0000 0000

¶

URFCR

0x9C03

0x9C04

0x9C05

0x9C07

0x9C08

0x9C09

0x9C0A

0x9C0B

0x9C0C

URLCR

Line Control Register

0000 0000

URMCR

URLSR

URSCR

Modem Control Register

Line Status Register

0000 0000

0110 0000

Scratch Register

xxxx xxxx

‡

URDLL

Divisor Latch LSB Register

Divisor Latch MSB Register

Peripheral ID Register (LSW)

Peripheral ID Register (MSW)

Power and Emulation Control Register

–

§

URDLM

–

URPID1

URPID2

URPECR

–

0000 0000 0000 0000

†

‡

x denotes a “don’t care.”

The registers URRBR, URTHR, and URDLL share one address. URDLL also has a dedicated address. When using the dedicated address, the

DLAB bit can be kept cleared, so that URRBR and URTHR are always selected at the shared address.

If DLAB = 0 :

Read Only: URRBR

Write Only: URTHR

Read/Write: URDLL

If DLAB = 1:

§

¶

The registers URIER and URDLM share one address. URDLM also has a dedicated address. When using the dedicated address, the DLAB bit

can be kept cleared, so that URIER is always selected at the shared address.

If DLAB = 0:

If DLAB = 1:

Read/WRite: URIER

Read/Write: URDLM

The registers URIIR and URFCR share one address.

Read Only:

Write Only:

URIIR

URFCR

Table 3–72. External Bus Selection

WORD ADDRESS

REGISTER NAME

XBSR

XBCR

DESCRIPTION

External Bus Selection Register

External Bus Control Register

RESET VALUE

0000 0000 0000 0000

0x6C00

0x8800

Table 3–73. Clock Mode Register

WORD ADDRESS

REGISTER NAME

DESCRIPTION

RESET VALUE

0x8C00

CLKMD

Clock Mode Control Register

0000 0000 0000 0000

Table 3–74. CLKOUT Selector Register

WORD ADDRESS

REGISTER NAME

DESCRIPTION

CLKOUT Selection Register

RESET VALUE

0x8400

CLKOUTSR

0000 0000 0000 0010

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Functional Overview

Table 3–75. Clock Controller Registers

WORD ADDRESS

0x1C80

REGISTER NAME

DESCRIPTION

PLL Control Status Register

RESET VALUE

PLLCSR

CK3SEL

PLLM

0000 0000 0000 0000

0x1C82

CLKOUT3 Select Register

PLL Multiplier Control Register

PLL Divider 0 Register

0000 0000 0000 1011

0000 0000 0000 0000

1000 0000 0000 0000

1000 0000 0000 0011

0000 0000 0000 0000

0x1C88

0x1C8A

PLLDIV0

PLLDIV1

PLLDIV2

PLLDIV3

OSCDIV1

WKEN

0x1C8C

PLL Divider 1 Register

0x1C8E

PLL Divider 2 Register

0x1C90

PLL Divider 3 Register

0x1C92

Oscillator Divider 1 Register

Oscillator Wakeup Control Register

0x1C98

Table 3–76. IDLE Control Registers

WORD ADDRESS

0x9400

REGISTER NAME

DESCRIPTION

Peripheral IDLE Control Register

Peripheral IDLE Status Register

Master IDLE Control Register

Master IDLE Status Register

RESET VALUE

0000 0000 0000 0000

PICR

PISTR

MICR

MISR

0x9401

0x9402

0x9403

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Functional Overview

3.16 Interrupts

Vector-relativelocationsandprioritiesforallinternalandexternalinterruptsareshowninTable 3–77. For more

information on setting up and using interrupts, please refer to the TMS320C55x DSP CPU Reference Guide

(literature number SPRU371).

Table 3–77. Interrupt Table

SOFTWARE

LOCATION

NAME

RESET

(TRAP)

PRIORITY

FUNCTION

(HEX BYTES)

EQUIVALENT

SINT0

0

Reset (hardware and software)

Nonmaskable interrupt

NMI

SINT1

8

1

INT0

SINT2

10

18

20

28

30

38

40

48

50

58

60

68

70

78

80

88

90

98

A0

A8

B0

B8

C0

C8

D0

D8

E0

E8

F0

F8

3

External interrupt #0

INT2

SINT3

5

External interrupt #2

TINT0

RINT0

RINT1

XINT1

LCKINT

DMAC1

DSPINT

INT3/WDTINT

RINT2

XINT2

DMAC4

DMAC5

INT1

SINT4

6

Timer #0 interrupt

SINT5

7

McBSP #0 receive interrupt

McBSP #1 receive interrupt

McBSP #1 transmit interrupt

PLL lock interrupt

SINT6

9

SINT7

10

11

13

14

15

17

18

21

22

4

SINT8

SINT9

DMA Channel #1 interrupt

Interrupt from host

SINT10

SINT11

SINT12

SINT13

SINT14

SINT15

SINT16

SINT17

SINT18

SINT19

SINT20

SINT21

SINT22

SINT23

SINT24

SINT25

SINT26

SINT27

SINT28

SINT29

SINT30

SINT31

†

External interrupt #3 or Watchdog timer interrupt

McBSP #2 receive interrupt

McBSP #2 transmit interrupt

DMA Channel #4 interrupt

DMA Channel #5 interrupt

External interrupt #1

XINT0

DMAC0

–

8

McBSP #0 transmit interrupt

DMA Channel #0 interrupt

Software interrupt #19

12

16

19

20

23

24

2

DMAC2

DMAC3

TINT1

IIC

DMA Channel #2 interrupt

DMA Channel #3 interrupt

Timer #1 interrupt

2

I C interrupt

BERR

DLOG

RTOS

–

Bus Error interrupt

25

26

27

28

29

30

31

Data Log interrupt

Real-time Operating System interrupt

Software interrupt #27

Software interrupt #28

Software interrupt #29

Software interrupt #30

Software interrupt #31

–

†

WDTINT is only available when the Watchdog Timer is used as a general-purpose timer.

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Functional Overview

3.16.1 IFR and IER Registers

The Interrupt Enable Registers (IER0 and IER1) control which interrupts will be masked or enabled during

normal operation. The Interrupt Flag Registers (IFR0 and IFR1) contain flags that indicate interrupts that are

currently pending.

The Debug Interrupt Enable Registers (DBIER0 and DBIER1) are used only when the CPU is halted in the

real-time emulation mode. If the CPU is running in real-time mode, the standard interrupt processing (IER0/1)

is used and DBIER0/1 are ignored.

A maskable interrupt enabled in DBIER0/1 is defined as a time-critical interrupt. When the CPU is halted in

the real-time mode, the only interrupts that are serviced are time-critical interrupts that are also enabled in an

interrupt enable register (IER0 or IER1).

Write the DBIER0/1 to enable or disable time-critical interrupts. To enable an interrupt, set its corresponding

bit. To disable an interrupt, clear its corresponding bit. Initialize these registers before using the real-time

emulation mode.

A DSP hardware reset clears IFR0/1, IER0/1, and DBIER0/1 to 0. A software reset instruction clears IFR0/1

to 0 but does not affect IER0/1 and DBIER0/1.

The bit layouts of these registers for each interrupt are shown in Figure 3–49 and Figure 3–50. For more

information on the IER, IFR, and DBIER registers, refer to the TMS320C55x DSP CPU Reference Guide

(literature number SPRU371).

15

14

13

12

11

10

9

8

RINT2/

UART

INT3/

WDTINT

DMAC5

R/W, 0

DMAC4

R/W, 0

XINT2

R/W, 0

DSPINT

R/W, 0

DMAC1

R/W, 0

Reserved

R/W, 0

†

R/W, 0

4

R/W, 0

3

7

6

5

2

1

0

XINT1

R/W, 0

RINT1

R/W, 0

RINT0

R/W, 0

TINT0

R/W, 0

INT2

INT0

Reserved

R, 0

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

†

The WDT interrupt pin must be connected to INT3 through the TSSR.

Figure 3–49. IFR0, IER0, DBIFR0, and DBIER0 Registers Layout

15

11

10

9

8

Reserved

R, 0

RTOS

R/W, 0

DLOG

R/W, 0

BERR

R/W, 0

7

6

5

4

3

2

1

0

2

I C

TINT1

R/W, 0

DMAC3

R/W, 0

DMAC2

R/W, 0

INT4

R/W, 0

DMAC0

R/W, 0

XINT0

R/W, 0

INT1

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3–50. IFR1, IER1, DBIFR1, and DBIER1 Registers Layout

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Functional Overview

3.16.2 Interrupt Timing

The external interrupts (NMI and INT) are synchronized to the CPU by way of a two-flip-flop synchronizer. The

interrupt inputs are sampled on falling edges of the CPU clock. A sequence on the interrupt pin of 1–0–0–0

on consecutive cycles is required for an interrupt to be detected. Therefore, the minimum low pulse duration

on the external interrupts on the 5502 is three CPU clock periods.

TIM0, TIM1, WDTOUT,andHPI.HAScanbeconfiguredtogenerateinterruptstotheCPU. Whentheyareused

for this function, these pins will generate the interrupt associated with that module, i.e., TIM0 will generate

TINT0, HPI.HAS will generate DSPINT, etc. Three SYSCLK1 clock cycles must be allowed to pass between

consecutive interrupts generated using the HPI.HAS signal; otherwise, the last interrupt will be ignored

(i.e., a sequence of 0–1–1–1–0 on consecutive cycles is required for consecutive interrupts). For more

information on configuring TIM0, TIM1, WDTOUT, and HPI.HAS as interrupt pins, please refer to the

TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618) for the timer pins and to

the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620) for

the HPI pin.

3.16.3 Interrupt Acknowledge

TheIACK pin is used to indicate the receipt of an interrupt and that the program counter is fetching the interrupt

vector location designated on the address bus. As the CPU fetches the first word or the software vector, it

generates the IACK signal, which clears the appropriate interrupt flag bit. The IACK signal will go low for a total

of one CPU clock pulse and then go high again. For maskable interrupts, note that the CPU will not jump to

an interrupt service routine if the appropriate interrupt enable bit is not set; consequently, the IACK pin will not

go low when the interrupt is generated.

110

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Documentation Support

4

Documentation Support

Extensive documentation supports all TMS320 DSP family of devices from product announcement through

applications development. The following types of documentation are available to support the design and use

of the TMS320C5000 platform of DSPs:

•

Device-specific data sheets

Complete user’s guides

Development support tools

Hardware and software application reports

TMS320C55x reference documentation that includes, but is not limited to, the following:

•

TMS320C55x DSP CPU Reference Guide (literature number SPRU371)

TMS320C55x DSP Mnemonic Instruction Set Reference Guide (literature number SPRU374)

TMS320C55x DSP Algebraic Instruction Set Reference Guide (literature number SPRU375)

TMS320C55x DSP Programmer’s Guide (literature number SPRU376)

TMS320VC5501/5502 DSP Instruction Cache Reference Guide (literature number SPRU630)

TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618)

TMS320VC5501/5502/5509 DSP Inter-Integrated Circuit (I2C) Module Reference Guide

(literature number SPRU146)

•

TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)

TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide

(literature number SPRU613)

•

TMS320VC5501/5502/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide

(literature number SPRU592)

TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide

(literature number SPRU621)

TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) Reference Guide

(literature number SPRU597)

The reference guides describe in detail the TMS320C55x DSP products currently available and the

hardware and software applications, including algorithms, for fixed-point TMS320 DSP family of devices.

A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal

processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published

quarterly and distributed to update TMS320 DSP customers on product information.

Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform

resource locator (URL).

TMS320 and TMS320C5000 are trademarks of Texas Instruments.

111

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SPRS166D

Device and Development-Support Tool Nomenclature

5

Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three

prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for

support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from

engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device’s electrical

specifications

Final silicon die that conforms to the device’s electrical specifications but has not completed quality

and reliability verification

Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification

testing.

TMDS Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers

describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a

final product and Texas Instruments reserves the right to change or discontinue these products without notice.

TMS devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI’s standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production system

because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

112

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Electrical Specifications

6

Electrical Specifications

This section provides the absolute maximum ratings and the recommended operating conditions for the

TMS320VC5502 DSP.

All electrical and switching characteristics in this data manual are valid over the recommended operating

conditions unless otherwise specified.

6.1 Absolute Maximum Ratings

The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those

listed under Section 6.2, Electrical Specifications, may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those

indicated under Section 6.3, Recommended Operating Conditions, is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability. All supply voltage

values (core and I/O) are with respect to V . Figure 6–1 provides the test load circuit values for a 3.3-V

SS

device. Measured timing information contained in this data manual is based on the test load setup and

conditions shown in Figure 6–1.

6.2 Electrical Specifications

This section provides the absolute maximum ratings for the TMS320VC5502 DSP.

Supply voltage I/O range, DV

Supply voltage core range, CV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.0 V

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 2.0 V

DD

Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.5 V

I

Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.5 V

o

Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

C

Storage temperature range T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55_C to 150_C

stg

6.3 Recommended Operating Conditions

This section provides the recommended operating conditions for the TMS320VC5502 DSP.

MIN NOM

MAX UNIT

DV

CV

PV

Device supply voltage, I/O

Device supply voltage, core

Device supply voltage, PLL

Supply voltage, GND

3.0

1.20

3.0

3.3

1.26

3.3

0

3.6

1.32

3.6

V

DD

V

SS

Hysteresis inputs

DV = 3.0 – 3.6 V

2.2

2

DV

0.3

0.8

DD +

DD

All other inputs

DV = 3.0 – 3.6 V

V

High-level input voltage, I/O

Low-level input voltage, I/O

V

IH

DD

Hysteresis inputs

DV = 3.0 – 3.6 V

–0.3

DD

All other inputs

DV = 3.0 – 3.6 V

V

IL

DD

I

High-level output current

Low-level output current

Operating case temperature

All outputs

– 300

1.5

µA

mA

°C

OH

OL

T

–40

85

C

113

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

6.4 Electrical Characteristics Over Recommended Operating Case Temperature

Range (Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

DV

= 3.3 ± 0.3 V,

= MAX

DD

V

High-level output voltage

2.4

V

OH

I

OH

Low-level output voltage

I

= MAX

0.4

V

OL

Bus holders enabled

DV = MAX,

Output-only or input/output pins

with bus holders

– 300

300

DD

Input current for outputs in

high impedance

V

O

= V

to DV

SS DD

I

IZ

µA

All other output-only or

input/output pins

DV

= MAX,

DD

– 5

5

300

–0.3 V < V < 4.5 V

I

Input pins with internal

pulldown

DV

= MAX,

DD

–0.3 V < V < 4.5 V

I

DV

= MAX,

DD

–0.3 V < V < 4.5 V

X2/CLKIN with oscillator on

X2/CLKIN with oscillator off

TBD

I

DV

= MAX,

DD

–0.3 V < V < 4.5 V

I

Input current

µA

I

Pullup enabled

Input pins with internal pullup

All other input-only pins

DV

= MAX,

– 300

– 5

5

DD

–0.3 V < V < 4.5 V

I

DV

= MAX,

DD

–0.3 V < V < 4.5 V

I

CV

= Nominal

DD

CPU clock = MAX

= 25°C

†

‡

I

CV

DV

PV

supply current, CPU + internal memory access

TBD

mA

DDC

DD

T

C

DV

= Nominal

DD

CPU clock = MAX

= 25°C

§

supply current, pins active

DDD

T

C

PV

DD

= Nominal

30-MHz clock input,

APLL mode = x10

supply current, standby

I

TBD

mA

DDP

Only CLKGEN domain enabled, PLL enabled

T

C

= 25°C

25°C

85°C

TBD

CV

supply current, standby

CV

= Nominal

DD

All domains idled

DD

input clock stopped

I

mA

DDC

DV = Nominal

DD

no pin activity

= 25°C

DV

supply current, standby

DD

TBD

µA

DDD

All domains idled

T

C

Input capacitance

Output capacitance

3

pF

i

o

†

Test Condition: CPU executing 75% Dual-MAC / 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN domains

are active. All other domains are idled. The APLL is enabled.

‡

§

MAX is 300 MHz for the TMS320VC5502-300 and 200 MHz for the TMS320VC5502-200.

Test Condition: One word of a table of 16-bit sine values is written to the EMIF each microsecond (16 Mbps). Each EMIF output pin is connected

to a 10-pF load capacitance.

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Electrical Specifications

Tester Pin Electronics

Data Sheet Timing Reference Point

Output

Under

Test

42 Ω

3.5 nH

Transmission Line

Z0 = 50 Ω

(see note)

Device Pin

(see note)

4.0 pF

1.85 pF

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects

must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.

The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from

the data sheet timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 6–1. 3.3-V Test Load Circuit

6.5 Package Thermal Resistance Characteristics

Table 6–1 and Table 6–2 provide the thermal resistance characteristics for the recommended package types

used on the TMS320VC5502 DSP.

Table 6–1. Thermal Resistance Characteristics (Ambient)

†

PACKAGE

R

(°C/W)

θJA

125

BOARD TYPE

AIRFLOW (LFM)

High-K

0

125

122

118

151

149

143

134

60

High-K

Low-K

High-K

Low-K

150

250

500

0

GGW

150

250

500

0

52

150

250

500

0

49

45

PGF

104

81

150

250

500

73

64

†

BoardtypesareasdefinedbyJEDEC. ReferenceJEDECStandardJESD51–9, TestBoardsforAreaArraySurfaceMountPackage

Thermal Measurements.

115

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

Table 6–2. Thermal Resistance Characteristics (Case)

†

BOARD TYPE

PACKAGE

R

(°C/W)

θJC

27.2

GGW

2s JEDEC Test Card

PGF

13.2

†

Board types are as defined by JEDEC. Reference JEDEC Standard JESD51–9, Test Boards for Area Array Surface

Mount Package Thermal Measurements.

6.6 Timing Parameter Symbology

Timing parameter symbols used in the timing requirements and switching characteristics tables are created

in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related

terminology have been abbreviated as follows:

Lowercase subscripts and their meanings:

Letters and symbols and their meanings:

a

access time

H

L

High

c

cycle time (period)

delay time

Low

d

V

Z

Valid

dis

en

f

disable time

High impedance

enable time

fall time

h

hold time

r

rise time

su

t

setup time

transition time

valid time

v

w

X

pulse duration (width)

Unknown, changing, or don’t care level

6.7 Clock Options

This section provides the timing requirements and switching characteristics for the various clock options

available on the 5502.

6.7.1 Internal System Oscillator With External Crystal

The 5502 includes an internal oscillator which can be used in conjunction with an external crystal or ceramic

resonator to generate the input clock to the DSP. The oscillator requires an external crystal or ceramic

resonator connected across the X1 and X2/CLKIN pins. If the internal oscillator is not used, an external clock

source must be applied to the X2/CLKIN pin and the X1 pin should be left unconnected. Since the internal

oscillator can be used as a clock source to the PLL, the crystal oscillation frequency can be multiplied to

generate the input clock to the different clock groups of the DSP.

GPIO4 is sampled on the rising edge of the reset signal to set the state of the CLKMD0 bit of the Clock Mode

Control Register (CLKMD), which in turns, determines the clock source for the DSP. The CLKMD0 bit selects

either the internal oscillator output (OSCOUT) or the X2/CLKIN pin as the input clock source for the DSP. If

GPIO4 is low at reset, the CLKMD0 bit will be set to ‘0’ and the internal oscillator and the external crystal

generate the input clock for the DSP. If GPIO4 is high, the CLKMD0 bit will be set to ‘1’ and the input clock

will be taken directly from the X2/CLKIN pin.

The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective series

resistance (ESR) as specified in Table 6–3. The connection of the required circuit is shown in Figure 6–2.

Under some conditions, all the components shown are not required. The capacitors, C and C , should be

1

2

chosen such that the equation below is satisfied. C in the equation is the load specified for the crystal that

L

is also specified in Table 6–3.

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Electrical Specifications

C₁C₂

(C₁) C₂)

C_L+

X2/CLKIN

X1

R

S

Crystal

C

2

1

Figure 6–2. Internal System Oscillator With External Crystal

Table 6–3. Recommended Crystal Parameters

MAXIMUM ESR

SPECIFICATIONS (Ω)

MAXIMUM

FREQUENCY RANGE (MHz)

C

(pF)

R

(kΩ)

S

LOAD

10

C

(pF)

SHUNT

20–15

15–12

12–10

10–8

8–6

40

60

80

7

0

16

7

16

2.8

18

2.2

8.8

14

18

6–5

18

The recommended ESR is presented as a maximum, and theoretically, a crystal with a lower maximum ESR

might seem to meet these specifications. However, it is recommended that crystals with actual maximum ESR

specifications as shown in Table 6–3 be used since this will result in maximum crystal performance reliability.

6.7.2 Layout Considerations

Since parasitic capacitance, inductance, and resistance can be significant in this and any circuit, good PC

board layout practices should always be observed when planning trace routing to the discrete components

used in this oscillator circuit. Specifically, the crystal and the associated discrete components should be

locatedasclosetotheDSPasphysicallypossible. Also, X1andX2/CLKINtracesshouldbeseparatedassoon

as possible after routing away from the DSP to minimize parasitic capacitance between them, and a ground

trace should be run between these two signal lines. This also helps to minimize stray capacitance between

these two signals.

117

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

6.7.3 Clock Generation in Bypass Mode (APLL Disabled)

Table 6–4 and Table 6–5 assume testing over recommended operating conditions and H = 0.5t

Figure 6–3).

(see

c(CO)

Table 6–4. CLKIN in Bypass Mode Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

MIN

MAX

†

‡

C7

C8

t

Cycle time, CLKIN

Fall time, CLKIN

Rise time, CLKIN

APLL Synthesis Disabled

20

ns

c(CI)

6

f(CI)

C9

r(CI)

C10

C11

Pulse duration, CLKIN low

Pulse duration, CLKIN high

H – 1 H + 1 H – 1 H + 1

w(CIL)

w(CIH)

†

‡

If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 6–3.

This device utilizes a fully static design and therefore can operate with t

approaching 0 Hz.

approaching ∞. The device is characterized at frequencies

c(CI)

Table 6–5. CLKOUT in Bypass Mode Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

20

1

TYP MAX

MIN

20

1

TYP MAX

‡

C1

C2

C3

C4

C5

C6

t

Cycle time, CLKOUT

t

ns

c(CO)

c(CI)

2

t

Delay time, CLKIN high to CLKOUT high/low

Fall time, CLKOUT

2

1

4

d(CIH-CO)

t

1

f(CO)

t

Rise time, CLKOUT

1

r(CO)

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

H–1

H

H+1

H–1

H

H+1

w(COL)

w(COH)

‡

This device utilizes a fully static design and therefore can operate with t

approaching 0 Hz.

approaching ∞. The device is characterized at frequencies

c(CI)

C9

C8

C7

CLKIN

C6

C3

C1

C4

C2

C5

CLKOUT

NOTE: The relationship of CLKIN to CLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 6–3 is intended

to illustrate the timing parameters only and may differ based on configuration.

Figure 6–3. Bypass Mode Clock Timings

118

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

6.7.4 Clock Generation in Lock Mode (APLL Synthesis Enabled)

The frequency of the reference clock provided at the CLKIN pin can be multiplied by a synthesis factor of N

to generate the internal CPU clock cycle. The synthesis factor is determined by:

M

D₀

N +

where: M = the multiply factor set in the PLLM field of the PLL Multiplier Control Register (PLLM)

D

=

the divide factor set in the PLLDIV0 field of the PLL Divider 0 Register (PLLDIV0)

0

Valid values for M are (multiply by) 2 to 15. Valid values for D are (divide by) 1 – 32.

0

For detailed information on clock generation configuration, see Section 3.9, System Clock Generator.

Table 6–6 and Table 6–7 assume testing over recommended operating conditions and H = 0.5t

Figure 6–4).

(see

c(CO)

Table 6–6. CLKIN in Lock Mode Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

88.3

6

†

‡

10

C7

C8

C9

t

Cycle time, CLKIN

Fall time, CLKIN

Rise time, CLKIN

APLL synthesis enabled

ns

c(CI)

f(CI)

r(CI)

6

†

‡

If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 6–3.

The clock frequency synthesis factor and minimum CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the

specified range [t

].

c(CO)

Table 6–7. CLKOUT in Lock Mode Switching Characteristics

VC5502-200

VC5502-300

TYP MAX

NO.

PARAMETER

UNIT

MIN

5

TYP MAX

MIN

3.33

1

§

/N

§

C1

C2

C3

C4

C5

C6

t

Cycle time, CLKOUT

t

t /N

c(CI)

ns

c(CO)

c(CI)

t

Delay time, CLKIN high/low to CLKOUT high/low

Fall time, CLKOUT

1

2

4

2

4

d(CI-CO)

t

1

f(CO)

t

Rise time, CLKOUT

r(CO)

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

H–1

H

H+1

H–1

H

H+1

w(COL)

w(COH)

§

N = Clock frequency synthesis factor

C8

C9

C7

CLKIN

C2

C1

C3

C5

C6

C4

CLKOUT

Bypass Mode

NOTE: The waveform relationship of CLKIN to CLKOUT depends on the multiply and divide factors chosen. The waveform relationship shown

in Figure 6–4 is intended to illustrate the timing parameters only and may differ based on configuration.

Figure 6–4. External Multiply-by-N Clock Timings

119

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

6.7.5 EMIF Clock Options

Table 6–8 through Table 6–10 assume testing over recommended operating conditions (see Figure 6–5

through Figure 6–7).

†‡

Table 6–8. EMIF Timing Requirements for ECLKIN

VC5502-200

VC5502-300

NO.

UNIT

MIN

10

MAX

E7

E8

t

Cycle time, ECLKIN

16P

ns

c(EKI)

Pulse duration, ECLKIN high

Pulse duration, ECLKIN low

Transition time, ECLKIN

4.5

w(EKIH)

w(EKIL)

t(EKI)

E9

E10

2

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

The reference points for the rise and fall transitions are measured at V MAX and V MIN.

IL IH

§¶#

Table 6–9. EMIF Switching Characteristics for ECLKOUT1

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

E + 0.7

E1

E2

E3

E4

E5

E6

t

Cycle time, ECLKOUT1

E – 0.7

ns

c(EKO1)

Pulse duration, ECLKOUT1 high

Pulse duration, ECLKOUT1 low

Transition time, ECLKOUT1

EH – 0.7 EH + 0.7

EL – 0.7 EL + 0.7

1

w(EKO1H)

w(EKO1L)

t(EKO1)

Delay time, ECLKIN high to ECLKOUT1 high

Delay time, ECLKIN low to ECLKOUT1 low

3

8

d(EKIH-EKO1H)

d(EKIL-EKO1L)

§

¶

#

The reference points for the rise and fall transitions are measured at V

MAX and V

MIN.

OH

OL

E = the EMIF input clock (CPU clock, CPU/2 clock, or CPU/4 clock) period in ns for EMIF.

EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIF.

E7

E10

E8

ECLKIN

E9

E10

Figure 6–5. ECLKIN Timings for EMIF

ECLKIN

E1

E6

E2

E4

E3

E5

ECLKOUT1

Figure 6–6. ECLKOUT1 Timings for EMIF Module

120

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

†‡

Table 6–10. EMIF Switching Characteristics for ECLKOUT2

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

E11

E12

E13

E14

E15

E16

t

Cycle time, ECLKOUT2

NE – 0.7

NE + 0.7

ns

c(EKO2)

Pulse duration, ECLKOUT2 high

Pulse duration, ECLKOUT2 low

Transition time, ECLKOUT2

0.5NE – 0.7

0.5NE + 0.7

w(EKO2H)

w(EKO2L)

0.5NE + 0.7

1

8

t(EKO2)

Delay time, ECLKIN high to ECLKOUT2 high

Delay time, ECLKIN high to ECLKOUT2 low

3

d(EKIH-EKO2H)

d(EKIH-EKO2L)

†

‡

The reference points for the rise and fall transitions are measured at V

E = the EMIF input clock (CPU clock, CPU/2 clock, or CPU/4 clock) period in ns for EMIF.

N = the EMIF input clock divider; N = 1, 2, or 4.

MAX and V

MIN.

OH

OL

E16

E15

ECLKIN

E11

E12

E14

E13

ECLKOUT2

Figure 6–7. ECLKOUT2 Timings for EMIF Module

121

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

6.8 Memory Timings

6.8.1 Asynchronous Memory Timings

Table 6–11 and Table 6–12 assume testing over recommended operating conditions (see Figure 6–8 and

Figure 6–9).

†‡

Table 6–11. Asynchronous Memory Cycle Timing Requirements for ECLKIN

VC5502-200

VC5502-300

NO.

UNIT

MIN

6

MAX

A3

A4

A6

A7

t

Setup time, EMIF.Dx valid before EMIF.ARE high

Hold time, EMIF.Dx valid after EMIF.ARE high

Setup time, EMIF.ARDY valid before ECLKOUT1 high

Hold time, EMIF.ARDY valid after ECLKOUT1 high

ns

su(EDV-AREH)

1

h(AREH-EDV)

3

su(ARDY-EKO1H)

h(EKO1H-ARDY)

1

†

‡

To ensure data setup time, simply program the strobe width wide enough. EMIF.ARDY is internally synchronized. The EMIF.ARDY signal is

recognized in the cycle for which the setup and hold time is met. To use EMIF.ARDY as an asynchronous input, the pulse width of the EMIF.ARDY

signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.

RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are

programmed via the EMIF CE space control registers.

‡§¶

Table 6–12. Asynchronous Memory Cycle Switching Characteristics for ECLKOUT1

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

RS * E – 1.5

RH * E – 1.5

1.5

MAX

A1

A2

t

Output setup time, select signals valid to EMIF.ARE low

Output hold time, EMIF.ARE high to select signals invalid

Delay time, ECLKOUT1 high to EMIF.ARE valid

ns

osu(SELV-AREL)

oh(AREH-SELIV)

d(EKO1H-AREV)

osu(SELV-AWEL)

oh(AWEH-SELIV)

d(EKO1H-AWEV)

A5

5

A8

Output setup time, select signals valid to EMIF.AWE low

Output hold time, EMIF.AWE high to select signals invalid

Delay time, ECLKOUT1 high to EMIF.AWE valid

WS * E – 1.5

WH * E – 1.5

1.5

A9

A10

5

‡

RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are

programmed via the EMIF CE space control registers.

§

¶

E = ECLKOUT1 period in ns for EMIF.

Select signals for EMIF include: EMIF.CEx, EMIF.BE[3:0], EMIF.A[21:2], and EMIF.AOE; and for EMIF writes, include EMIF.D[31:0].

122

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

Setup = 2

Strobe = 3

Not Ready

Hold = 2

ECLKOUT1

EMIF.CEx

A1

A2

EMIF.BE[3:0]

EMIF.A[21:2]

BE

Address

A3

A4

EMIF.D[31:0]

A1

A5

A2

A5

Read Data

†

EMIF.AOE/SOE/SDRAS

†

EMIF.ARE/SADS/SDCAS/SRE

†

EMIF.AWE/SWE/SDWE

A7

A6

EMIF.ARDY

†

EMIF.AOE/SOE/SDRAS, EMIF.ARE/SADS/SDCAS/SRE, and EMIF.AWE/SWE/SDWE operate as EMIF.AOE (identified under select signals),

EMIF.ARE, and EMIF.AWE, respectively, during asynchronous memory accesses.

†

Figure 6–8. Asynchronous Memory Read Timings

123

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

Setup = 2

A8

Hold = 2

Strobe = 3

Not Ready

ECLKOUT1

A9

EMIF.CEx

EMIF.BE[3:0]

EMIF.A[21:2]

EMIF.D[31:0]

A8

BE

Address

Write Data

A8

A9

†

EMIF.AOE/SOE/SDRAS

†

EMIF.ARE/SADS/SDCAS/SRE

A10

†

EMIF.AWE/SWE/SDWE

A7

A6

EMIF.ARDY

†

EMIF.AOE/SOE/SDRAS, EMIF.ARE/SADS/SDCAS/SRE, and EMIF.AWE/SWE/SDWE operate as EMIF.AOE (identified under select signals),

EMIF.ARE, and EMIF.AWE, respectively, during asynchronous memory accesses.

†

Figure 6–9. Asynchronous Memory Write Timings

124

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

6.8.2 Programmable Synchronous Interface Timings

Table 6–13 and Table 6–14 assume testing over recommended operating conditions (see Figure 6–10

through Figure 6–12).

Table 6–13. Programmable Synchronous Interface Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

2

MAX

PS6

PS7

t

Setup time, read EMIF.Dx valid before ECLKOUTx high

Hold time, read EMIF.Dx valid after ECLKOUTx high

ns

su(EDV-EKOxH)

1.5

h(EKOxH-EDV)

†

Table 6–14. Programmable Synchronous Interface Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

PS1

PS2

PS3

PS4

PS5

PS8

PS9

PS10

PS11

PS12

t

Delay time, ECLKOUTx high to EMIF.CEx valid

Delay time, ECLKOUTx high to EMIF.BEx valid

Delay time, ECLKOUTx high to EMIF.BEx invalid

Delay time, ECLKOUTx high to EMIF.Ax valid

Delay time, ECLKOUTx high to EMIF.Ax invalid

Delay time, ECLKOUTx high to EMIF.SADS/SRE valid

Delay time, ECLKOUTx high to, EMIF.SOE valid

Delay time, ECLKOUTx high to EMIF.Dx valid

Delay time, ECLKOUTx high to EMIF.Dx invalid

Delay time, ECLKOUTx high to EMIF.SWE valid

1

5

ns

d(EKOxH-CEV)

d(EKOxH-BEV)

d(EKOxH-BEIV)

d(EKOxH-EAV)

d(EKOxH-EAIV)

d(EKOxH-ADSV)

d(EKOxH-OEV)

d(EKOxH-EDV)

d(EKOxH-EDIV)

d(EKOxH-WEV)

1

5

1

5

1

5

†

The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2):

–

Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

EMIF.CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, EMIF.CEx goes inactive after the final command has

been issued (CEEXT = 0). For synchronous FIFO interface with glue, EMIF.CEx is active when EMIF.SOE is active (CEEXT = 1).

Function of EMIF.SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, EMIF.SADS/SRE acts as EMIF.SADS with deselect

cycles (RENEN = 0). For FIFO interface, EMIF.SADS/SRE acts as EMIF.SRE with NO deselect cycles (RENEN = 1).

Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2

–

125

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

‡

READ latency = 2

ECLKOUTx

PS1

†

EMIF.CEx

PS2

BE1

PS3

EMIF.BE[3:0]

BE2

BE3

A3

BE4

PS5

EA3

PS4

A1

EMIF.A[21:2]

A2

A4

PS6

PS7

Q2

EMIF.D[31:0]

Q1

Q3

Q4

PS8

PS9

PS8

EMIF.ARE/SADS/

§

SDCAS/SRE

PS9

§

EMIF.AOE/SOE/SDRAS

§

EMIF.AWE/SWE/SDWE

†

‡

The read latency and the length of EMIF.CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIF CE

Secondary Control Registers (CEx_SC1, CEx_SC2). In the figure, SYNCRL = 2 and CEEXT = 0.

The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2):

–

Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

EMIF.CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, EMIF.CEx goes inactive after the final command has

been issued (CEEXT = 0). For synchronous FIFO interface with glue, EMIF.CEx is active when EMIF.SOE is active (CEEXT = 1).

Function of EMIF.SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, EMIF.SADS/SRE acts as EMIF.SADS with deselect

cycles (RENEN = 0). For FIFO interface, EMIF.SADS/SRE acts as EMIF.SRE with NO deselect cycles (RENEN = 1).

Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2

–

§

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, and EMIF.AWE/SWE/SDWE operate as EMIF.SADS/SRE, EMIF.SOE, and

EMIF.SWE, respectively, during programmable synchronous interface accesses.

Figure 6–10. Programmable Synchronous Interface Read Timings (With Read Latency = 2)

126

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

ECLKOUTx

PS1

†

EMIF.CEx

PS2

BE1

PS3

PS5

EMIF.BE[3:0]

BE2

A2

BE3

A3

BE4

A4

PS4

A1

EMIF.A[21:2]

EMIF.D[31:0]

PS10

Q1

PS11

PS8

Q2

Q3

Q4

PS8

‡

EMIF.ARE/SADS/SDCAS/SRE

‡

EMIF.AOE/SOE/SDRAS

PS12

‡

EMIF.AWE/SWE/SDWE

†

‡

The write latency and the length of EMIF.CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF CE

Secondary Control Registers (CEx_SC1, CEx_SC2). In this figure, SYNCWL = 0 and CEEXT = 0.

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, and EMIF.AWE/SWE/SDWE operate as EMIF.SADS/SRE, EMIF.SOE, and

EMIF.SWE, respectively, during programmable synchronous interface accesses.

Figure 6–11. Programmable Synchronous Interface Write Timings (With Write Latency = 0)

127

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

Write

Latency =

‡

1

ECLKOUTx

PS1

†

EMIF.CEx

EMIF.BE[3:0]

EMIF.A[21:2]

PS3

PS5

PS2

BE1

BE2

A2

BE3

A3

BE4

A4

PS4

A1

PS10

Q1

PS10

PS11

PS8

EMIF.D[31:0]

Q2

Q3

Q4

PS8

EMIF.ARE/SADS/

§

SDCAS/SRE

§

EMIF.AOE/SOE/SDRAS

PS12

§

EMIF.AWE/SWE/SDWE

†

‡

The write latency and the length of EMIF.CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF CE

Secondary Control Registers (CEx_SC1, CEx_SC2). In this figure, SYNCWL = 1 and CEEXT = 0.

The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2):

–

Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

EMIF.CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, EMIF.CEx goes inactive after the final command has

been issued (CEEXT = 0). For synchronous FIFO interface with glue, EMIF.CEx is active when EMIF.SOE is active (CEEXT = 1).

Function of EMIF.SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, EMIF.SADS/SRE acts as EMIF.SADS with deselect

cycles (RENEN = 0). For FIFO interface, EMIF.SADS/SRE acts as EMIF.SRE with NO deselect cycles (RENEN = 1).

Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2

–

§

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, and EMIF.AWE/SWE/SDWE operate as EMIF.SADS/SRE, EMIF.SOE, and

EMIF.SWE, respectively, during programmable synchronous interface accesses.

Figure 6–12. Programmable Synchronous Interface Write Timings (With Write Latency = 1)

128

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

6.8.3 Synchronous DRAM Timings

Table 6–15 and Table 6–16 assume testing over recommended operating conditions (see Figure 6–13

through Figure 6–20).

Table 6–15. Synchronous DRAM Cycle Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN MAX

SD6

SD7

t

Setup time, read EMIF.Dx valid before ECLKOUT1 high

Hold time, read EMIF.Dx valid after ECLKOUT1 high

0.5

2

ns

su(EDV-EKO1H)

h(EKO1H-EDV)

Table 6–16. Synchronous DRAM Cycle Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

SD1

SD2

t

Delay time, ECLKOUT1 high to EMIF.CEx valid/invalid

Delay time, ECLKOUT1 high to EMIF.BEx valid

Delay time, ECLKOUT1 high to EMIF.BEx invalid

Delay time, ECLKOUT1 high to EMIF.Ax valid

Delay time, ECLKOUT1 high to EMIF.Ax invalid

Delay time, ECLKOUT1 high to EMIF.SDCAS valid

Delay time, ECLKOUT1 high to EMIF.Dx valid

Delay time, ECLKOUT1 high to EMIF.Dx invalid

Delay time, ECLKOUT1 high to EMIF.SDWE valid

Delay time, ECLKOUT1 high to EMIF.SDRAS valid

Delay time, ECLKOUT1 high to EMIF.SDCKE valid

1

5

ns

d(EKO1H-CEV)

d(EKO1H-BEV)

d(EKO1H-BEIV)

d(EKO1H-EAV)

d(EKO1H-EAIV)

d(EKO1H-CASV)

d(EKO1H-EDV)

d(EKO1H-EDIV)

d(EKO1H-WEV)

d(EKO1H-RASV)

d(EKO1H-CKEV)

SD3

1

SD4

5

SD5

1

SD8

5

SD9

SD10

SD11

SD12

SD13

1

5

129

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

READ

ECLKOUT1

SD1

EMIF.CEx

SD2

BE1

SD3

EMIF.BE[3:0]

BE2

BE3

BE4

SD4

SD5

Bank

EMIF.A[21:13]

EMIF.A[11:2]

SD4

Column

SD4

EMIF.A12

SD6

SD7

D2

EMIF.D[31:0]

D1

D3

D4

†

EMIF.AOE/SOE/SDRAS

SD8

EMIF.ARE/SADS/

†

SDCAS/SRE

†

EMIF.AWE/SWE/SDWE

†

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and

EMIF.SDRAS, respectively, during SDRAM accesses.

Figure 6–13. SDRAM Read Command (CAS Latency 3)

WRITE

ECLKOUT1

SD1

SD2

SD1

SD2

EMIF.CEx

SD3

EMIF.BE[3:0]

BE1

SD4

Bank

SD4

Column

BE2

BE3

BE4

SD5

SD9

EMIF.A[21:13]

EMIF.A[11:2]

EMIF.A12

SD4

SD9

SD10

EMIF.D[31:0]

D1

D2

D3

D4

†

EMIF.AOE/SOE/SDRAS

SD8

EMIF.ARE/SADS/

†

SDCAS/SRE

SD11

†

EMIF.AWE/SWE/SDWE

†

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and

EMIF.SDRAS, respectively, during SDRAM accesses.

Figure 6–14. SDRAM Write Command

130

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

ACTV

ECLKOUT1

SD1

SD4

SD1

EMIF.CEx

EMIF.BE[3:0]

SD5

Bank Activate

EMIF.A[21:13]

EMIF.A[11:2]

SD4

Row Address

SD4

Row Address

EMIF.A12

EMIF.D[31:0]

SD12

†

EMIF.AOE/SOE/SDRAS

EMIF.ARE/SADS/

†

SDCAS/SRE

†

EMIF.AWE/SWE/SDWE

†

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and

EMIF.SDRAS, respectively, during SDRAM accesses.

Figure 6–15. SDRAM ACTV Command

DCAB

ECLKOUT1

SD1

EMIF.CEx

EMIF.BE[3:0]

EMIF.A[21:13, 11:2]

SD4

SD5

EMIF.A12

EMIF.D[31:0]

SD12

SD11

SD12

SD11

†

EMIF.AOE/SOE/SDRAS

†

EMIF.ARE/SADS/SDCAS/SRE

†

EMIF.AWE/SWE/SDWE

†

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and

EMIF.SDRAS, respectively, during SDRAM accesses.

Figure 6–16. SDRAM DCAB Command

131

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

DEAC

ECLKOUT1

SD1

EMIF.CEx

EMIF.BE[3:0]

SD4

SD5

EMIF.A[21:13]

EMIF.A[11:2]

Bank

SD4

SD5

EMIF.A12

EMIF.D[31:0]

SD12

SD11

SD12

SD11

†

EMIF.AOE/SOE/SDRAS

EMIF.ARE/SADS/

†

SDCAS/SRE

†

EMIF.AWE/SWE/SDWE

†

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and

EMIF.SDRAS, respectively, during SDRAM accesses.

Figure 6–17. SDRAM DEAC Command

REFR

ECLKOUT1

SD1

EMIF.CEx

EMIF.BE[3:0]

EMIF.A[21:13, 11:2]

EMIF.A12

EMIF.D[31:0]

SD12

SD8

SD12

SD8

†

EMIF.AOE/SOE/SDRAS

EMIF.ARE/SADS/

†

SDCAS/SRE

†

EMIF.AWE/SWE/SDWE

†

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and

EMIF.SDRAS, respectively, during SDRAM accesses.

Figure 6–18. SDRAM REFR Command

132

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

MRS

ECLKOUT1

SD1

SD4

SD1

SD5

EMIF.CEx

EMIF.BE[3:0]

MRS value

EMIF.A[21:2]

EMIF.D[31:0]

SD12

SD8

SD12

SD8

†

EMIF.AOE/SOE/SDRAS

EMIF.ARE/SADS/

†

SDCAS/SRE

SD11

†

EMIF.AWE/SWE/SDWE

†

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and

EMIF.SDRAS, respectively, during SDRAM accesses.

Figure 6–19. SDRAM MRS Command

≥ TRAS cycles

End Self-Refresh

Self Refresh

ECLKOUT1

EMIF.CEx

EMIF.BE[3:0]

EMIF.A[21:13, 11:2]

EMIF.A12

EMIF.D[31:0]

†

EMIF.AOE/SOE/SDRAS

EMIF.ARE/SADS/

†

SDCAS/SRE

†

EMIF.AWE/SWE/SDWE

SD13

EMIF.SDCKE

†

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and

EMIF.SDRAS, respectively, during SDRAM accesses.

Figure 6–20. SDRAM Self-Refresh Timings

133

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

6.9 HOLD/HOLDA Timings

Table 6–17 and Table 6–18 assume testing over recommended operating conditions (see Figure 6–21).

†

Table 6–17. EMIF.HOLD/HOLDA Timing Requirements

VC5502-200

VC5502-300

NO.

H3

UNIT

MIN MAX

t

Hold time, EMIF.HOLD low after EMIF.HOLDA low

E

ns

oh(HOLDAL-HOLDL)

†

E = the EMIF input clock (ECLKIN, CPU/1 clock, CPU1/2 clock, or CPU1/4 clock) period in ns for EMIF.

†‡§

Table 6–18. EMIF.HOLD/HOLDA Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

4E

0

MAX

¶

H1

H2

H4

H5

H6

H7

t

Delay time, EMIF.HOLD low to EMIF Bus high impedance

Delay time, EMIF Bus high impedance to EMIF.HOLDA low

Delay time, EMIF.HOLD high to EMIF Bus low impedance

Delay time, EMIF Bus low impedance to EMIF.HOLDA high

Delay time, EMIF.HOLD low to ECLKOUTx high impedance

Delay time, EMIF.HOLD high to ECLKOUTx low impedance

ns

d(HOLDL-EMHZ)

d(EMHZ-HOLDAL)

d(HOLDH-EMLZ)

d(EMLZ-HOLDAH)

d(HOLDL-EKOHZ)

d(HOLDH-EKOLZ)

2E

7E

2E

0

2E

¶

4E

2E

7E

†

‡

E = the EMIF input clock (ECLKIN, CPU/1 clock, CPU1/2 clock, or CPU1/4 clock) period in ns for EMIF.

EMIF Bus consists of: EMIF.CE[3:0], EMIF.BE[3:0], EMIF.D[31:0], EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS,

EMIF.AWE/SWE/SDWE, EMIF.SDCKE, and EMIF.SOE3.

§

¶

The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during EMIF.HOLDA.

If EKxHZ = 0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown

in Figure 6–21.

All pending EMIF transactions are allowed to complete before EMIF.HOLDA is asserted. If no bus transactions are occurring, then the minimum

delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

External Requestor

DSP Owns Bus

Owns Bus

H3

EMIF.HOLD

H2

H5

EMIF.HOLDA

H1

H4

H7

†

EMIF Bus

5502

ECLKOUTx

H6

†

EMIF Bus consists of: EMIF.CE[3:0], EMIF.BE[3:0], EMIF.D[31:0], EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS,

EMIF.AWE/SWE/SDWE, EMIF.SDCKE, and EMIF.SOE3.

Figure 6–21. EMIF.HOLD/HOLDA Timings

134

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

6.10 Reset Timings

Table 6–19 and Table 6–20 assume testing over recommended operating conditions (see Figure 6–22).

†

Table 6–19. Reset Timing Requirements

VC5502-200

VC5502-300

NO.

R1

UNIT

MIN

MAX

t

Pulse width, RESET low

2P + 5

ns

w(RSL)

†

P = the period of the clock on the X2/CLKIN pin in ns. For example, when using 20 MHz as the input clock, use P = 50 ns.

†

Table 6–20. Reset Switching Characteristics

VC5502-200

VC5502-300

NO.

R2

PARAMETER

UNIT

MIN

MAX

‡

t

Delay time, RESET low to EMIF group high impedance

6

ns

d(RSL-EMIFHZ)

GPIO4 = 0 (CLKMOD = 0)

GPIO4 = 1 (CLKMOD = 1)

41102P + 6

70P + 6

6

‡

R3

R4

t

Delay time, RESET high to EMIF group valid

ns

d(RSH-EMIFV)

d(RSL-HIGHIV)

§

t

Delay time, RESET low to high group invalid

GPIO4 = 0 (CLKMOD = 0)

41102P + 6

§

R5

R6

R7

t

Delay time, RESET high to high group valid

ns

d(RSH-HIGHV)

d(RSL-ZHZ)

d(RSH-ZV)

GPIO4 = 1 (CLKMOD = 1)

70P + 6

¶

Delay time, RESET low to Z group high impedance

6

GPIO4 = 0 (CLKMOD = 0)

GPIO4 = 1 (CLKMOD = 1)

41102P + 6

¶

Delay time, RESET high to Z group invalid

70P + 6

#

R8

R9

t

Delay time, RESET low to Input/Output group switch to input mode

6

ns

d(RSL-IOIM)

||

Delay time, RESET low to Toggle group switch to default toggle frequency

d(RSL-TGLD)

†

‡

P = the period of the clock on the X2/CLKIN pin in ns. For example, when using 20 MHz as the input clock, use P = 50 ns.

EMIF group: EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, EMIF.AWE/SWE/SDWE, EMIF.ARDY, EMIF.CE0,

EMIF.CE1, EMIF.CE2, EMIF.CE3, EMIF.BE0, EMIF.BE1, EMIF.BE2, EMIF.BE3, EMIF.SDCKE, EMIF.SOE3, EMIF.HOLD, EMIF.HOLDA,

ECLKOUT1.

EMIF.ARDY and EMIF.HOLDA do not go to a high-impedance state during reset since they are input-only signals; they are included here simply

for completeness.

High group: IACK, XF, SCL (assumes external pullup on pin), SDA (assumes external pullup on pin), UART.TX, TDO.

Z group: HRDY, HINT, DX2, DX1, DX0

Input/Outputgroup:PGPIO[45:0],HPI.HA[15:0],HPI.HD[15:0],EMIF.D[31:0],HPI.HAS, HPI.HBIL, HCNTL1, HCNTL0, HCS,R/W, HDS1,HDS2,

NMI/WDTOUT, GPIO[7:0], TIM0, TIM1, CLKR0, CLKX0, FSR0, FSX0, CLKR1, CLKX1, FSR1, FSX1, CLKR2, CLKX2, FSR2, FSX2, EMU0,

EMU1/OFF. Signals in this group switch to input mode with reset.

§

¶

#

||

Toggle group: ECLKOUT2, CLKOUT. Pins in this group toggle with a default frequency during reset.

135

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

R1

RESET

R3

R5

R2

R4

R6

†

‡

§

EMIF Group

High Group

Z Group

R7

R8

R9

¶

Input/Output Group

#

Toggle Group

†

EMIF group: EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, EMIF.AWE/SWE/SDWE, EMIF.ARDY, EMIF.CE0,

EMIF.CE1, EMIF.CE2, EMIF.CE3, EMIF.BE0, EMIF.BE1, EMIF.BE2, EMIF.BE3, EMIF.SDCKE, EMIF.SOE3, EMIF.HOLD, EMIF.HOLDA,

ECLKOUT1.

EMIF.ARDY and EMIF.HOLDA do not go to a high-impedance state during reset since they are input-only signals; they are included here simply

for completeness.

High group: IACK, XF, SCL (assumes external pullup on pin), SDA (assumes external pullup on pin), UART.TX, TDO.

Z group: HRDY, HINT, DX2, DX1, DX0

Input/Output group: PGPIO[45:0], HPI.HA[15:0], HPI.HD[15:0], EMIF.D[31:0], HPI.HAS, HPI.HBIL, HCNTL1, HCNTL0, HCS, R/W, HDS1,

HDS2, NMI/WDTOUT, GPIO[7:0], TIM0, TIM1, CLKR0, CLKX0, FSR0, FSX0, CLKR1, CLKX1, FSR1, FSX1, CLKR2, CLKX2, FSR2, FSX2,

EMU0, EMU1/OFF. Signals in this group switch to input mode with reset.

‡

§

¶

#

Toggle group: ECLKOUT2, CLKOUT. Pins in this group toggle with a default frequency during reset.

Figure 6–22. Reset Timings

136

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

6.11 External Interrupt and Interrupt Acknowledge (IACK) Timings

Table 6–21 and Table 6–22 assume testing over recommended operating conditions (see Figure 6–23 and

Figure 6–24).

Table 6–21. External Interrupt and Interrupt Acknowledge Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

†

I1

I2

t

Pulse width, interrupt low, CPU active

Pulse width, interrupt high, CPU active

3P

2P

ns

w(INTL)A

†

w(INTH)A

†

P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

Table 6–22. External Interrupt and Interrupt Acknowledge Switching Characteristics

VC5502-200

VC5502-300

NO.

I3

PARAMETER

UNIT

MIN

MAX

t

Delay time, CLKOUT high to IACK valid

0

6

ns

d(COH-IACKV)

I1

INTx, NMI

I2

Figure 6–23. External Interrupt Timings

CLKOUT

I3

IACK

Figure 6–24. External Interrupt Acknowledge Timings

137

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

6.12 XF Timings

Table 6–23 assumes testing over recommended operating conditions (see Figure 6–25).

Table 6–23. XF Switching Characteristics

VC5502-200

VC5502-300

NO.

X1

PARAMETER

UNIT

MIN

0

MAX

Delay time, CLKOUT high to XF high

Delay time, CLKOUT high to XF low

3

t

ns

d(XF)

0

CLKOUT

X1

XF

Figure 6–25. XF Timings

138

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

6.13 General-Purpose Input/Output (GPIOx) Timings

Table 6–24 and Table 6–25 assume testing over recommended operating conditions (see Figure 6–26).

Table 6–24. GPIO Pins Configured as Inputs Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

4

MAX

G2

G3

t

Setup time, GPIOx input valid before CLKOUT high

Hold time, GPIOx input valid after CLKOUT high

ns

su(GPIO–COH)

0

h(COH–GPIO)

Table 6–25. GPIO Pins Configured as Outputs Switching Characteristics

VC5502-200

VC5502-300

NO.

G1

PARAMETER

UNIT

MIN

MAX

t

Delay time, CLKOUT high to GPIOx output change

0

8

ns

d(COH–GPIO)

CLKOUT

G2

G3

GPIOx

Input Mode

G1

GPIOx

Output Mode

Figure 6–26. General-Purpose Input/Output (GPIOx) Signal Timings

139

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

6.14 Parallel General-Purpose Input/Output (PGPIOx) Timings

Table 6–26 and Table 6–27 assume testing over recommended operating conditions (see Figure 6–27).

Table 6–26. PGPIO Pins Configured as Inputs Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

4.3

0

MAX

PG2

PG3

t

Setup time, PGPIOx input valid before CLKOUT high

Hold time, PGPIOx input valid after CLKOUT high

ns

su(PGPIO–COH)

h(COH–PGPIO)

Table 6–27. PGPIO Pins Configured as Outputs Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

PG1

t

Delay time, CLKOUT high to PGPIOx output change

6.8

ns

d(COH–PGPIO)

CLKOUT

PG2

PG3

PGPIOx

Input Mode

PG1

PGPIOx

Output Mode

Figure 6–27. Parallel General-Purpose Input/Output (PGPIOx) Signal Timings

140

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

6.15 TIM0/TIM1/WDTOUT Timings

6.15.1 TIM0/TIM1/WDTOUT Timer Pin Timings

Table 6–28 and Table 6–29 assume testing over recommended operating conditions (see Figure 6–28 and

Figure 6–29).

†

Table 6–28. TIM0/TIM1/WDTOUT Pins Configured as Timer Input Pins Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

P/4

MAX

T4

T5

t

Pulse width, TIM0/TIM1/WDTOUT low

Pulse width, TIM0/TIM1/WDTOUT high

ns

w(TIML)

w(TIMH)

†

P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

Table 6–29. TIM0/TIM1/WDTOUT Pins Configured as Timer Output Pins Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

0

MAX

T1

T2

T3

t

Delay time, CLKOUT high to TIM0/TIM1/WDTOUT high

Delay time, CLKOUT high to TIM0/TIM1/WDTOUT low

Pulse duration, TIM0/TIM1/WDTOUT

5

ns

d(COH–TIMH)

d(COH–TIML)

w(TIM)

0

†

P

†

P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

T5

T4

TIM0/TIM1/WDTOUT

as Input

Figure 6–28. TIM0/TIM1/WDTOUT Timings When Configured as Timer Input Pins

CLKOUT

T2

T1

TIM0/TIM1/WDTOUT

as Output

T3

Figure 6–29. TIM0/TIM1/WDTOUT Timings When Configured as Timer Output Pins

141

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

6.15.2 TIM0/TIM1/WDTOUT General-Purpose I/O Timings

Table 6–30 and Table 6–31 assume testing over recommended operating conditions (see Figure 6–30).

†

Table 6–30. TIM0/TIM1/WDTOUT General-Purpose I/O Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

3

MAX

T9

t

Setup time, TIM0-GPIO input mode before CLKOUT high

Hold time, TIM0-GPIO input mode after CLKOUT high

Setup time, TIM1-GPIO input mode before CLKOUT high

Hold time, TIM1-GPIO input mode after CLKOUT high

Setup time, WDTOUT-GPIO input mode before CLKOUT high

Hold time, WDTOUT-GPIO input mode after CLKOUT high

ns

su(TIM0GPIO–COH)

h(COH–TIM0GPIO)

su(TIM1GPIO–COH)

h(COH–TIM1GPIO)

su(WDTGPIO–COH)

h(COH–WDTGPIO)

T10

T11

T12

T13

T14

0

3

0

3

0

†

In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

†

Table 6–31. TIM0/TIM1/WDTOUT General-Purpose I/O Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

4.9

T6

T7

T8

t

Delay time, CLKOUT high to TIM0-GPIO output mode

Delay time, CLKOUT high to TIM1-GPIO output mode

Delay time, CLKOUT high to WDTOUT-GPIO output mode

ns

d(COH–TIM0GPIO)

d(COH–TIM1GPIO)

d(COH–WDTGPIO)

4.9

4.6

†

In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

142

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

CLKOUT

T9

T10

T12

T14

TIM0 GPIO

Input Mode

T6

TIM0 GPIO

Output Mode

T11

TIM1 GPIO

Input Mode

T7

TIM1 GPIO

Output Mode

T13

WDTOUT GPIO

Input Mode

T8

WDTOUT GPIO

Output Mode

Figure 6–30. TIM0/TIM1/WDTOUT General-Purpose I/O Timings

143

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

6.15.3 TIM0/TIM1/WDTOUT Interrupt Timings

Table 6–32 assumes testing over recommended operating conditions (see Figure 6–31).

†‡

Table 6–32. TIM0/TIM1/WDTOUT Interrupt Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

3

MAX

§

T15

T16

T17

T18

T19

T20

T21

T22

T23

t

Setup time, TIM0 low before CLKOUT rising edge

ns

su(TIM0L–COH)

h(COH–TIM0L)

w(TIM0L)

§

Hold time, TIM0 low after CLKOUT rising edge

0

§

Pulse width, TIM0 low

P

3

§

Setup time, TIM1 low before CLKOUT rising edge

su(TIM1L–COH)

h(COH–TIM1L)

w(TIM1L)

§

Hold time, TIM1 low after CLKOUT rising edge

0

§

Pulse width, TIM1 low

Setup time, WDTOUT low before CLKOUT rising edge

P

3

§

su(WDTL–COH)

h(COH–WDTL)

w(WDTL)

§

Hold time, WDTOUT low after CLKOUT rising edge

0

§

Pulse width, WDTOUT low

P

†

‡

In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

Aninterruptcanbetriggeredbysettingthetimerpinshighorlow,dependingonthesettingoftheTIN1INVbitintheGPIOInterruptControlRegister

(GPINT). Refer to the TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618) for more information on the interrupt

capability of the timer pins.

§

CLKOUT

T15

T16

T17

TIM0

T18

T19

T20

TIM1

T21

T22

T23

WDTOUT

Figure 6–31. TIM0/TIM1/WDTOUT Interrupt Timings

144

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

6.16 Multichannel Buffered Serial Port (McBSP) Timings

6.16.1 McBSP Transmit and Receive Timings

Table 6–33 and Table 6–34 assume testing over recommended operating conditions (see Figure 6–32 and

Figure 6–33).

†‡

Table 6–33. McBSP Transmit and Receive Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

2P

MAX

M11

M12

t

Cycle time, CLKR/X

CLKR/X ext

ns

c(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

P – 1

w(CKRX)

M13

M14

t

Rise time, CLKR/X

Fall time, CLKR/X

CLKR/X ext

5

ns

r(CKRX)

f(CKRX)

t

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKX int

CLKX ext

CLKX int

CLKX ext

5

1

0

6

3

1

0

6

5

1

0

6

M15

M16

M17

M18

M19

M20

t

Setup time, external FSR high before CLKR low

Hold time, external FSR high after CLKR low

Setup time, DR valid before CLKR low

ns

su(FRH–CKRL)

h(CKRL–FRH)

su(DRV–CKRL)

h(CKRL–DRV)

su(FXH–CKXL)

h(CKXL–FXH)

Hold time, DR valid after CLKR low

Setup time, external FSX high before CLKX low

Hold time, external FSX high after CLKX low

†

‡

Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are

also inverted.

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

145

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

†‡

Table 6–34. McBSP Transmit and Receive Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

M1

M2

M3

t

Cycle time, CLKR/X

CLKR/X int

CLKR int

CLKR ext

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

2P

ns

c(CKRX)

§

Pulse duration, CLKR/X high

Pulse duration, CLKR/X low

D–1

C–1

D+1

w(CKRXH)

w(CKRXL)

§

C+1

–2

4

6

M4

M5

M6

t

Delay time, CLKR high to internal FSR valid

Delay time, CLKX high to internal FSX valid

ns

d(CKRH–FRV)

d(CKXH–FXV)

dis(CKXH–DXHZ)

16

6

–2

4

16

5

–5

1

Disable time, CLKX high to DX high impedance

following last data bit

11

6

Delay time, CLKX high to DX valid.

This applies to all bits except the first bit transmitted.

16

6

¶

Delay time, CLKX high to DX valid

DXENA = 0

M7

t

ns

d(CKXH–DXV)

CLKX ext

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

CLKX ext

FSX int

16

2P+2

2P+8

Only applies to first bit transmitted

when in Data Delay

(XDATDLY=01b or 10b) modes

1

or

2

DXENA = 1

DXENA = 0

DXENA = 1

DXENA = 0

DXENA = 1

DXENA = 0

DXENA = 1

¶

0

6

Enable time, CLKX high to DX driven

M8

M9

t

ns

en(CKXH–DX)

d(FXH–DXV)

en(FXH–DX)

Only applies to first bit transmitted

when in Data Delay

(XDATDLY=01b or 10b) modes

2P

1

or

2

2P+6

¶

1

7

Delay time, FSX high to DX valid

FSX ext

FSX int

Only applies to first bit transmitted

when in Data Delay 0 (XDATDLY=00b)

mode.

2P+1

2P+7

FSX ext

FSX int

¶

0

6

Enable time, FSX high to DX driven

FSX ext

FSX int

M10

Only applies to first bit transmitted

when in Data Delay 0 (XDATDLY=00b)

mode

2P

FSX ext

P+6

†

‡

§

Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are

also inverted.

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

T=CLKRX period = (1 + CLKGDV) * P

C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even

D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even

See the TMS320VC5501/5502/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592) for

a description of the DX enable (DXENA) and data delay features of the McBSP.

¶

146

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

M1, M11

M2, M12

M13

M3, M12

M4

CLKR

FSR (Int)

FSR (Ext)

M4

M14

M15

M17

M16

M18

DR

Bit (n–1)

(n–2)

(n–3)

(n–2)

(n–4)

(n–3)

(RDATDLY=00b)

M17

M18

DR

Bit (n–1)

(RDATDLY=01b)

M17

M18

DR

Bit (n–1)

(n–2)

(RDATDLY=10b)

Figure 6–32. McBSP Receive Timings

M1, M11

M2, M12

M13

M14

M3, M12

M5

CLKX

M5

FSX (Int)

M19

M20

FSX (Ext)

DX

M9

M7

M10

Bit 0

Bit (n–1)

(n–2)

(n–3)

(n–2)

(n–4)

(n–3)

(XDATDLY=00b)

M7

M8

DX

Bit 1

Bit 0

Bit (n–1)

(XDATDLY=01b)

M7

M6

M8

DX

Bit 1

Bit 0

Bit 2

Bit (n–1)

(n–2)

(XDATDLY=10b)

NOTE A: This figure does not include first or last frames. For first frame, no data will be present before frame synchronization.

For last frame, no data will be present after frame synchronization.

Figure 6–33. McBSP Transmit Timings

147

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

6.16.2 McBSP General-Purpose I/O Timings

Table 6–35 and Table 6–36 assume testing over recommended operating conditions (see Figure 6–34).

Table 6–35. McBSP General-Purpose I/O Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

4

MAX

†

M22

M23

t

Setup time, MGPIOx input mode before CLKOUT high

ns

su(MGPIO–COH)

†

Hold time, MGPIOx input mode after CLKOUT high

0

h(COH–MGPIO)

†

MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input.

Table 6–36. McBSP General-Purpose I/O Switching Characteristics

VC5502-200

VC5502-300

NO.

M21

PARAMETER

UNIT

MIN

MAX

‡

t

Delay time, CLKOUT high to MGPIOx output mode

0

4

ns

d(COH–MGPIO)

‡

MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.

M22

CLKOUT

M21

M23

MGPIO

†

Input Mode

MGPIO

‡

Output Mode

†

‡

MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input.

MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.

Figure 6–34. McBSP General-Purpose I/O Timings

148

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

6.16.3 McBSP as SPI Master or Slave Timings

Table 6–37 to Table 6–44 assume testing over recommended operating conditions (see Figure 6–35 through

Figure 6–38).

†‡

Table 6–37. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)

VC5502-200

VC5502-300

UNIT

NO.

MASTER

SLAVE

MIN MAX

MIN

11

MAX

M30

M31

M32

M33

t

Setup time, DR valid before CLKX low

Hold time, DR valid after CLKX low

Setup time, FSX low before CLKX high

Cycle time, CLKX

0 – 5P

8 + 6P

10

ns

su(DRV–CKXL)

h(CKXL–DRV)

su(FXL–CKXH)

c(CKX)

1

2P

16P

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

†‡§

Table 6–38. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)

VC5502-200

VC5502-300

NO.

UNIT

PARAMETER

MASTER

SLAVE

MIN MAX

MIN

T – 1

C – 1

–2

MAX

¶

M24

M25

M26

t

Delay time, CLKX low to FSX low

T + 1

C + 1

2

ns

d(CKXL–FXL)

d(FXL–CKXH)

d(CKXH–DXV)

#

Delay time, FSX low to CLKX high

Delay time, CLKX high to DX valid

3P + 4 4P+ 18

Disable time, DX high impedance following last data bit from

CLKX low

M27

t

C – 2

C +10

ns

dis(CKXL–DXHZ)

Disable time, DX high impedance following last data bit from

FSX high

M28

M29

t

2P+ 4 4P + 10

2P + 4 4P + 10

ns

dis(FXH–DXHZ)

Delay time, FSX low to DX valid

d(FXL–DXV)

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

§

¶

T

= BCLKX period = (1 + CLKGDV) * 2P

C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

#

149

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

M32

M25

M33

LSB

MSB

CLKX

M26

M24

FSX

M28

M27

M29

DX

DR

Bit 0

Bit (n–1)

(n–2)

M31

(n–2)

(n–3)

(n–4)

M30

Bit 0

Bit (n–1)

Figure 6–35. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

150

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

†‡

Table 6–39. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)

VC5502-200

VC5502-300

NO.

UNIT

MASTER

SLAVE

MIN MAX

MIN

11

MAX

M39

M40

M41

M42

t

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

Setup time, FSX low before CLKX high

Cycle time, CLKX

0 – 5P

8 +6P

10

ns

su(DRV–CKXH)

h(CKXH–DRV)

su(FXL–CKXH)

c(CKX)

1

2P

16P

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

†‡§

Table 6–40. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MASTER

MIN

SLAVE

MIN

MAX

C + 1

T + 1

2

MAX

¶

M34

M35

M36

t

Delay time, CLKX low to FSX low

C – 1

T – 1

ns

d(CKXL–FXL)

d(FXL–CKXH)

d(CKXL–DXV)

#

Delay time, FSX low to CLKX high

Delay time, CLKX low to DX valid

–2

3P + 4

2P – 4

4P + 18

4P + 10

Disable time, DX high impedance following last

data bit from CLKX low

M37

t

–2

10

ns

dis(CKXL–DXHZ)

M38

t

Delay time, FSX low to DX valid

D – 2

D +10

d(FXL–DXV)

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

§

¶

T

= CLKX period = (1 + CLKGDV) * P

C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even

D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

#

M41

M42

LSB

MSB

CLKX

FSX

M35

M34

M36

M38

M37

DX

DR

Bit 0

Bit (n–1)

(n–2)

M40

(n–2)

(n–3)

(n–4)

M39

Bit (n–1)

Figure 6–36. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

151

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

†‡

Table 6–41. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)

VC5502-200

VC5502-300

NO.

UNIT

MASTER

SLAVE

MIN MAX

MIN

11

MAX

M49

M50

M51

M52

t

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

Setup time, FSX low before CLKX low

Cycle time, CLKX

2 – 6P

6 + 6P

10

ns

su(DRV–CKXH)

h(CKXH–DRV)

su(FXL–CKXL)

c(CKX)

1

2P

16P

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

†‡§

Table 6–42. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MASTER

MIN

SLAVE

MIN

MAX

T + 1

D + 1

2

MAX

¶

M43

M44

M45

t

Delay time, CLKX high to FSX low

T – 1

ns

d(CKXH–FXL)

d(FXL–CKXL)

d(CKXL–DXV)

#

Delay time, FSX low to CLKX low

Delay time, CLKX low to DX valid

D – 1

–2

3P + 4

4P + 18

Disable time, DX high impedance following last

data bit from CLKX high

M46

t

D – 2

D +10

ns

dis(CKXH–DXHZ)

Disable time, DX high impedance following last

data bit from FSX high

M47

M48

t

2P + 4

4P + 10

ns

dis(FXH–DXHZ)

Delay time, FSX low to DX valid

2P – 4

d(FXL–DXV)

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

§

¶

T

= CLKX period = (1 + CLKGDV) * P

D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

#

152

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

M51

M44

LSB

MSB

M52

CLKX

FSX

M45

M43

M47

M46

M48

DX

DR

Bit 0

Bit (n–1)

(n–2)

(n–3)

(n–4)

M49

M50

(n–2)

Bit 0

Bit (n–1)

Figure 6–37. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

153

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

†‡

Table 6–43. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)

VC5502-200

VC5502-300

NO.

UNIT

MASTER

SLAVE

MIN

11

MAX

M58

M59

M60

M61

t

Setup time, DR valid before CLKX low

Hold time, DR valid after CLKX low

Setup time, FSX low before CLKX low

Cycle time, CLKX

0 – 5P

8 + 6P

10

ns

su(DRV–CKXL)

h(CKXL–DRV)

su(FXL–CKXL)

c(CKX)

1

2P

16P

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

†‡§

Table 6–44. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MASTER

MIN

SLAVE

MIN

MAX

D + 1

T + 1

2

MAX

¶

M53

M54

M55

t

Delay time, CLKX high to FSX low

D – 1

T – 1

ns

d(CKXH–FXL)

d(FXL–CKXL)

d(CKXH–DXV)

#

Delay time, FSX low to CLKX low

Delay time, CLKX high to DX valid

–2

3P + 4

2P – 4

4P + 18

4P + 10

Disable time, DX high impedance following last

data bit from CLKX high

M56

t

–2

10

ns

dis(CKXH–DXHZ)

M57

t

Delay time, FSX low to DX valid

C – 2

C +10

d(FXL–DXV)

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

§

¶

T

= CLKX period = (1 + CLKGDV) * P

C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even

D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

#

154

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

M60

M54

LSB

MSB

M61

CLKX

FSX

M53

M55

M57

M56

DX

DR

Bit 0

Bit (n–1)

(n–2)

(n–3)

(n–4)

M58

M59

(n–2)

(n–3)

Figure 6–38. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

155

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

6.17 Host-Port Interface Timings

6.17.1 HPI Read and Write Timings

Table 6–45 and Table 6–46 assume testing over recommended operating conditions (see Figure 6–39

through Figure 6–44).

†‡

Table 6–45. HPI Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

5

MAX

H9

t

Setup time, HPI.HAS low before DS falling edge

Hold time, HPI.HAS low after DS falling edge

Setup time, HAD valid before HPI.HAS falling edge

Hold time, HAD valid after HPI.HAS falling edge

Pulse duration, DS low

ns

su(HASL–HDSL)

h(HDSL–HASL)

su(HBV–HASL)

h(HASL–HBV)

w(HDSL)

H10

H11

H12

H13

H14

H15

H16

H17

H18

2

5

10

2P

5

Pulse duration, DS high

w(HDSH)

Setup time, HAD valid before DS falling edge

Hold time, HAD valid after DS falling edge

Setup time, HD valid before DS rising edge

Hold time, HD valid after DS rising edge

su(HBV–HDSL)

h(HDSL–HBV)

su(HDV–HDSH)W

h(HDSH–HDV)W

5

10

0

†

‡

P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

DS refers to logical OR of HCS, HDS1, and HDS2. HD refers to HPI Data Bus. HDS refers to HDS1 or HDS2. HAD refers to HCNTL0, HCNTL1,

and HR/W.

‡§

Table 6–46. HPI Switching Characteristics

VC5502-200

VC5502-300

NO.

H1

PARAMETER

UNIT

MIN

MAX

Case 1. Read Data present in FIFO.

3

20

ns

Case 2. FIFO is Empty; No other

DMA/MEM activity is present.

n*2H+20

20

Delay time, DS low to HD

valid

t

d(HDSL–HDV)

Case 3. HPIC or Unobstructed HPIA

Read.

3

ns

H2

H3

H4

H5

t

Delay time, DS rising edge to HD valid, read

Delay time, DS low to HD driven

0

3

10

20

12

ns

d(HDSH–HDV)R

d(HDSL–HDD)

Delay time, DS low to HRDY low

Delay time, DS high to HRDY low

d(HDSL–HRDYL)

d(HDSH–HRDYL)

Case 1. FIFO is Empty; No other

DMA/MEM activity present.

n*2H+20

ns

Delay time, DS high to HRDY

high

H6

t

d(HDSH–HRDYH)

Case 2. FIFO is Full; No other DMA/MEM

activity is present.

H7

H8

t

Valid time, HD valid after HRDY high

7

3

ns

v(HRDYH–HDV)

Delay time, CLKOUT rising edge to HINT change

d(COH–HINT)

‡

§

DS refers to logical OR of HCS, HDS1, and HDS2. HD refers to HPI Data Bus. HDS refers to HDS1 or HDS2. HAD refers to HCNTL0, HCNTL1,

and HR/W.

H is half the CPU clock cycle.

156

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

Read

H13

Write

HCS

HDSx

H14

H13

H15

H16

HR/W

HPI.HA[15:0]

Valid

H1

H2

H3

HPI.HD[15:0]

(Read)

Read data

H18

H17

HPI.HD[15:0]

(Write)

Write data

H6

H7

H4

H5

HRDY

Figure 6–39. Non-Multiplexed Read/Write Timings

157

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

HCS

H9

H10

HPI.HAS

HDSx

H11

H13

H12

H14

HR/W

HCNTL[1:0]

H1

H2

HPI.HD[7:0]

HRDY

Data 1

Data 2

H5

H3

H4

H6

H7

HPI.HBIL

Figure 6–40. Multiplexed Read Timings Using HPI.HAS

158

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

HCS

HDSx

H15

H14

H13

H16

HR/W

HCNTL[1:0]

HPI.HD[7:0]

H2

H1

Data 1

Data 2

H3

H4

H5

HRDY

H7

H6

HPI.HBIL

Figure 6–41. Multiplexed Read Timings With HPI.HAS Held High

159

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

HCS

H11

H10

HPI.HAS

HR/W

H9

H12

HCNTL[1:0]

HDSx

H14

H17

Data 1

H13

Data 2

HPI.HD[7:0]

HRDY

H18

H5

H6

HPI.HBIL

Figure 6–42. Multiplexed Write Timings Using HPI.HAS

160

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

HCS

H14

HDSx

HR/W

H15

H13

H16

HCNTL[1:0]

HPI.HD[7:0]

H17

Data 1

Data 2

H18

HRDY

H5

H6

HPI.HBIL

Figure 6–43. Multiplexed Write Timings With HPI.HAS Held High

CLKOUT

H8

HINT

Figure 6–44. HINT Timings

161

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

6.17.2 HPI General-Purpose I/O Timings

Table 6–47 and Table 6–48 assume testing over recommended operating conditions (see Figure 6–45).

†

Table 6–47. HPI General-Purpose I/O Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

3

MAX

‡

H23

H24

H25

H26

H27

H28

H29

H30

t

Setup time, HAGPIO input mode before CLKOUT high

ns

su(HAGPIO–COH)

‡

Hold time, HAGPIO input mode after CLKOUT high

Setup time, HDNMGPIO input mode before CLKOUT high

0

h(COH–HAGPIO)

§

3.1

0

su(HDNMGPIO–COH)

h(COH–HDNMGPIO)

su(HDMGPIO–COH)

h(COH–HDMGPIO)

su(HCGPIO–COH)

h(COH–HCGPIO)

§

Hold time, HDNMGPIO input mode after CLKOUT high

¶

Setup time, HDMGPIO input mode before CLKOUT high

3.1

¶

Hold time, HDMGPIO input mode after CLKOUT high

0

3.5

0

#

Setup time, HCGPIO input mode before CLKOUT high

#

Hold time, HCGPIO input mode after CLKOUT high

†

‡

§

¶

#

In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

HAGPIO refers to HPI.HA[15:0] configured as general-purpose input.

HDNMGPIO refers to HPI.HD[15:0] configured as general-purpose input during non-multiplexed operation of the HPI.

HDMGPIO refers to HPI.HD[7:0] configured as general-purpose input during multiplexed operation of the HPI.

HCGPIO refers to HPI.HAS (multiplexed mode only), HPI.HBIL (multiplexed mode only), HCNTL0, HCNTL1, HCS, HR/W, HDS1, HDS2, HRDY,

and HINT configured as general-purpose input.

†

Table 6–48. HPI General-Purpose I/O Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

||

H19

H20

H21

H22

t

Delay time, CLKOUT high to HAGPIO output mode

6.6

ns

d(COH–HAGPIO)

d(COH–HDNMGPIO)

d(COH–HDMGPIO)

d(COH–HCGPIO)

k

8.6

7.8

5.0

Delay time, CLKOUT high to HDNMGPIO output mode

h

Delay time, CLKOUT high to HDMGPIO output mode

◊

Delay time, CLKOUT high to HCGPIO output mode

†

||

In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

HAGPIO refers to HPI.HA[15:0] configured as general-purpose output.

kHDNMGPIO refers to HPI.HD[15:0] configured as general-purpose output during non-multiplexed operation of the HPI.

hHDMGPIO refers to HPI.HD[7:0] configured as general-purpose output during multiplexed operation of the HPI.

◊ HCGPIO refers to HPI.HAS (multiplexed mode only), HPI.HBIL (multiplexed mode only), HCNTL0, HCNTL1, HCS, HR/W, HDS1, HDS2, HRDY,

and HINT configured as general-purpose output.

162

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

CLKOUT

H23

H25

H27

H29

H24

H26

H28

H30

HAGPIO

Input Mode

H19

HAGPIO

Output Mode

HDNMGPIO

Input Mode

H20

HDNMGPIO

Output Mode

HDMGPIO

Input Mode

H21

HDMGPIO

Output Mode

HCGPIO

Input Mode

H22

HCGPIO

Output Mode

Figure 6–45. HPI General-Purpose I/O Timings

163

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

6.17.3 HPI.HAS Interrupt Timings

Table 6–49 assumes testing over recommended operating conditions (see Figure 6–46).

†

Table 6–49. HPI.HAS Interrupt Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

2.8

0

MAX

‡

H31

H32

H33

t

Setup time, HPI.HAS low before CLKOUT rising edge

ns

su(HASL–COH)

h(COH–HASL)

w(HASL)

‡

Hold time, HPI.HAS low after CLKOUT rising edge

‡

§

P

Pulse width, HPI.HAS low

†

‡

In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT.

An interrupt can be triggered by setting the HPI.HAS signal high or low, depending on the setting of the HAS bit in the General-Purpose I/O

Interrupt Control Register 2 (HPGPIOINT2). Refer to the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature

number SPRU620) for more information on the interrupt capability of the HPI.HAS signal.

P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

§

CLKOUT

H31

H32

H33

HPI.HAS

Figure 6–46. HPI.HAS Interrupt Timings

164

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

2

6.18 Inter-Integrated Circuit (I C) Timings

Table 6–50 and Table 6–51 assume testing over recommended operating conditions (see Figure 6–47 and

Figure 6–48).

2

Table 6–50. I C Signals (SDA and SCL) Timing Requirements

VC5502-200

VC5502-300

STANDARD

MODE

FAST

MODE

NO.

UNIT

MIN

MAX

MIN

MAX

IC1

IC2

t

Cycle time, SCL

10

2.5

µs

c(SCL)

Setup time, SCL high before SDA low for a repeated START

condition

4.7

4

0.6

su(SCLH-SDAL)

Hold time, SCL low after SDA low for a START and a repeated

START condition

IC3

t

µs

h(SCLL-SDAL)

IC4

IC5

t

Pulse duration, SCL low

4.7

4

1.3

0.6

µs

ns

µs

ns

µs

ns

pF

w(SCLL)

t

Pulse duration, SCL high

w(SCLH)

su(SDA-SCLH)

h(SDA-SCLL)

w(SDAH)

r(SDA)

†

IC6

t

Setup time, SDA valid before SCL high

250

100

0

2

‡

0

‡

§

0.9

IC7

t

Hold time, SDA valid after SCL low For I C bus devices

IC8

t

Pulseduration,SDAhighbetweenSTOPandSTARTconditions

Rise time, SDA

4.7

1.3

¶

IC9

t

1000 20 + 0.1C

300 20 + 0.1C

300

b

IC10

IC11

IC12

IC13

IC14

IC15

t

Rise time, SCL

r(SCL)

t

Fall time, SDA

f(SDA)

t

Fall time, SCL

f(SCL)

t

Setup time, SCL high before SDA high (for STOP condition)

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

4.0

0.6

0

su(SCLH-SDAH)

t

50

w(SP)

¶

C

400

b

†

‡

2

A Fast-mode I C-bus device can be used in a Standard-mode I C-bus system, but the requirement t

≥ 250 ns must then be met.

su(SDA–SCLH)

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period

oftheSCLsignal,itmustoutputthenextdatabittotheSDAlinet max+t

I C-Bus Specification) before the SCL line is released.

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V

region of the falling edge of SCL.

=1000+250=1250ns(accordingtotheStandard-mode

su(SDA–SCLH)

r

2

of the SCL signal) to bridge the undefined

IHmin

§

¶

The maximum t

has only to be met if the device does not stretch the LOW period [t

] of the SCL signal.

h(SDA–SCLL)

w(SCLL)

C

= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

b

IC11

IC9

SDA

IC6

IC8

IC14

IC13

IC4

IC5

IC10

SCL

IC1

IC3

IC12

IC3

IC2

IC7

Stop

Start

Repeated

Start

Stop

2

Figure 6–47. I C Receive Timings

2

I C Bus is a trademark of Koninklijke Philips Electronics N.V.

165

April 2001 – Revised June 2003

SPRS166D

Electrical Specifications

2

Table 6–51. I C Signals (SDA and SCL) Switching Characteristics

VC5502-200

VC5502-300

STANDARD

MODE

FAST

MODE

NO.

PARAMETER

UNIT

MIN MAX

MIN

MAX

IC16

IC17

t

Cycle time, SCL

10

2.5

µs

c(SCL)

Delay time, SCL high to SDA low for a repeated START

condition

4.7

0.6

d(SCLH-SDAL)

Delay time, SDA low to SCL low for a START and a repeated

START condition

IC18

t

4

µs

d(SDAL-SCLL)

IC19

IC20

IC21

IC22

IC23

IC24

IC25

IC26

IC27

IC28

IC29

t

Pulse duration, SCL low

4.7

4

1.3

0.6

100

0

µs

ns

µs

ns

µs

pF

w(SCLL)

Pulse duration, SCL high

w(SCLH)

d(SDA-SCLH)

v(SCLL-SDAV)

w(SDAH)

r(SDA)

Delay time, SDA valid to SCL high

250

0

2

Valid time, SDA valid after SCL low For I C bus devices

0.9

Pulseduration,SDAhighbetweenSTOPandSTARTconditions

4.7

1.3

†

Rise time, SDA

1000 20 + 0.1C

300 20 + 0.1C

300

b

Rise time, SCL

r(SCL)

Fall time, SDA

f(SDA)

Fall time, SCL

f(SCL)

Delay time, SCL high to SDA high for a STOP condition

4

0.6

d(SCLH-SDAH)

2

C

Capacitance for each I C pin

10

p

†

C

= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

b

IC26

IC24

SDA

IC21

IC23

IC19

IC28

IC20

IC27

IC25

SCL

IC16

IC18

IC17

IC22

Stop

Start

Repeated

Start

Stop

2

Figure 6–48. I C Transmit Timings

166

SPRS166D

April 2001 – Revised June 2003

Electrical Specifications

6.19 Universal Asynchronous Receiver/Transmitter (UART) Timings

Table 6–52 to Table 6–53 assume testing over recommended operating conditions (see Figure 6–49).

Table 6–52. UART Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

†

U4

U5

t

Pulse width, receive data bit

Pulse width, receive start bit

0.99U

1.01U

ns

w(UDB)R

†

w(USB)R

†

U = UART baud time = 1/programmed baud rate

Table 6–53. UART Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

U1

U2

U3

f

t

Maximum programmable baud rate

Pulse width, transmit data bit

Pulse width, transmit start bit

5

MHz

ns

baud

†

U – 2

U + 2

w(UDB)X

w(USB)X

†

U – 2

ns

†

U = UART baud time = 1/programmed baud rate

U3

Data Bits

Start

Bit

UART.TX

U2

Data Bits

Start

Bit

UART.RX

U4

U5

Figure 6–49. UART Timings

167

April 2001 – Revised June 2003

SPRS166D

Mechanical Data

7

Mechanical Data

7.1 Ball Grid Array Mechanical Data

GGW (S–PBGA–N176)

PLASTIC BALL GRID ARRAY

15,10

SQ

12,80 TYP

14,90

0,80

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11 13 15 17

10 12 14 16

A1 Corner

2

4

6

8

Bottom View

0,95

0,85

1,40 MAX

Seating Plane

0,12

0,55

0,45

0,08

0,45

0,35

4145255–2/D 08/02

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice

C. MicroStar BGAt configuration.

Figure 7–1. TMS320VC5502 176-Ball MicroStar BGA Plastic Ball Grid Array Package

MicroStar BGA is a trademark of Texas Instruments.

168

SPRS166D

April 2001 – Revised June 2003

Mechanical Data

7.2 Low-Profile Quad Flatpack Mechanical Data

PGF (S-PQFP-G176)

PLASTIC QUAD FLATPACK

132

89

133

88

0,27

0,17

M

0,08

0,50

0,13 NOM

176

45

1

44

Gage Plane

21,50 SQ

24,20

SQ

23,80

0,25

0,05 MIN

26,20

SQ

0°–ā7°

25,80

0,75

0,45

1,45

1,35

Seating Plane

0,08

1,60 MAX

4040134/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

Figure 7–2. TMS320VC5502 176-Pin Low-Profile Quad Flatpack

169

April 2001 – Revised June 2003

SPRS166D


型号：	TMS320VC5502-300
厂家：	ETC
描述：	Fixed-Point Digital Signal Processor 定点数字信号处理器\n 数字信号处理器
文件：	总191页 (文件大小：2350K)
中文：	中文翻译
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