STC62WV256TC [ETC]
VERY LOW POWER/VOLTAGE CMOS SRAM; 非常低的功率/电压CMOS SRAM
| 型号： | STC62WV256TC |
| 厂家： | 
ETC |
| 描述： | VERY LOW POWER/VOLTAGE CMOS SRAM |
| 文件： | 总10页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
32K X 8 bit
STC
STC62WV256
DESCRIPTION
FEATURES
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
The STC62WV256 is a high performance , very low power CMOS
Static Random Access Memory organized as 32,768 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.01uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable (OE) and three-state output drivers.
The STC62WV256 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.01uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc=3.0V
The STC62WV256 is available in the DICE form, JEDEC standard 28pin
330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and 8mm x
13.4mm TSOP (normal type).
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
(ICC, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
PKG
TYPE
(ICCSB1, Max)
Vcc=
3.0V
Vcc=
5.0V
Vcc=
3.0V
Vcc=
5.0V
Vcc=
3.0V
STC62WV256SC
STC62WV256TC
STC62WV256PC
STC62WV256JC
STC62WV256DC
STC62WV256SI
STC62WV256TI
STC62WV256PI
STC62WV256JI
STC62WV256DI
SOP-28
TSOP-28
PDIP-28
SOJ-28
0 O C to +70 O
C
2.4V ~ 5.5V
2.4V ~ 5.5V
70
70
1uA
0.2uA
0.4uA
35mA
20mA
25mA
DICE
SOP-28
TSOP-28
PDIP-28
SOJ-28
-40 O C to +85 O
C
2uA
40mA
DICE
BLOCK DIAGRAM
PIN CONFIGURATIONS
A14
A12
A7
1
28
27
26
25
24
23
VCC
WE
A13
A8
2
A5
A6
3
A6
4
A7
Address
A5
5
A9
Memory Array
A12
A14
A13
18
62WV256SC
62WV256SI
512
Row
Decoder
A4
6
A11
OE
Input
A3
7
62WV256PC 22
512 x 512
62WV256PI
62WV256JC
62WV256JI
Buffer
A2
8
21
A10
CE
A8
A9
A1
9
20
A0
10
11
12
13
14
19
18
17
16
15
DQ7
DQ6
DQ5
DQ4
DQ3
A11
DQ0
DQ1
DQ2
GND
512
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
8
Column I/O
Buffer
Write Driver
Sense Amp
8
8
Data
64
A10
CE
Output
Buffer
1
2
3
4
5
6
7
8
28
OE
A11
A9
27
26
25
24
23
22
21
20
19
18
17
16
15
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
Column Decoder
12
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
CE
WE
OE
STC62WV256TC
STC62WV256TI
Control
Address Input Buffer
9
10
11
12
13
14
Vdd
Gnd
A4 A3 A2 A1 A0 A10
A1
A2
STC International Limited. reserves the right to modify document contents without notice.
Revision 2.3
Jan. 2004
R0201-STC62WV256
1
STC
STC62WV256
PIN DESCRIPTIONS
Name
Function
A0-A14 Address Input
These 15 address inputs select one of the 32768 x 8-bit words in the RAM
CE Chip Enable Input
WE Write Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. If chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0 – DQ7 Data Input/Output
Ports
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
Not selected
Output Disabled
Read
WE
X
CE
H
L
OE
X
I/O OPERATION
High Z
Vcc CURRENT
ICCSB, ICCSB1
H
H
High Z
ICC
ICC
ICC
H
L
L
DOUT
Write
L
L
X
DIN
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
SYMBOL
VTERM
TBIAS
TSTG
PARAMETER
Terminal Voltage with
Respect to GND
RATING
-0.5 to
Vcc+0.5
UNITS
AMBIENT
TEMPERATURE
0 O C to +70O
RANGE
Vcc
V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
Commercial
Industrial
C
2.4V ~ 5.5V
2.4V ~ 5.5V
-40 O C to +85O
C
PT
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
IOUT
SYMBOL
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
IN
MAX.
UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
CIN
pF
V
=0V
6
CDQ
pF
VI/O=0V
8
1. This parameter is guaranteed and not 100% tested.
Revision 2.3
Jan. 2004
R0201-STC62WV256
2
STC
STC62WV256
DC ELECTRICAL CHARACTERISTICS ( TA =0oC to + 70oC)
PARAMETER
PARAMETER
TEST CONDITIONS
MIN. TYP. (1) MAX.
UNITS
NAME
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Guaranteed Input Low
Voltage(2)
IL
V
-0.5
--
0.8
V
Guaranteed Input High
2.0
2.2
IH
V
--
--
Vcc+0.2
1
V
Voltage(2)
IL
IN
I
Input Leakage Current
Output Leakage Current
Vcc = Max, V = 0V to Vcc
--
uA
Vcc = Max, CE = VIH, or OE = VIH
,
LO
I
--
--
1
uA
I/O
V
= 0V to Vcc
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
OL
OL
V
Output Low Voltage
Output High Voltage
Vcc = Max, I = 2mA
Vcc = Min, I = -1mA
--
--
--
0.4
--
V
V
OH
OH
V
2.4
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
--
--
--
--
--
--
--
--
20
35
1
Operating Power Supply
Current
(3)
CC
IL
DQ
I
CE = V , I = 0mA, F = Fmax
mA
mA
uA
--
ICCSB
Standby Current-TTL
CE = VIH, IDQ = 0mA
--
2
0.01
0.4
0.2
1.0
CE ≧ Vcc-0.2V,
CCSB1
I
Standby Current-CMOS
V
IN ≧ Vcc - 0.2V or VIN ≦ 0.2V
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
CE ≧ Vcc - 0.2V
MIN. TYP. (1) MAX.
UNITS
VDR
Vcc for Data Retention
1.5
--
--
V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
CE ≧ Vcc -0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
ICCDR
Data Retention Current
--
0
0.01
0.20
uA
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
TRC
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
Vcc
CE
t
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
Revision 2.3
R0201-STC62WV256
3
Jan.
2004
STC
STC62WV256
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Vcc/0V
1V/ns
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
AC TEST LOADS AND WAVEFORMS
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Ω
Ω
1269
1269
3.3V
3.3V
OUTPUT
OUTPUT
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
100PF
5PF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
Ω
Ω
1404
1404
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
667
Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA =0oC to + 70oC and Vcc=3.0V)
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
CYCLE TIME : 70ns
MIN. TYP. MAX.
DESCRIPTION
Read Cycle Time
UNIT
t
t
70
--
--
--
--
--
--
--
--
--
--
70
70
50
--
ns
ns
ns
ns
ns
ns
ns
ns
AVAX
RC
t
t
Address Access Time
AVQV
AA
t
t
Chip Select Access Time
--
ELQV
ACS
t
t
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
--
GLQV
OE
t
t
10
10
--
ELQX
CLZ
t
t
--
GLQX
OLZ
t
t
35
30
EHQZ
CHZ
t
t
--
GHQZ
OHZ
t
t
AXOX
OH
Data Hold from Address Change
10
--
--
ns
Revision 2.3
Jan. 2004
R0201-STC62WV256
4
STC
STC62WV256
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE
t
ACS
(5)
CHZ
t
(5)
t
CLZ
D OUT
READ CYCLE3 (1,4)
t
RC
ADDRESS
OE
t
AA
t
OH
t
OE
t
OLZ
CE
(5)
t
ACS
t
OHZ
(1,5)
t
CHZ
(5)
CLZ
t
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL
.
.
±
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.3
Jan. 2004
R0201-STC62WV256
5
STC
STC62WV256
AC ELECTRICAL CHARACTERISTICS ( TA =0oC to + 70oC and Vcc=3.0V)
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
CYCLE TIME : 70ns
DESCRIPTION
Write Cycle Time
UNIT
MIN.
70
70
0
TYP. MAX.
t
t
AVAX
WC
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
E1LWH
CW
Chip Select to End of Write
Address Set up Time
t
t
AVWL
AS
--
t
t
AVWH
AW
Address Valid to End of Write
Write Pulse Width
70
50
0
--
t
t
WLWH
WP
--
t
t
WHAX
WR
Write Recovery Time
(CE , WE)
--
t
t
WLOZ
WHZ
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End ot Write to Output Active
--
30
--
t
t
DVWH
DW
40
0
t
t
WHDX
DH
--
t
t
GHOZ
OHZ
--
30
--
t
t
WHQX
OW
5
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(11)
CW
t
(5)
CE
t
AW
t
WP
(2)
t
AS
WE
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 2.3
Jan. 2004
R0201-STC62WV256
6
STC
STC62WV256
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
CE
(11)
CW
t
(5)
t
AW
t
WP
(2)
WE
t
AS
(4,10)
t
t
OW
(7)
(8)
t
WHZ
D OUT
t
DW
(8,9)
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
Revision 2.3
Jan. 2004
R0201-STC62WV256
7
STC
STC62WV256
ORDERING INFORMATION
STC62WV256
X X Z Y Y
SPEED
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
J: SOJ
S: SOP
P: PDIP
T: TSOP (8mm x 13.4mm)
D: DICE
Note:
STC (STC International Limited.) assumes no responsibility for the application or use of any product or circuit described herein. STC does not authorize its products
for use as critical components in any application in which the failure of the STC product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
0.020 ± 0.005X45°
θ
b
WITH PLATING
c
c1
BASE METAL
b1
SOP - 28
Revision 2.3
Jan. 2004
R0201-STC62WV256
8
STC
STC62WV256
PACKAGE DIMENSIONS (continued)
UNIT
SYMBOL
INCH
MM
12°(2x)
12°(2x)
A
0.0433±0.004
1.10±0.10
A1 0.0045±0.0026 0.115±0.065
HD
A2 0.039±0.002
1.00±0.05
0.22±0.05
0.20±0.03
0.10 ~ 0.21
0.10 ~ 0.16
11.80±0.10
8.00±0.10
0.55±0.10
13.40±0.20
c
L
b
0.009±0.002
0.008±0.001
0.004 ~ 0.008
0.004 ~ 0.006
0.465±0.004
0.315±0.004
0.022±0.004
1
28
b1
c
c1
D
E
y
Seating Plane
e
14
15
12° (2X)
HD 0.528±0.008
+0.008
+0.20
L
0.0197
- 0.004
0.50
"A"
- 0.10
D
L1
y
0.0315±0.004
0.004 Max.
0°~ 8°
0.80±0.10
0.1 Max.
0°~ 8°
GAUGE PLANE
A
A
0
0
SEATING PLANE
14
15
12 (2X)
L
L1
"A" DATAIL VIEW
b
WITH PLATING
1
28
c
c1
BASE METAL
b1
SECTION A-A
TSOP - 28
PDIP - 28
Revision 2.3
Jan. 2004
R0201-STC62WV256
9
STC
STC62WV256
PACKAGE DIMENSIONS (continued)
SOJ - 28
Revision 2.3
R0201-STC62WV256
10
Jan.
2004
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