SSM01N60 [ETC]

N-CHANNEL ENHANCEMENT-MODE POWER MOSFET; N沟道增强模式功率MOSFET
SSM01N60
型号: SSM01N60
厂家: ETC    ETC
描述:

N-CHANNEL ENHANCEMENT-MODE POWER MOSFET
N沟道增强模式功率MOSFET

文件: 总6页 (文件大小:106K)
中文:  中文翻译
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SSM01N60H,J  
N-CHANNEL ENHANCEMENT-MODE POWER MOSFET  
Dynamic dv/dt rating  
Repetitive-avalanche rated  
Fast switching  
BVDSS  
RDS(ON)  
ID  
600V  
8  
D
S
1.6A  
G
Simple drive requirement  
Description  
G
The SSM01N60H is supplied in the industry-standard TO-252  
D
S
TO-252 (H)  
TO-251 (J)  
package, which is widely preferred for commercial and industrial  
surface mount applications, and is well suited for AC/DC converters. The  
through-hole version (SSM01N60J) is available for low-footprint applications.  
G
D
S
Absolute Maximum Ratings  
Symbol  
Parameter  
Rating  
600  
Units  
V
VDS  
VGS  
Drain-Source Voltage  
Gate-Source Voltage  
± 30  
V
A
ID @ TC=25°C  
ID @ TC=100°C  
IDM  
Continuous Drain Current, VGS @ 10V  
Continuous Drain Current, VGS @ 10V  
Pulsed Drain Current1  
1.6  
1
A
6
39  
A
PD @ TC=25°C  
Total Power Dissipation  
W
Linear Derating Factor  
Single Pulse Avalanche Energy2  
0.31  
W/°C  
mJ  
A
EAS  
IAR  
13  
Avalanche Current  
1.6  
EAR  
TSTG  
TJ  
Repetitive Avalanche Energy  
Storage Temperature Range  
Operating Junction Temperature Range  
0.5  
mJ  
°C  
°C  
-55 to 150  
-55 to 150  
Thermal Data  
Symbol  
Parameter  
Thermal Resistance Junction-case  
Thermal Resistance Junction-ambient  
Value  
3.2  
Unit  
Rthj-c  
Max.  
Max.  
°C/W  
°C/W  
Rthj-a  
110  
Rev.2.02 4/06/2004  
www.SiliconStandard.com  
1 of 6  
SSM01N60H,J  
Electrical Characteristics @ Tj=25oC(unless otherwise specified)  
Symbol  
BVDSS  
Parameter  
Test Conditions  
VGS=0V, ID=250uA  
Min. Typ. Max. Units  
Drain-Source Breakdown Voltage  
600  
-
-
V
V/°C  
BV /∆Τ  
j
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA  
-
-
0.6  
7.2  
-
DSS  
RDS(ON)  
Static Drain-Source On-Resistance  
Gate Threshold Voltage  
VGS=10V, ID=0.8A  
8
VGS(th)  
VDS=VGS, ID=250uA  
VDS=10V, ID=0.8A  
VDS=600V, VGS=0V  
VDS=480V, VGS=0V  
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8  
-
4
-
V
gfs  
Forward Transconductance  
Drain-Source Leakage Current (T=25oC)  
S
IDSS  
uA  
uA  
nA  
nC  
nC  
nC  
ns  
ns  
ns  
ns  
pF  
pF  
pF  
10  
j
Drain-Source Leakage Current (T=150oC)  
j
-
100  
IGSS  
Qg  
± 30V  
±100  
Gate-Source Leakage  
Total Gate Charge3  
Gate-Source Charge  
Gate-Drain ("Miller") Charge  
Turn-on Delay Time3  
Rise Time  
VGS=  
-
ID=1.6A  
7.7  
1.5  
2.6  
8
-
-
-
-
-
-
-
-
Qgs  
Qgd  
td(on)  
tr  
VDS=480V  
VGS=10V  
VDD=300V  
ID=1.6A  
5
td(off)  
tf  
Turn-off Delay Time  
Fall Time  
RG=10,VGS=10V  
RD=187.5Ω  
VGS=0V  
14  
7
Ciss  
Coss  
Crss  
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
286  
25  
6
VDS=25V  
-
-
f=1.0MHz  
Source-Drain Diode  
Symbol  
Parameter  
Test Conditions  
Min. Typ. Max. Units  
A
A
V
IS  
Continuous Source Current ( Body Diode )  
Pulsed Source Current ( Body Diode )1  
Forward On Voltage3  
VD=VG=0V , VS=1.5V  
-
-
-
-
1.6  
6
ISM  
VSD  
Tj=25°C, IS=1.6A, VGS=0V  
-
-
1.5  
Notes:  
1.Pulse width limited by safe operating area.  
2.Starting Tj=25oC , VDD=50V , L=10mH , RG=25, IAS=1.6A.  
3.Pulse width <300us , duty cycle <2%.  
Rev.2.02 4/06/2004  
www.SiliconStandard.com  
2 of 6  
SSM01N60H,J  
1.5  
T C =25 o C  
T C =150 o C  
V
V
G =10V  
G =6.0V  
V G =10V  
V G =6.0V  
0.8  
0.6  
0.4  
0.2  
0
V G =5.5V  
V
G =5.5V  
1
V G =5.0V  
V
V
G =5.0V  
G =4.5V  
0.5  
V
G =4.5V  
0
0
5
10  
15  
20  
0
5
10  
15  
20  
V DS , Drain-to-Source Voltage (V)  
V DS , Drain-to-Source Voltage (V)  
Fig 1. Typical Output Characteristics  
Fig 2. Typical Output Characteristics  
2.8  
1.2  
1.1  
1
I D =0.8A  
V G =10V  
2.4  
2
1.6  
1.2  
0.8  
0.4  
0
0.9  
0.8  
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
T j , Junction Temperature ( o C)  
T j , Junction Temperature ( o C )  
Fig 3. Normalized BVDSS  
Temperature  
vs. Junction  
Fig 4. Normalized On-Resistance  
vs. Junction Temperature  
Rev.2.02 4/06/2004  
www.SiliconStandard.com  
3 of 6  
SSM01N60H,J  
2
1.6  
1.2  
0.8  
0.4  
0
50  
40  
30  
20  
10  
0
25  
50  
75  
100  
125  
150  
0
50  
100  
150  
T c , Case Temperature ( o C )  
Tc, Case Temperature ( o C )  
Fig 5. Maximum Drain Current vs.  
Case Temperature  
Fig 6. Typical Power Dissipation  
1
10  
DUTY=0.5  
10us  
1
0.2  
0.1  
100us  
1ms  
0.1  
0.05  
0.02  
PDM  
10ms  
0.1  
t
T
0.01  
SINGLE PULSE  
100ms  
Duty factor = t/T  
Peak Tj = PDM x Rthjc + TC  
T c =25 o C  
Single Pulse  
0.01  
0.01  
1
10  
100  
1000  
10000  
0.00001  
0.0001  
0.001  
0.01  
0.1  
1
10  
V DS (V)  
t , Pulse Width (s)  
Fig 7. Maximum Safe Operating Area  
Fig 8. Effective Transient Thermal Impedance  
Rev.2.02 4/06/2004  
www.SiliconStandard.com  
4 of 6  
SSM01N60H,J  
f=1.0MHz  
1000  
100  
10  
16  
14  
12  
10  
8
I D =1.6A  
V DS =480V  
Ciss  
Coss  
Crss  
6
4
2
0
1
0
1
2
3
4
5
6
7
8
9
10  
1
9
17  
25  
V DS (V)  
Q G , Total Gate Charge (nC)  
Fig 9. Gate Charge Characteristics  
Fig 10. Typical Capacitance Characteristics  
5
4
3
2
1
0
100  
10  
1
T j = 150 o C  
T j = 25 o C  
0.1  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1.6  
-50  
0
50  
100  
150  
T j , Junction Temperature ( o C )  
V SD (V)  
Fig 11. Forward Characteristic of  
Reverse Diode  
Fig 12. Gate Threshold Voltage vs.  
Junction Temperature  
Rev.2.02 4/06/2004  
www.SiliconStandard.com  
5 of 6  
SSM01N60H,J  
VDS  
RD  
90%  
VDS  
TO THE  
OSCILLOSCOPE  
D
S
0.5x RATED VDS  
RG  
G
10%  
VGS  
+
-
10V  
VGS  
td(off)  
td(on) tr  
tf  
Fig 13. Switching Time Circuit  
Fig 14. Switching Time Waveform  
VG  
VDS  
QG  
TO THE  
OSCILLOSCOPE  
D
S
10V  
0.8 x RATED VDS  
QGD  
QGS  
G
VGS  
+
1~ 3 mA  
IG  
-
ID  
Q
Charge  
Fig 15. Gate Charge Circuit  
Fig 16. Gate Charge Waveform  
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no  
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no  
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its  
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including  
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to  
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of  
Silicon Standard Corporation or any third parties.  
Rev.2.02 4/06/2004  
www.SiliconStandard.com  
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