SSI34P3402A [ETC]
Analog Miscellaneous ; 模拟杂项\n
| 型号： | SSI34P3402A |
| 厂家： | 
ETC |
| 描述： | Analog Miscellaneous
|
| 文件： | 总3页 (文件大小：45K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSI 34P3402A
8 to 53 Mbit/s Read Channel
w/Adaptive Threshold Qualifier
June 1998
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CMOS RDIO signal output for servo timing
support
DESCRIPTION
The SSI 34P3402A device is a high performance
BiCMOS single chip read channel IC that contains all
the functions necessary to implement an adaptive
threshold read channel. Functional blocks include a
pulse detector with adaptive threshold qualifier,
programmable filter, and data synchronizer. Raw data
rates from 8 to 53 Mbit/s can be programmed by digital
commands.
Internal LOW-Z and fast decay timing for rapid
transient recovery and AGC acquisition
Fast decay mode is self-timed for optimal AGC
recovery
0.5 ns maximum pulse pairing with sine wave
input
Independent qualification thresholds for data
and timing extraction
The SSI 34P3402A allows complete flexibility in read
channel configuration. All critical parameters can be
programmed by a microprocessor via a bi-directional
serial port and a bank of internal registers.
PROGRAMMABLE FILTER
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Programmable cutoff frequency of 2 to 16 MHz
Programmable boost of 0 to 13 dB
The SSI 34P3402A utilizes an advanced BiCMOS
process technology along with advanced circuit design
techniques which result in a high performance device
with low power consumption.
Programmable group delay equalization (up to
38% change in group delay)
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Matched normal and differentiated outputs
±10% Fc accuracy from 10 to 16 MHz
Less than 1% total harmonic distortion
FEATURES
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8 to 53 Mbit/s raw data rate
DATA SYNCHRONIZER
Bi-directional serial port for access to internal
registers
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Fully integrated data synchronizer
- No external delay lines or active
components required
- No external active PLL components
required
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Low power operation (<TBD mW typical @
RRC = 53 MHz and 5 V)
Programmable power management (sleep
mode <1 mW )
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Selectable PLL input from adaptive threshold
qualifier or traditional window qualifier
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Power supply range (4.5 to 5.5 V)
Selectable data synchronizer input from
adaptive threshold qualifier or traditional
window qualifier
Small footprint 48-Pin TQFP package
PULSE DETECTOR
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Temperature compensated, exponential
control AGC
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Fast PLL acquisition phase lock loop
- Zero phase restart technique
- Programmable phase detector gain gear
shift
Fast attack/decay modes for rapid AGC
recovery
Programmable decode window symmetry
- Window shift control ±15% of decode
window
- Includes delayed read data and VCO
reference monitor points
Dual rate charge pump for fast transient
recovery
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Low drift AGC hold circuitry
Programmable AGC fixed gain mode
Adaptive threshold qualifier for data extraction
Traditional window qualifier for timing
extraction
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Programmable pulse qualification threshold
level
06/04/98 -rev.
1
SSI 34P3402A
8 to 53 Mbit/s Read Channel
w/Adaptive Threshold Qualifier
BLOCK DIAGRAM A
RDIO
LEVEL2
CP
CN
LEVEL
DP
DN
FNN
FNP
FDN
FDP
RP
RX
PWRON
2
SSI 34P3402A
8 to 53 Mbit/s Read Channel
w/Adaptive Threshold Qualifier
BLOCK DIAGRAM B
DACOUT
VPG
VNG
VND
VNC
VNB
VNA
VPD
VPC
VPB
VPA
DFLN
DFLP
MTP4 (TP)
MTP1 (TP)
MTP2 (TP)
MTP3 (TP)
SDATA
SCLK
SDEN
RR
FREF
3
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