SR202A [ETC]
The SR202A is a timing controller for small panel TFT-LCD. It provides horizontal and vertical control timing to TFT-LCD source and gate drivers.; 该SR202A为小面板的TFT-LCD的定时控制器。它提供了横向和纵向的控制定时，以TFT-LCD的源极和栅极驱动器。
| 型号： | SR202A |
| 厂家： | 
ETC |
| 描述： | The SR202A is a timing controller for small panel TFT-LCD. It provides horizontal and vertical control timing to TFT-LCD source and gate drivers. |
| 文件： | 总15页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SR202A
1. General Description
The SR202A is a timing controller for small panel TFT-LCD. It provides horizontal and
vertical control timing to TFT-LCD source and gate drivers. Built-in vertical synchronization
detection circuit generates vertical synchronization signal internally without the extra components.
Built-in phase lock loop sub-function with external VCO and low pass filter produces system
clock which synchronizes input composite synchronization signal. SR202A also provides 8
different zoom in/zoom out display modes for 2 different display resolutions.
2. Features
z
z
z
z
z
z
z
z
z
z
z
Programmable resolution mode.
Master clock frequency: 30 MHz max.
Built-in vertical sync. detection to omit the external sync. separator.
Supply voltage: +5.0V or +3.3V.
Shift clock signals for the source driver (3-φ Clock).
Line inversion driving scheme.
Support NTSC/PAL TV system.
Provides control timings for source and gate drivers.
Provides flip and mirror scan control.
Built-in zoom in/zoom out display mode selection.
48 pins LQFP.
3. Block Diagram
Rev.2.1
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SR202A
4. Pin Assignment
41
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SR202A
5. Pin Description
Pin no.
Symbol
NVCOM
HZ_OUT
OEH
I/O
O
O
O
O
I
Description
Inverter output of VCOM
1
2
3
4
5
6
7
Zoom in control signal
Source driver output enable control signal
Gate driver output enable control signal
Test pin
OEV
MODE (1)
FIELD
GND
O
Odd/even field output
Ground
Simultaneous/sequential sampling control setting
of LCD.
8
MOD_OUT
O
I
Resolution mode setting pin
9
RES
RES=”H”, 1440 resolution mode
RES=”L”, 1200 resolution mode
Start pulse for gate driver.
10
STVD
O
O
(1) STVD is “HiZ”, when UDC=”L”
(2) STVD is ”Output”, when UDC=”H”
Start pulse for gate driver.
11
12
13
STVU
VCC
(1) STVU is ”HiZ”, when UDC=”H”
(2) STVU is ”Output”, when UDC=”L”
Power for internal circuit
Start pulse for source driver.
STHL
O
O
(1) STHL is ”HiZ”, when LRC=”H”
(2) STHL is ”Output”, when LRC=”L”
Start pulse for source driver.
14
STHR
(1) STHR is ”HiZ”, when LRC=”L”
(2) STHR is ”Output”, when LRC=”H”
Phase detector output
15
16
17
18
19
20
21
22
23
24
25
PDO
CKV
O
O
O
O
O
I
Shift clock for gate driver
CPH1
Shift clock φ1 for source driver
Shift clock φ2 for source driver
Shift clock φ3 for source driver
Zoom in/out modes setting pin
Zoom in/out modes setting pin
Zoom in/out modes setting pin
Ground
CPH2
CPH3
ZX1(2)
ZX2(2)
ZX3(2)
I
I
GND
VCC2
Power for I/O pad
VCO_CLK_OUT
O
I
Inverted system clock signal output
System clock input. It connects with external VCO
and low pass filter circuits to generate system clock which
synchronizes input composite synchronization signal
26
VCO_CLK_IN
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SR202A
27
28
29
DVS
DS
O
O
I
Negative polarity vertical synchronization signal output
Dual scan mode vertical duplication control signal
Active low global reset signal input
HWRESETZ
Negative polarity vertical synchronization signal input
which is from the external synchronization separator
circuits
30
VS
I
Pin no.
31
Symbol
UDC_INV
Z1_MODE (1)
DS_EN (1)
I/O
O
I
Description
UDC inverted signal output
Test pin
32
33
I
Test pin
Horizontal synchronization signal output with
negative polarity
34
DHS
O
I
Composite synchronization signal input with
positive polarity
35
36
CVS
GND
Ground
Up / Down scan setting pin
37
38
39
UDC
VZ_MODE (1)
LRC
I
I
I
(1) Normal scan, when UDC=”L”
(2) Reverse scan, when UDC=”H”
Test pin
Left / Right scan setting pin
(1) Normal scan, LRC=”L”
(2) Reverse scan, LRC=”H”
LRC inverted signal output
40
41
LRC_INV
VS_DET
O
O
Test pin
VS detection setting pin
42
EXT_VS
I
(1) VS is from external detection , when EXT_VS=”H”
(2) VS is from internal detection , when EXT_VS=”L”
Video signal input format setting pin; pull-up for
normal operation.
43
44
NPC
I/O
O
Toggling signal for common electrode generation
circuits
VCOM
NPC I/O setting pin
45
EXT_NPC
I
(1) NPC is “Output”, when EXT_NPC =”L”
(2) NPC is “Input”, when EXT_NPC =”H”
Reference signal output for phase lock loop operation
Reference signal input for phase lock loop operation
Power for internal circuit
46
47
48
HS_REF_FBO
HS_REF_FBI
VCC
O
I
Note:(1) These test pins should be set “OPEN” for normal operation.
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SR202A
(2) Zoom in/out display mode setting:
Display
Display Characteristics
ZX1 ZX2
ZX3
Remark
Mode
(4:3 aspect-ratio input signal)
Input signals are
displayed on full
screen.(To display
4:3 signal on 16:9
screen)
Full
H
L
H
L
H
H
L
L
H
Central 176 lines
of input signals are
displayed on full
screen. (Vertically
extension, zoom
factor =4/3).
Zoom1
H
H
H
Central 176 lines
of input signals are
displayed on full
screen. (Vertically
extension and
zoom-
Wide1
different horizontal
timing scaling).
Input signal(4:3)
are displayed on
center 75%
Normal
screen.(4:3
aspect-ratio).
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SR202A
Display
Mode
Display Characteristics
ZX1 ZX2
ZX3
Remark
(4:3 aspect-ratio input signal)
Lower 205 lines of
input signals are
displayed on full
screen.(Zoom
factor=8/7,
Zoom2
H
L
H
L
H
H
L
L
L
vertically offset
extension).
Input signals are
displayed on full
screen.(Different
horizontal timing
scaling).
Wide
L
L
L
Lower 205 lines of
input signal are
displayed on full
screen. (Vertically
extension and
Zoom-
Wide2
different horizontal
timing scaling).
Center 205 lines of
input signal are
displayed on full
screen. (Vertically
extension, zoom
factor=8/7).
Zoom3
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Rev.2.1
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SR202A
6. DC Characteristics
6.1 Absolute maximum ratings:
Parameter
Power supply
Symbol
Rating
-0.3 to 6.0
Units
V
VCC,VCC2
VIN
Input voltage
-0.3 to VCC2 +0.3
-0.3 to VCC2 +0.3
-40 to 125
V
Output voltage
Storage temperature
VOUT
V
TSTG
ºC
6.2 Recommended operating conditions:
Parameter
Power supply
Symbol
Min.
3.0
Typ.
Max. Units
VCC,VCC2
VIN
5.0
5.5
VCC
85
V
V
Input voltage
0
-
-
Operating temperature
TOPR
TBD
ºC
6.3 Electrical Characteristics:
Parameter
Symbol
Condition
No pull-up or
pull-down
Min
Typ
Max
Units
Input low current
IIL
-1
-
-
-
1
1
μA
No pull-up or
pull-down
Input high current
IIH
-1
μA
μA
Tri-state leakage
current
IOZ
-10
10
Input capacitance
Output capacitance
Logic input low voltage
Schmitt input low
voltage
CIN
COUT
VIL
-
3
-
3
-
-
pF
pF
V
6
CMOS
CMOS
CMOS
CMOS
-
0.3VCC2
(1)
VSI
-
TBD
-
-
-
-
V
V
V
Logic input high voltage
Schmitt input high
voltage
VIH
0.7VCC2
-
(1)
VSIH
TBD
(2)
Output low voltage
Output high voltage
Input pull up/down
resistance
VOL
IOL=4mA
IOH=-4mA
VIL= 0V or
VIH= VCC2
-
-
-
0.2VCC2
-
V
V
(3)
VOH
0.8VCC2
RI
40
-
100
KΩ
Note:(1) HWRESETZ, VCO_CLK_IN, VS, CVS, HS_REF_FBI.
(2)VOL is 0.3VCC2 when VCC2 = 3V
(3)VOH is 0.7VCC2 when VCC2 = 3V
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SR202A
6.4 Current consumption for 5 Volts operating:
Parameter
Symbol
Conditions
Min.
-
Typ.
14
Max.
21.5
Units
mA
Vcc=+5.0V,
Full Chip Current
Consumption
f
OSC = 23.2 MHz
IIN
Vcc=+5.0V,
-
16
23.5
mA
fOSC = 29.1 MHz
7. AC Characteristics
7.1 1440 mode
a. Input signal characteristics
PARAMETER
VCO_CLK_IN period
CVS period
Symbol
tOSC
tH
Min.
Typ.
Max.
Unit.
ns
33
34
35
65.5
5.4
700
300
5
61.5
63.5
us
CVS pulse width
tCVS
tCr
4
-
4.7
us
CVS rising time
-
ns
CVS falling time
tCf
-
-
ns
VS pulse width
tVS
1
-
3
tH
VS rising time
tVr
-
700
1.5
-
ns
VS falling time
tVf
-
-
us
Horizontal lines per NTSC
-
262.5
312.5
line
line
field
PAL
-
-
b. Output signal characteristics
PARAMETER
Rising time
Symbol
Min.
Typ.
Max.
10
Unit.
ns
tr
tf
-
-
-
-
Falling time
10
ns
Clock high and low level pulse
width
tCPH
-
40
-
3
-
60
-
tOSC
%
Clock pulse duty
tCWH
50
tC12, tC23
tC31
tSUH
tSTH
tHS
,
3-φ clock phase difference
t
CPH/3
ns
STH setup time
-
-
-
-
-
-
-
-
-
-
-
tCPH/2
1
-
-
-
-
-
-
-
-
-
-
-
tCPH
tCPH
tCPH
tCPH
tCPH
tCPH
tCPH
tH
STH pulse width
DHS pulse width
46
12
80
46
37
1
OEH pulse width
tOEH
tDIS1
tOEV
tCKV
tCP
Sample & hold disable time
OEV pulse width
CKV pulse width
HS_REF_FBO period
HS_REF_FBO pulse duty
DHS-OEH time
tWCP
t1
1/2
34
28
tH
tCPH
tCPH
DHS-CKV time
t2
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SR202A
DHS-OEV time
t3
-
-
-
-
-
-
8
-
-
-
-
-
-
tCPH
tCPH
tCPH
tH
DHS-HS_REF_FBO time
STV setup time
t4
32
16
1
tSUV
tSTV
tVS1
tVS1
STV pulse width
NTSC
PAL
19
27
tH
DVS-STV time
tH
Note:(1) For all of the logic signals.
(2) CPH1~3.
(3) When ZX1, ZX2, ZX3 are all Hi.
7.2 1200 mode
a. Input signal characteristics
PARAMETER
VCO_CLK_IN period
CVS period
Symbol
tOSC
tH
Min.
Typ.
Max.
43
Unit.
ns
40.3
41.6
61.5
63.5
65.5
5.4
700
300
5
us
CVS pulse width
tCVS
tCr
4
-
4.7
us
CVS rising time
-
ns
CVS falling time
tCf
-
-
ns
VS pulse width
tVS
1
-
3
tH
VS rising time
tVr
-
700
1.5
-
ns
VS falling time
tVf
-
-
us
Horizontal lines per NTSC
-
262.5
312.5
line
line
field
PAL
-
-
b. Output signal characteristics
PARAMETER
Rising time(1)
Falling time(1)
Symbol
Min.
Typ.
Max.
10
Unit.
ns
tr
tf
-
-
-
-
10
ns
Clock high and low level
pulse width(2)
tCPH
-
3
-
tOSC
Clock pulse duty
tCWH
tC12, tC23, tC31
tSUH
40
-
50
tCPH/3
tCPH/2
1
60
-
%
3-φlock phase difference
STH setup time
ns
-
-
tCPH
tCPH
tCPH
tCPH
tCPH
tCPH
tCPH
tH
STH pulse width
tSTH
-
-
DHS pulse width
tHS
-
36
-
OEH pulse width
tOEH
-
9
-
Sample & hold disable time
OEV pulse width
tDIS1
-
61
-
tOEV
-
40
-
CKV pulse width
tCKV
-
50
-
HS_REF_FBO period
HS_REF_FBO pulse WIDTH
tCP
-
1
-
tWCP
-
1/2
-
tH
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SR202A
DHS-OEH time
t1
t2
-
-
-
-
-
-
-
-
27
14
12
26
8
-
-
-
-
-
-
-
-
tCPH
tCPH
tCPH
tCPH
tCPH
tH
DHS-CKV time
DHS-OEV time
t3
DHS-HS_REF_FBO time
STV setup time
t4
tSUV
tSTV
tVS1
tVS1
STV pulse width
1
NTSC
PAL
19
27
tH
DVS-STV
tH
Note:(1) For all of the logic signals.
(2) CPH1~3.
(3) When ZX1, ZX2, ZX3 are all Hi.
7.3 Zoom in/out display mode
7.3.1 1440 mode
Zoom mode
Horizontal Display Start
Vertical Display Start
ZX1
L
ZX2
L
ZX3
L
12.94us
12.98us
33H
H
L
L
45H
L
H
L
12.98us
19H
H
H
L
12.94us
45H
L
L
H
8.83us
19H
48H
H
L
H
12.98us
L
H
H
12.94us
48H
H
H
H
12.94us
19H
From falling edge of
DHS to rising edge of
STHL(R)
From falling edge of
DVS to rising edge of
STVU(D)
Remark
7.3.2 1200 mode
Zoom mode
Horizontal Display Start
Vertical Display Start
ZX1
L
ZX2
L
ZX3
L
12.59us
12.65us
33H
H
L
L
45H
L
H
L
12.65us
19H
H
H
L
12.59us
45H
L
L
H
8.65us
19H
48H
H
L
H
12.65us
L
H
H
12.59us
48H
H
H
H
12.59us
19H
From falling edge of
DHS to rising edge of
STHL(R)
From falling edge of
DVS to rising edge of
STVU(D)
Remark
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SR202A
8. Waveform
8.1 VCO_CLK, STHL(R) and CPH1~3 timing waveform
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Rev.2.1
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SR202A
8.2 CVS and horizontal control timing waveform
8.3 CVS and vertical shift clock timing waveform
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Rev.2.1
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SR202A
8.4 CVS and vertical control timing waveform
0755-89812241
Rev.2.1
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SR202A
9 Application circuit
V5
R92
39K
CSY
R90
15K
R91
10K
C53
105
R88
15K
U8
6
5
4
U4
4053
Q4
15K
R89
180K
R154
1
2
E1
C1
A1015
VSY
B1 B2
3
C2 E2
XN4501
C63
R153
150K
102
R156
10K
3K R155
VG
VB
VB1
R75
P11
P10
P1
R63 R66
R60
10K
R73
100
JP5
R70 R71 R72
100 100 100
R76
R77
R78
10K
10K
1
100
P2
2
3
4
5
6
7
8
U3
-10V
+15V
P2
100
P1
12
V5
25
26
27
28
29
30
31
32
33
34
35
36
VCO-OUT
VCO-IN
DVS
+5V
P9
VB1
JP3
UDI
P4
11
10
9
B
G
R
STVU
R35
100
1
2
3
4
9
VCOM
104
10
11
12
13
14
15
STVD
RES
R59
10K
C40
10K
R74
RL1
P3
P5
P10
P11
P6
DS
8
P3
RESET
MOD-OUT
100
VG1
VR1
VSY
7
R145
16
17
18
19
20
21
22
23
24
VS
GND
FIELD
MODE
OEV
5
6
R93
100
100
R96
P7
P8
6
SR202A
U/D1
R/L1
UDC-INV
5
100
R143
ZI-MODE
DS-EN
7
VR
VG
VB
V5
4
P4
P5
R94
100
GND
CSY
8
R?1K
R971K
R108
HSY
V5
3
100
100
SYS
OEH
DHS
CVS
9
25
26
R142
2
HZ
HF
GND
HZ-OUT
NVCOM
10
11
1
P26/0.5
GND
R100
2.7K
100
R144
12
13
GND
CSC8806A
V5
V5
10K
RV15
14
U/D
V5
P14/2
R104
R105
R/L
R?
1K
C60
R103
100
100
100
100p
1K
R107
C47
10U
R102
10K
2.7K
R106
C54
V5
560P
82K
-10V
M2X355
DH2
R101
1M
10K VCOM
RV13
C57
RV14
10K
C41
10U
R98
104
R95
24K
47P
C66
102
C65
P14
104
C42
3
4
L15
1.5UH
R161
U7
-
O
JRC3414A
1M
U10
2
1
G
NJM2107F
R86
22K
R87
10K
R160
100
5
R163
2.7K
V5
+
V
R162
100
-10V
R157
68K
R151
20K
R148
20K
T
S
C67
104
V5
4.7K
R158
4.7K
R159
C64
104
R152
10K
10k
R150
10K
D
F
R149
0755-89812241
Rev.2.1
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SR202A
10. Packages Outline(Unit:μm)：
10.1:LQFP48
0755-89812241
Rev.2.1
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