SPIF223A [ETC]
ATA to Serial ATA Bi-direction Bridge; ATA串行ATA双向桥接
| 型号： | SPIF223A |
| 厂家： | 
ETC |
| 描述： | ATA to Serial ATA Bi-direction Bridge |
| 文件： | 总21页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPIF223A
ATA to Serial ATA Bi-direction Bridge
MAY 29, 2006
Version 1.2
Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be
accurate and reliable. However, Sunplus Technology makes no warranty for any errors which may appear in this document. Contact Sunplus Technology to
obtain the latest version of device specifications before placing your order. No responsibility is assumed by Sunplus Technology for any infringement of patent
or other rights of third parties which may result from its use. In addition, Sunplus products are not authorized for use as critical components in life support
devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the
user, without the express written approval of Sunplus.
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SPIF223A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3
2. FEATURES.................................................................................................................................................................................................. 3
3. REFERENCES ............................................................................................................................................................................................ 3
4. FUNCTIONAL BLOCK DIAGRAM.............................................................................................................................................................. 4
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
5.1. PIN DESCRIPTIONS ................................................................................................................................................................................ 5
5.2. PIN LIST ................................................................................................................................................................................................ 5
5.3. ATA INTERFACE REVERSE...................................................................................................................................................................... 6
5.4. SPIF223A PIN DIAGRAM........................................................................................................................................................................ 9
6. ELECTRONICAL SPECIFICATION .......................................................................................................................................................... 10
6.1. POWER REQUIREMENT ........................................................................................................................................................................ 10
6.2. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 10
6.3. RECOMMENDED/TYPICAL OPERATING CONDITIONS ............................................................................................................................... 10
6.4. DC CHARACTERISTICS..........................................................................................................................................................................11
6.5. SPIF223A UART AND SPI INTERFACE SELECT:.....................................................................................................................................11
6.6. SPIF223A DEVICE MODE OR HOST :.....................................................................................................................................................11
6.7. SPIF223AATA DEVICE MODE SELECT:.................................................................................................................................................11
6.8. SPIF223A SERIAL ATA BUS TRI-STATE FEATURE:...................................................................................................................................11
6.9. SPIF223AATA BUS TRI-STATE FEATURE: ..............................................................................................................................................11
7. COMMAND LIST ....................................................................................................................................................................................... 12
7.1. ATA COMMAND LIST:............................................................................................................................................................................ 12
7.2. ATAPI COMMAND LIST: ........................................................................................................................................................................ 15
8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 17
8.1. PACKAGE INFORMATION ....................................................................................................................................................................... 17
8.1.1. 64 pin TQFP............................................................................................................................................................................ 17
8.2. ORDERING INFORMATION ..................................................................................................................................................................... 19
8.3. STORAGE CONDITION AND PERIOD FOR PACKAGE................................................................................................................................. 19
8.4. RECOMMENDED SMT TEMPERATURE PROFILE...................................................................................................................................... 19
9. DISCLAIMER............................................................................................................................................................................................. 20
10.REVISION HISTORY ................................................................................................................................................................................. 21
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SPIF223A
A SINGLE-CHIP SOLUTION
FOR AN ATA TO SERIAL ATA DEVICE BRIDGE
1. GENERAL DESCRIPTION
The Sunplus SPIF223A is a single-chip solution for bi-direction of
ATA to Serial ATA and Serial ATA to ATA device bridge. It could
accept ATA commands through both ATA and SATA interface ,
decode the commands and converts them into ATA commands to
the device. Response from the device through the serial ATA or
ATA bus are deciphered, processed and converted to ATA protocol
and sent to the host. The SPIF223A supports the Serial ATA
generation 1 transfer rate of 1.5Gb/s (150MB/s) on the serial side
and is compatible with Ultra133 on the ATA side.
Serial ATA Features
⎯ Integrated Serial ATA Link and PHY logic.
⎯ Compliant with Serial ATA 1.0A specifications.
⎯ Support Serial ATA Generation 1 transfer rate of 1.5Gb/s.
⎯ Support Spread Spectrum in receiver.
⎯ Support Serial ATA power saving mode : Partial, and
Slumber..
ATA Features
⎯ Compliant with ATA specifications.
⎯ Compatible with Ultra ATA 133.
⎯ Support PIO mode 0,1,2,3,4,5,6 MDMA0,1,2 and Ultra DMA
mode 0,1,2,3,4,5,6
2. FEATURES
⎯ Support UDMA data transfer rates of up to 133MBps.
⎯ Support ATA device master/slave/Chip select emulation.
⎯ Support ATA bus timing control.
Overall Features
⎯ Bi-Direction of ATA to Serial ATA bridge chip.
⎯ Compliant with ATA specification.
⎯ Compliant with SATA 1.0a specification.
⎯ Compatible with Ultra ATA 133.
⎯ Support ATA and ATAPI device like HDD and ODD, Tape..
⎯ Support ATA interface reverse feature.
⎯ Fabricated in 0.16um CMOS process with 1.8 volt core and
3.3 volt I/Os.
⎯ Available in a 64-pin TQFP package with e-Pad1.
⎯ PHY isolation debug mode
3. REFERENCES
For more details about Serial ATA and ATA technology please refer
to the following industry specifications:
⎯ Full scan for high production test coverage
⎯ Build-in 8051 uP to control data flow.
⎯ Support UART, SPI, I2C bus.
Serial ATA
/
High Speed Serialized ATA Attachment
specification, Revision 1.0A.
⎯ Support ATA bus skew-rate programming by UART/SPI
interface.2
Http://www.T13.org/ ATA/ATAPI specifications.
1
For e-Pad of SPIF223A, please always connect e-Pad to the
ground of application board.
2
For ATA bus timing control, please check with agent to get more
information for UART/SPI interface.
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SPIF223A
4. FUNCTIONAL BLOCK DIAGRAM
TestControlSignals
SDAT SCLK
Test
Controller
XTALI
XTALO
PLL
clock
I2C
TX+/-
RX+/-
ATA
IF
FIFO
Registers
ATA
Transport
LINK
PHY
SDIF
8051
Power Management
UART
RAM ROM
UAI UAO
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SPIF223A
5.SIGNAL DESCRIPTIONS
5.1. Pin Descriptions
Table 5-1: Pin Types
Pin Type
Pin Description
I/O
Bi-directional Pin
I
O
Input Pin with LVTTL Thresholds
Output Pin
I-Sch
P
Input Pin with Schmitt Trigger
Pull-Down resistor is internal
Tri-state Output Pin
T
5.2. Pin List
Table 5-2: SPIF223A Pin Listing
Pin#
1
Pin Name
B_IDE_DD[13]
Type
I/O
I/O
I/O
PWR
I/O
I/O
I/O
GND
PWR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Description
ATA Interface Data Bus bit 13
ATA Interface Data Bus bit 2
ATA Interface Data Bus bit 12
3.3V Digital I/O Power
2
B_IDE_DD[2]
B_IDE_DD[12]
D3V3_IO
3
4
5
B_IDE_DD[3]
B_IDE_DD[11]
B_IDE_DD[4]
DVSS
ATA Interface Data Bus bit 3
ATA Interface Data Bus bit 11
ATA Interface Data Bus bit 4
Ground for the Digital Core and I/O
1.8V Digital CORE Power
ATA Interface Data Bus bit 10
ATA Interface Data Bus bit 5
ATA Interface Data Bus bit 9
ATA Interface Data Bus bit 6
ATA Interface Data Bus bit 8
ATA Interface Data Bus bit 7
ATA Interface Reset.
6
7
8
9
D1V8_CO
B_IDE_DD[10]
B_IDE_DD[5]
B_IDE_DD[9]
B_IDE_DD[6]
B_IDE_DD[8]
B_IDE_DD[7]
I_IDE_RST_B
RESET_B
D3V3_IO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
ASIC Reset input
PWR
I
3.3V Digital I/O Power
IDE_ORD_INV
CFG0
ATA Cable Signal Ordering Inverse
Device/Host mode enable
I
UART_SPI_SEL
XTALI/CLKI
XTALO
I
UART/SPI interface enable 0: UART enable, 1: SPI enable
Crystal oscillator input or external clock input
Crystal oscillator output
I
O
VDDA
PWR
GND
I
1.8V Analog Power
GNDA
Analog Ground
REXT
External reference resistor input
Differential receive +ve
RXP
I
RXN
I
Differential receive –ve
VDDA
PWR
GND
O
1.8V Analog Power
GNDA
Analog Ground
TXN
Differential transmit –ve
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Pin#
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Pin Name
Type
Description
TXP
O
Differential transmit +ve
Jumper 0
I_IDE_JUMP0
IDE_DASP
IDE_JUMP1
TEST_CFG
UAO_SPI_OUT
SPI_En_B
SPL_CLK
I
I/O
I
ATA Interface Device Active or Slave(Device 1) Present
Jumper 1
I
Test Configuration bit 0
UART/SPI data output
SPI Enable
O
O
O
SPI Clock
UAI_SPI_IN
D1V8_CO
DVSS
I
UART/SPI data in
PWR
GND
I/O
PWR
I/O
1.8V Digital CORE Power
Ground for the Digital Core and I/O
I2C Serial Data
I2C_SDA
D3V3_IO
3.3V Digital I/O Power
I2C Serial Clock
I2C_SCLK
IDE_PDIAG
IDE_CS1_B
IDE_CS0_B
IDE_DA2
I/O
I/O
ATA Interface Passed Diagnostics ATA Interface Cable Assembly Type Identifier
ATA Interface Chip Select 1
I/O
I/O
I/O
ATA Interface Chip Select 0
ATA Interface Device Address bit 2
IDE_DA0
ATA Interface Device Address bit 0
IDE_DA1
I/O
I/O
I/O
I/O
I/O
ATA Interface Device Address bit 1
IDE_CSEL
IDE_INTRQ
IDE_DMACK_B
IDE_IORDY
ATA Interface Cable Select
ATA Interface Interrupt Request
ATA Interface DMA Acknowledge
ATA Interface I/O Ready ATA Interface DMA Read during Ultra DMA data-out
bursts ATA Interface Data Strobe during Ultra DMA data-in bursts
3.3V Digital I/O Power
56
57
58
D3V3_IO
DVSS
PWR
GND
I/O
Ground for the Digital Core and I/O
IDE_DIOR_B
ATA Interface I/O Read ATA Interface DMA Ready during Ultra DMA data-in bursts
ATA Interface Data Strobe during Ultra DMA data-out bursts
ATA Interface I/O Write ATA Interface Stop during Ultra DMA data bursts
ATA Interface DMA Request
59
60
61
62
63
64
IDE_DIOW_B
IDE_DMARQ
IDE_DD[15]
IDE_DD[0]
I/O
I/O
I/O
I/O
I/O
I/O
ATA Interface Data Bus bit 15
ATA Interface Data Bus bit 0
IDE_DD[14]
IDE_DD[1]
ATA Interface Data Bus bit 14
ATA Interface Data Bus bit 1
5.3. ATA Interface Reverse
IDE_ORD_INV = 0
Pin Name
IDE_ORD_INV = 1
Pin Name
Pin#
1
IDE_DD[13]
IDE_DD[0]
2
IDE_DD[2]
IDE_DD[12]
D3V3_IO
IDE_DD[15]
3
IDE_DMARQ
4
5
IDE_DD[3]
IDE_DD[11]
IDE_DIOW_
IDE_DIOR_
6
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IDE_ORD_INV = 0
Pin Name
IDE_ORD_INV = 1
Pin Name
Pin#
7
B_IDE_DD[4]
IDE_DMACK_
8
DVSS
9
D1V8_CO
IDE_DD[10]
IDE_DD[5]
IDE_DD[9]
IDE_DD[6]
IDE_DD[8]
IDE_DD[7]
I_IDE_RST_B
RESET_B
D3V3_IO
IDE_ORD_INV
CFG0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
IDE_INTRQ
IDE_CSEL
IDE_DA1
IDE_DA0
IDE_DA2
IDE_CS0_
IDE_CS1_
UART_SPI_SEL
XTALI/CLKI
XTALO
VDDA
GNDA
REXT
RXP
RXN
VDDA
GNDA
TXN
TXP
I_IDE_JUMP0
IDE_DASP
IDE_JUMP1
TEST_CFG
UAO_SPI_OUT
SPI_En_B
SPL_CLK
UAI_SPI_IN
D1V8_CO
DVSS
I2C_SDA
D3V3_IO
I2C_SCLK
IDE_PDIAG
IDE_CS1_B
IDE_CS0_B
IDE_DA2
IDE_DA0
IDE_DA1
IDE_RESET_
IDE_DD[7]
IDE_DD[8]
IDE_DD[6]
IDE_DD[9]
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IDE_ORD_INV = 0
Pin Name
IDE_ORD_INV = 1
Pin Name
Pin#
52
53
54
55
56
57
58
59
60
61
62
63
64
IDE_CSEL
IDE_DD[5]
IDE_DD[10]
IDE_DD[4]
IDE_INTRQ
IDE_DMACK_B
IDE_IORDY
D3V3_IO
DVSS
IDE_DIOR_B
IDE_DIOW_B
IDE_DMARQ
IDE_DD[15]
IDE_DD[0]
IDE_DD[14]
IDE_DD[1]
IDE_DD[11]
IDE_DD[3]
IDE_DD[12]
IDE_DD[2]
IDE_DD[13]
IDE_DD[1]
IDE_DD[14]
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5.4. SPIF223A Pin Diagram
U1
49
IDE_DA2/DD8
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
IDE_DA0/DD6
IDE_DA1/DD9
IDE_CSEL/DD5
IDE_INTRQ/DD10
IDE_DMACK_B/DD4
IDE_IORDY
TXP
TXN
GNDA
VDDA
RXN
RXP
REXT
GNDA
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SPIF223A
TQFP-64
pins
D3V3_IO
DVSS
IDE_DIOR_B/DD11
IDE_DIOW_B/DD3
IDE_DMARQ/DD12
IDE_DD15/DD2
IDE_DD0/DD13
IDE_DD14/DD1
IDE_DD1/DD14
VDDA
XTALO
XTALI/CLKI
UART_SPI_SEL
CFG0
IDE_ORD_INV
D3V3_IO
RESET_B
TQFP_64
QFP64-0.5-SKT-A
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6.ELECTRONICAL SPECIFICATION
6.1. Power Requirement
Table 6-1: Total Power Dissipation
Limits
Typ.
5.0
Symbol
Parameter
Condition
Unit
Min.
0
Max.
IIO
Ianalog
Absolute digital I/O pad power supply
Absolute digital power supply and PHY
3.3v
1.8v
-
-
mA
mA
60
90
6.2. Absolute Maximum Ratings
Table 6-2: Absolute Maximum Ratings
Limits
Typ.
Symbol
Parameter
Condition
Rating
Unit
Min.
3.0
Max.
3.6
VIO
Absolute digital I/O pad power supply
voltage
3.3
1.8
1.8
V
V
V
VCORE
Absolute digital power supply
1.62
1.62
1.98
1.98
VASATA
Absolute analog power supply voltage
for PHY
VI
Absolute input voltage
3.0
-40
3.3
25
3.6
V
℃
TSTR
Absolute storage temperature
150
6.3. Recommended/Typical Operating Conditions
Table 6-3: Recommended/Typical Operating Conditions
Limits
Typ.
1.8
Symbol
Parameter
Condition
Unit
Min.
1.62
3.0
Max.
1.98
3.6
VCORE
VIO
Operating digital power supply voltage
Operating digital I/O pad supply voltage
V
V
3.3
VASATA
Operating analog power supply
voltage for SATA PHY
1.62
1.8
1.98
V
VI
Operating Input signal voltage
Operating temperature
3.0
0
3.3
25
3.6
70
V
℃
TOPE
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6.4. DC Characteristics
Table 6-4 DC Characteristics
Limits
Typ.
-
Symbol
Parameter
Condition
Unit
Min.
-0.3
2.0
Max.
VIL
VIH
VT
Input low voltage
0.8
VDDPST+0.3
1.77
V
V
V
V
Input high voltage
-
Threshold point
1.45
1.47
1.59
1.50
+
Schmitt trig. Low to High threshold point
1.50
VT
VT
II
-
Schmitt trig. high to low threshold point
0.90
0.94
0.96
V
± 10
± 10
114
129
0.4
Input leakage current
Tri-state output leakage current
Pull-up resistor
VI=5.5V or 0V
VO=5.5V or 0V
-
-
-
-
µA
µA
KΩ
KΩ
V
IOZ
RPU
RPD
VOL
VOH
IOL
46
30
-
70
58
-
Pull-down resistor
Output low voltage
IOL (min)
IOH (min)
Output high voltage
Low level output current
2.4
4.5
8.9
12.3
18.5
-
-
V
VOL=0.4V
OL=0.4V
VOL=2.4V
4mA
6.6
13.2
24.8
37.1
8.3
mA
mA
mA
mA
V
8mA
8mA
16.7
40.5
60.8
IOH
High level output current
VOL=2.4V 12mA
6.5. SPIF223A UART and SPI Interface Select:
Mode
Master
Slave
IDE_JUMP0
IDE_JUMP1
SPIF223A have supported 2 IO interface: UART and SPI. Then,
it could be configured by pin21 (UART_SPI_Sel)
UART_SPI_Sel : 0 Using UART interface.
0
1
1
0
0
1
Cable Select
UART_SPI_Sel : 1 Using SPI interface.
6.8. SPIF223A Serial ATA bus Tri-state Feature:
6.6. SPIF223A Device Mode or Host :
SPIF223A have supported Serial ATA bus Tri-state feature under
UART_SPI_SEL as low. It could help to design a combo interface
or multi-interface product.
SPIF223A have supported both dirction : SerialATA to ATA host
bridge and ATA to SerialAT host bridge. Then, we could use pin20
(H_D_Sel).
SPI_CLK : Low
SPI_CLK : High
Serial ATA bus Hi-Z.
H_D_Sel : 0
Serial ATA device to ATA host mode
Serial ATA bus normal feature.
(Connecting to ATA HDD)..
H_D_Sel : 1
ATA device to Serial ATA host mode.
6.9. SPIF223A ATA bus Tri-state Feature:
(Connecting to Serial ATA HDD).
SPIF223A have supported ATA bus tri-state by pin 38 (SPI_EN). If
SPI_EN# is low, SPIF223A will enable ATA bus Tri-state. If
SPI_EN# is high, SPIF223A will go into normal function to accept
ATA bus access. (For this mode, UART_SPI_Sel must be low.)
6.7. SPIF223A ATA Device Mode Select:
When SPIF223A have been choice to H_D_Sel as 1, it will use as
ATA device mode. For ATA device, SPIF223A could support
master, slave and Cable select. It could be configured by :
SPI_EN# : Low
SPI_EN#: High
ATA bus Tri-State
ATA bus normal feature.
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7.COMMAND LIST
The SPIF223A ATA to Serial ATA Controller decodes ATA
commands in hardware. The commands supported include
ATA/ATAPI-5 and ATA/ATAPI-6 commands, including the 48-bit
LBA extended commands. Certain obsolesced commands are
also supported. The supported commands are listed below:
7.1. ATA Command List:
Table 7-1 ATA Standard Commands
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7.2. ATAPI Command List:
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3
3
About ATAPI command, SPIF223A will not support 16-byte SCSI command if ATAPI device don’t indicate 16-byte packet support on
Identify packet device information.
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8.PACKAGE/PAD LOCATIONS
8.1. Package Information
8.1.1. 64 pin TQFP
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Fig 8-1: SPIF223A in TQFP-64 package
◎E-Pad dimension could be changed without notice.
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8.2. Ordering Information
Product Number
SPIF223A - HF021
Package Type
Green Package form – TQFP 64*
8.3. Storage Condition and Period for Package
Package
Moisture sensitivity level
Max. Reflow temperature
Floor life storage condition
Dry pack
TQFP
LEVEL 3
255 +5/-0℃
168Hrs @ ≦30℃/ 60% R.H.
Yes
Note1: Please refer to IPC/JEDEC standard J-STD-020A and EIA JEDEC stand JFSD22-A112
Note2: or refer to the “CAUTION Note” on dry pack bag.
8.4. Recommended SMT Temperature Profile
This “Recommended” temperature profile is a rough guideline for
SMT process reference. Most of SUNPLUS leadframe base
product choice Matte Tin and Sn/Bi for plating recipe. For
PPF(Pre-Plated Frame) product with 63/37 solder paste, we
recommend 240℃~245℃ for peak temperature.
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9.DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or
regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and
prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this
publication are current before placing orders. Products described herein are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are
specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits
illustrated in this document are for reference purposes only.
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MAY 29, 2006
Version: 1.2
http://www.golon.net E-mail:wuyuanqi2@126.com
Mr Wu 13798432566
SPIF223A
10. REVISION HISTORY
Date
Revision #
Description
Page
MAY 29, 2006
1.2
1.Update application into datasheet . (UART/SPI, ATA_bus Tri-State, SerialATA Hi_Z)
2.Update AC timing
3-6
10-11
12-16
3.Add command list for ATA command and Packet command.
APR. 25, 2006
1.1
1.Update application into datasheet . (UART/SPI, ATA_bus Tri-State, SerialATA Hi_Z)
2.Update AC timing
3-6
10-11
12-16
18
3.Add command list for ATA command and Packet command.
4.Update pin assignment,
5.Add ATA interface reverse 5.3 section.
6-8
SEP. 08, 2005
1.0
Original
16
21
MAY 29, 2006
Version: 1.2
http://www.golon.net E-mail:wuyuanqi2@126.com
Mr Wu 13798432566
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