SOC-3000 [ETC]
Scale-On-Chip ASIC Technical Specification Rev.B1; 尺度片ASIC技术规格Rev.B1
| 型号： | SOC-3000 |
| 厂家： | 
ETC |
| 描述： | Scale-On-Chip ASIC Technical Specification Rev.B1 |
| 文件： | 总98页 (文件大小：1070K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SOC-3000/i
Scale-On-Chip ASIC
Technical Specification Rev.B1
July 2002
Document order number: SOC-3000-0001-SP
2001 CybraTech (1998) Ltd. All rights reserved.
CybraTech (1998) Ltd. reserves the right to alter the equipment specifications and descriptions in this publication
without prior notice. No part of this publication shall be deemed to be part of any contract or warranty unless
specifically incorporated by reference into such contract or warranty.
The information contained herein is merely descriptive in nature, and does not constitute a binding offer for the sale of
the product described herein.
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
TABLE OF CONTENTS
LIST OF FIGURES .................................................................................................................................. IV
LIST OF TABLES ......................................................................................................................................V
GENERAL....................................................................................................................................................1
GENERAL DESCRIPTION ............................................................................................................................2
ADVANTAGES............................................................................................................................................2
SPECIFICATIONS......................................................................................................................................3
ANALOG-TO-DIGITAL CONVERTER (ADC)...............................................................................................3
ADC Converter Main Channel – Wheatstone Bridge (Load Cell)........................................................3
ADC Converter Auxiliary Channel .......................................................................................................3
REFERENCE INPUTS ...................................................................................................................................4
DIGITAL INPUT ..........................................................................................................................................4
DIGITAL OUTPUT.......................................................................................................................................4
FLASH MEMORY........................................................................................................................................4
CPU...........................................................................................................................................................5
FREQUENCY SOURCE INPUT......................................................................................................................5
POWER SUPPLY AND MONITOR.................................................................................................................5
ENVIRONMENTAL CONDITIONS.................................................................................................................5
ABSOLUTE MAXIMUM RATING* ...............................................................................................................6
OUTLINE DIMENSIONS...............................................................................................................................6
SCALE MAIN BOARD LAYOUT AND ASSEMBLY PROCESS PARAMETERS FOR SOC-3000........................7
PIN CONFIGURATION.............................................................................................................................9
CPU 80C51TBO .........................................................................................................................................21
MEMORY ORGANIZATION .......................................................................................................................22
Flash (Program & Non-Volatile Data) Memory Mapping and Usage ...............................................22
Application Program Start Address ....................................................................................................23
Serial Downloading (In-Circuit Programming)..................................................................................23
Using the Flash for Data Memory ......................................................................................................24
Data Memory Mapping.......................................................................................................................25
Memory Bank Select Register .............................................................................................................25
CPU SFRs and Configuration Registers (CFR)..................................................................................25
INSTRUCTION SET....................................................................................................................................25
RESET ......................................................................................................................................................26
INTERRUPT VECTORS ..............................................................................................................................26
ADC CONTROLLER INTERFACE .......................................................................................................27
CONTROLLER REGISTERS........................................................................................................................27
Semaphore Register.............................................................................................................................27
Control Register..................................................................................................................................27
Revision B
Page i
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Status/Data Registers ..........................................................................................................................28
OPERATION ..............................................................................................................................................29
KEYBOARD CONTROLLER................................................................................................................. 31
CONTROLLER REGISTERS ........................................................................................................................32
REGISTERS DESCRIPTION.........................................................................................................................32
Control Register ..................................................................................................................................32
Data Registers .....................................................................................................................................32
OPERATION ..............................................................................................................................................33
LCD CONTROLLER/DRIVER .............................................................................................................. 35
LCD Bias Generator............................................................................................................................36
Drive Mode Waveforms.......................................................................................................................36
REGISTERS DESCRIPTION.........................................................................................................................42
Control Register ..................................................................................................................................42
Data Registers .....................................................................................................................................43
OPERATION ..............................................................................................................................................44
LED PARALLEL DISPLAY CONTROLLER ...................................................................................... 45
REGISTERS DESCRIPTION.........................................................................................................................46
Semaphore Register.............................................................................................................................47
Data Registers .....................................................................................................................................47
OPERATION ..............................................................................................................................................48
LED SERIAL INTERFACE DISPLAY CONTROLLER..................................................................... 49
REGISTERS DESCRIPTION.........................................................................................................................50
Control Register ..................................................................................................................................51
Semaphore Register.............................................................................................................................51
Data Registers .....................................................................................................................................52
OPERATION ..............................................................................................................................................53
PROGRAMMABLE FREQUENCY CONTROLLER.......................................................................... 55
OPERATION ..............................................................................................................................................56
CONTROL REGISTERS DESCRIPTION........................................................................................................56
WATCHDOG TIMER.............................................................................................................................. 57
OPERATION ..............................................................................................................................................57
CONTROL REGISTERS DESCRIPTION........................................................................................................57
LOW VOLTAGE DETECTOR............................................................................................................... 59
INTERRUPT REGISTER..............................................................................................................................59
CONFIGURATION REGISTERS (CFR)............................................................................................... 61
SPECIAL FUNCTION REGISTERS (SFR) .......................................................................................... 65
GLOBAL CONFIGURATION REGISTER ......................................................................................................65
Operation.............................................................................................................................................65
CONTROLLERS CLOCK ENABLE REGISTER..............................................................................................66
CONTROLLERS RESET REGISTERS .........................................................................................................67
Revision B
Page ii
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
I/O OPERATION.......................................................................................................................................69
8051-COMPATIBLE ON-CHIP PERIPHERALS..................................................................................71
PARALLEL I/O PORTS ..............................................................................................................................71
Timers/Counters..................................................................................................................................71
SOC-3000 INITIALIZATION ..................................................................................................................73
SOC-3000 HARDWARE DESIGN CONSIDERATIONS AND PERIPHERAL INTERFACE
CONNECTIONS........................................................................................................................................75
LOAD CELL INTERFACE...........................................................................................................................75
4-Wire and 6-Wire Interfaces..............................................................................................................75
Load Cells Connected in Parallel .......................................................................................................77
Load Cell Impedance ..........................................................................................................................78
KEYBOARD INTERFACE ...........................................................................................................................78
LCD DISPLAY INTERFACE ......................................................................................................................79
LED DISPLAY INTERFACE.......................................................................................................................80
EXTERNAL INTERRUPT SOURCES ............................................................................................................80
Using the Vdet input:...........................................................................................................................80
Using Timer0 and Timer1 inputs: .......................................................................................................81
I2C-COMPATIBLE INTERFACE..................................................................................................................81
POWER SAVING SCHEMES .......................................................................................................................81
GROUNDING AND BOARD LAYOUT RECOMMENDATIONS.......................................................................82
IN-CIRCUIT EMULATOR (ICE) SYSTEM..........................................................................................83
EXAMPLES OF PIN CONFIGURATION PROGRAMMING............................................................85
EXAMPLE 1: CONFIGURING A 20-DIGIT LCD DISPLAY AND AN 8X8 KEYBOARD...................................85
EXAMPLE 2: CONFIGURING A 16-DIGIT LCD DISPLAY, AN 8X4 KEYBOARD, 8 OUTPUT AND 4 I/O
PORTS ......................................................................................................................................................86
EXAMPLE 3: CONFIGURING A 21-DIGIT LED PARALLEL DISPLAY, AN 8X8 KEYBOARD AND 13
OUTPUT PORTS........................................................................................................................................87
EXAMPLE 4: OUTPUTS AND I/O PORTS PROGRAMMING .........................................................................88
Revision B
Page iii
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
LIST OF FIGURES
FIGURE 1:
FIGURE 2:
FIGURE 3:
FIGURE 4:
FIGURE 5:
FIGURE 6:
FIGURE 7:
FIGURE 8:
FIGURE 9:
FIGURE 10:
FIGURE 11:
FIGURE 12:
FIGURE 13:
FIGURE 14:
FIGURE 15:
FIGURE 16:
FIGURE 17:
FIGURE 18:
FIGURE 19:
FIGURE 20:
FIGURE 21:
FIGURE 22:
FIGURE 23:
FIGURE 24:
FIGURE 25:
FIGURE 26:
FIGURE 27:
FIGURE 28:
FIGURE 29:
FIGURE 30:
FIGURE 31:
SOC-3000 TYPICAL APPLICATION ........................................................................................ 1
SOC-3000 BLOCK DIAGRAM................................................................................................. 2
MECHANICAL OUTLINE DRAWING ........................................................................................ 6
MAIN BOARD PADS DIMENSIONS RECOMMENDATION ........................................................ 7
SOC-3000 PIN ARRANGEMENT ........................................................................................... 15
SOC-3000 LCD DISPLAY PIN CONFIGURATION ................................................................. 16
SOC-3000 LED DISPLAY PIN CONFIGURATION ................................................................. 17
CPU BLOCK DIAGRAM........................................................................................................ 21
SOC-3000 PROGRAM MEMORY MAP.................................................................................. 22
SOC-3000/I STARTUP PROCEDURE .................................................................................... 24
SOC-3000 DATA MEMORY MAP......................................................................................... 25
KEYBOARD MATRIX CONFIGURATION ................................................................................ 31
LCD CONTROLLER/DRIVER BLOCK DIAGRAM ................................................................... 35
STATIC DRIVE MODE WAVEFORMS..................................................................................... 37
1:2 MULTIPLEX DRIVE RATIO–1/2 BIAS WAVEFORMS....................................................... 38
1:2 MULTIPLEX DRIVE RATIO–1/3 BIAS WAVEFORMS....................................................... 39
1:3 MULTIPLEX DRIVE RATIO WAVEFORMS....................................................................... 40
1:4 MULTIPLEX DRIVE RATIO WAVEFORMS....................................................................... 41
BACKPLANE OUTPUTS PER LCD DIGIT ............................................................................... 43
LED PARALLEL DISPLAY CONTROLLER BLOCK DIAGRAM ................................................ 45
LED PARALLEL DISPLAY CONTROLLER TIMING DIAGRAM ............................................... 46
LED SERIAL INTERFACE DISPLAY BLOCK DIAGRAM ......................................................... 49
LED SERIAL INTERFACE CONTROLLER TIMING DIAGRAM................................................. 50
CLOCK GENERATOR BLOCK DIAGRAM ............................................................................... 55
LOW VOLTAGE DETECTOR .................................................................................................. 59
4-WIRE LOAD-CELL CONNECTION ...................................................................................... 76
6-WIRE LOAD-CELL CONNECTION ...................................................................................... 76
MULTIPLE LOAD-CELL CONNECTION.................................................................................. 77
KEYBOARD INTERFACE ....................................................................................................... 78
LCD DISPLAY INTERFACE................................................................................................... 79
LED PARALLEL DISPLAY INTERFACE ................................................................................. 80
Revision B
Page iv
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
LIST OF TABLES
TABLE 1: SOC-3000 PIN CONFIGURATION FOR LCD DISPLAY.................................................................9
TABLE 2: SOC-3000 PIN CONFIGURATION FOR LED DISPLAY...............................................................12
TABLE 3: NOTES ON SOC-3000 PIN CONFIGURATION.............................................................................15
TABLE 4: SOC-3000 QUICK REFERENCE PIN CONFIGURATION FOR LCD DISPLAY ...............................18
TABLE 5: SOC-3000 QUICK REFERENCE PIN CONFIGURATION FOR LED DISPLAY ...............................19
TABLE 6: INTERRUPT VECTORS DESCRIPTION.........................................................................................26
TABLE 7: ADC CONTROLLER REGISTERS DESCRIPTION .........................................................................27
TABLE 8: ADC CONTROLLER INTERFACE SEMAPHORE REGISTER BIT DEFINITIONS .............................27
TABLE 9: ADC CONTROLLER INTERFACE CONTROL REGISTER BIT FUNCTIONS....................................28
TABLE 10:
TABLE 11:
TABLE 12:
TABLE 13:
TABLE 14:
TABLE 15:
TABLE 16:
TABLE 17:
TABLE 18:
TABLE 19:
TABLE 20:
TABLE 21:
TABLE 22:
TABLE 23:
TABLE 24:
TABLE 25:
TABLE 26:
TABLE 27:
TABLE 28:
TABLE 29:
TABLE 30:
TABLE 31:
TABLE 32:
TABLE 33:
TABLE 34:
TABLE 35:
TABLE 36:
TABLE 37:
TABLE 38:
TABLE 39:
TABLE 40:
TABLE 41:
TABLE 42:
TABLE 43:
TABLE 44:
ADC CONTROLLER INTERFACE DATA REGISTER BIT DEFINITIONS....................................28
ADC CONTROLLER INTERFACE DATA REGISTER BIT FUNCTIONS ......................................28
ADC OUTPUT COUNTS VS. ADC SETTINGS ......................................................................30
KEYBOARD CONTROLLER REGISTERS DESCRIPTION ...........................................................32
KEYBOARD CONTROLLER CONTROL REGISTER BIT FUNCTIONS.........................................32
KEYBOARD CONTROLLER DATA REGISTER BIT DEFINITIONS.............................................33
MAXIMUM DISPLAY CAPACITY PER DISPLAY CONFIGURATION..........................................36
LCD BIAS CONFIGURATIONS...............................................................................................36
LCD CONTROLLER/DRIVER REGISTERS DESCRIPTION........................................................42
LCD CONTROLLER CONTROL REGISTER BIT FUNCTIONS ...................................................42
LCD CONTROLLER DATA REGISTER BIT DEFINITIONS – 20-DIGIT DISPLAY......................43
LED PARALLEL DISPLAY CONTROLLER DRIVER REGISTERS DESCRIPTION .......................46
LED PARALLEL DISPLAY CONTROLLER SEMAPHORE REGISTER BIT DEFINITIONS ............47
LED PARALLEL DISPLAY CONTROLLER SEMAPHORE REGISTER BIT FUNCTIONS ..............47
LED PARALLEL CONTROLLER DATA REGISTER BIT DEFINITIONS......................................47
LED SERIAL CONTROLLER DRIVER REGISTERS DESCRIPTION............................................50
LED SERIAL INTERFACE DISPLAY CONTROL REGISTER BIT FUNCTIONS ...........................51
LED SERIAL INTERFACE DISPLAY DATA REGISTER BIT DEFINITIONS................................52
CLOCK FREQUENCY CONTROL REGISTER BIT SETTINGS.....................................................56
WATCHDOG TIMER OPERATING PARAMETERS ....................................................................57
WATCHDOG TIMER COMMAND SEQUENCE..........................................................................57
POWER-FAILURE INTERRUPT REGISTER BIT SETTINGS .......................................................59
CFR BIT ASSIGNMENT .........................................................................................................62
GLOBAL CFR REGISTER.......................................................................................................65
CLOCK ENABLE REGISTER ...................................................................................................66
CONTROLLERS CLOCK ENABLE REGISTER BIT FUNCTIONS.................................................67
CONTROLLERS RESET REGISTER........................................................................................67
BIT-ORIENTED I/O PORTS ADDRESSES, PIN AND BIT ASSIGNMENT....................................69
BYTE-ORIENTED OUTPUT PORTS ADDRESSES AND PIN ASSIGNMENT ................................69
AVAILABLE PINS ON THE 80C51 I/O PORT ..........................................................................71
I2C-COMPATIBLE INTERFACE HARDWARE INTERFACE.......................................................81
EXAMPLE 1: 20-DIGIT LCD DISPLAY, 8×8 KEYBOARD ......................................................85
EXAMPLE 2: 16-DIGIT LCD DISPLAY, 8×4 KEYBOARD, 8 OUTPUT, 4 I/O..........................86
EXAMPLE 3: 21-DIGIT LED DISPLAY, 8×8 KEYBOARD, 13 OUTPUT ..................................87
OUTPUT AND I/O PORTS PROGRAMMING.............................................................................88
Revision B
Page v
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
GENERAL
• 4 cycles/instruction
Features
Scale-On-Chip System
• Single-Chip Scale electronics
• Full OIML R-76 compliance
ꢀ SOC-3000 - 3000 d
• 120KByte, field-programmable Flash program
and data memory
• 4KByte RAM
• 4KByte non-volatile Data Flash
Analog–to–Digital Converter
• Resolution-20 bits
• Sample rate-5, 10, 20 samples per second
• Programmable gain-0.5, 0.75, 1, 1.5, 2
ꢀ SOC-3000i - 6000 d
• Up to eight load cells
• 6-wire load cell connection (including Sense
inputs)
Power
Peripherals
• 5/3.3V operation, 15mA
• Battery operation support
• Power failure detector
• Supports LCD and LED displays:
ꢀ LCD: Up to 20 digits (160 segments, 4×40)
ꢀ LED: Up to 24 digits
• Keyboard: Up to 64 keys
Applications
• Serial communication: RS-232/485
• I/O (set-points): Up to 40 lines
• Temperature sensor input
• Price computing scales
• Weighing indicators
• Counting scales
• Checkout scales
CPU
• Enhanced 80C51TBO
LCD (20 digits)
LED (21 digits)
LED/LCD Module
+5V
8 . . . . . 888
SEN+
SIG+
S 0-39
BP 0-3
RS-232
Printer
RS-485
TxD
RxD
SEN–
SIG–
Load Cell
(Up to 8)
SOC-3000
I/O
Set Point
8
VIN
KB 1-8 KBI 1-8
VInp
Buzzer
5V +
3.3V
Up to 64
keys
FIGURE 1: SOC-3000 TYPICAL APPLICATION
Revision B
Page 1
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
General Description
The SOC-3000 ASIC is an 84-pin, single-chip scale intended to replace present-day,
multiple-component weighing scale electronic circuitry designs. It includes the
pre-amplifier, ADC converter, display drivers, keyboard controller, serial
communication, embedded CPU and field-programmable program and data memory.
As a "stand-alone" unit it incorporates all scale hardware functions and represents a true
breakthrough in scale manufacturing. It eliminates the risks, costs and inventory needs
associated with discrete components.
The SOC-3000 comes with a comprehensive software library, which implements
hardware drivers, such as the display and keyboard, as well as most of the standard
weighing functions. A complete development environment is available, enabling youto
tailor and customize the application according to specific needs.
The general SOC-3000 block diagram is presented in Figure 2.
Advantages
•
Generic OIML R-76 approval
•
•
•
Minimize hardware and software development
Significantly cuts time-to-market
Reduces inventory needs
Display
Ref+ Ref-
. . . .
Display Controllers / Drivers
LCD / LED
20 - 24 Digits
MicroController Core And
Peripherals
Load
Cell
Delta - Sigma
ADC
PGA
Serial
Communication
20 Bits
80C51TBO
120Kx8 Program/Data Flash
4K x 8 RAM
MUX
Aux.
Channel
Watchdog Timer
3x16-Bit Timers
Power Supply Monitor
I2C Compatible
I/O
Power-Down
Detector
8
VDET
SPI Like Serial Interfaces
UART
Internal
Bandgap
Reference
Keyboard Controller
8 x 8
Frequency Controller
8
8
Oscillator/
Resonator
Keyboard
FIGURE 2: SOC-3000 BLOCK DIAGRAM
Revision B
Page 2
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
SPECIFICATIONS
Analog-to-Digital Converter (ADC)
ADC Converter Main Channel – Wheatstone Bridge (Load Cell)
PARAMETER
Differential Input Voltage
Programmable Gain
Offset Drift vs. Temperature
Gain Drift vs. Temperature
Integral Non-linearity
Common-Mode Rejection (CMR)
Power Supply Rejection
Output Noise
MIN TYP MAX
UNIT
COMMENTS
0
+10 mV
0.5
2
20
Up to 8 load cell
ppm/ºC
ppm/ºC
%
4
0.004
Of full scale
±1 count
120
120
dB
dB
200
10
nVp-t-p
bit
Resolution
20
20
Sample Rate
5
Samples/s
ADC Converter Auxiliary Channel
PARAMETER
Analog Input Voltage
Offset Drift
MIN
0
TYP
MAX
UNIT
COMMENTS
0.8
20
V
ppm/ºC
Gain Drift
4
ppm/ºC
Resolution
20
20
Bit
Sample Rate
5
10
Samples/s
Revision B
Page 3
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Reference Inputs
PARAMETER
Reference Input
MIN
TYP
MAX
5
UNIT
V
COMMENTS
Ratiometric
Digital Input
PARAMETER
MIN
TYP
MAX
UNIT
COMMENTS
VIH (Input High Voltage)
VIL (Input Low Voltage)
2
5
V
V
TTL Level excluding XTAL
TTL Level excluding XTAL
0.0
0.8
XTAL Input
VIH (Input High Voltage)
VIL (Input Low Voltage)
2.5
V
V
VDD = 3.3V
VDD = 3.3V
0.4
Digital Output
For LCD Display mode:
PARAMETER
MIN TYP MAX UNIT
COMMENTS
VOH (Output High Voltage)
5
V
V
LCD Output set by user by external resistors
LCD Output set by user by external resistors
VOL (Output Low Voltage) 0.0
VLCD
For I/O mode:
PARAMETER
MIN TYP MAX UNIT
COMMENTS
VOH (Output High Voltage)
VOL (Output Low Voltage) 0.0
3.3
0.8
V
V
Flash Memory
PARAMETER
Endurance
MIN
10,000
100
TYP
MAX
UNIT
Cycles
Years
100,000
Data Retention
Erase
Full Memory
Single Block (4kByte)
100
25
ms
ms
Program Byte
20
us
Revision B
Page 4
July, 2002
CybraTech (2000) Ltd.
Technical Specification
COMMENTS
SOC-3000/i Scale-On-Chip ASIC
MIN TYP MAX UNIT
CPU
PARAMETER
Enhanced 80C51TBO
Reset Signal Threshold
Start-Up Time
3.98
V
500
1
ms
ms
•
•
•
From Power On
From Idle Mode
From Power Down
1
ms Oscillator power-down not through OSCEN bit.
500
ms Oscillator power-down through OSCEN bit.
1
ms
From Watchdog Reset
Frequency Source Input
PARAMETER
Frequency Level
MIN
TYP
MAX
16
UNIT
COMMENTS
MHz Crystal oscillator or
resonator
Power Supply and Monitor
PARAMETER
Input Voltage Monitor
MIN
TYP MAX UNIT
COMMENTS
4.50
4.75
2.21
5.25
3.60
V
V
V
V
Power Fail Input Monitor Level
Set by external resistors
Analog Voltage Input (AVCC
)
4.75
3.00
5.00
3.30
Digital Voltage Input (VCC
)
Power Supply Current (IIN)
CPU Freq. = 16 MHz
CPU Freq. = 8 MHz
CPU Freq. = 4 MHz
CPU Freq. = 2 MHz
CPU Freq. = 1 MHz
CPU Freq. = 0.5 MHz
5V and 3.3V .
21
15
12
11
10
10
mA Without connected I/O ports
mA All controllers operating.
mA Depends on the software
program and the Flash memory
utilization.
mA
mA
mA
Environmental Conditions
PARAMETER
Temperature
MIN
-10
-20
0
TYP
20
MAX
UNIT
COMMENTS
Full performance
40
70
95
ºC
ºC
%
20
Operation
Humidity
Non-condensing
Revision B
Page 5
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Absolute Maximum Rating*
PARAMETER
MIN
TYP
MAX
6
UNIT
V
COMMENTS
Analog power
Digital power
Power
AVCC
VDD
4
V
VCC
6
V
Input Signal Voltage
Operating Temperature
Storage Temperature
3.6
+70
+85
V
–20
–20
ºC
ºC
Lead Temperature
Manual soldering
Reflow soldering
300
225
ºC
ºC
Soldering for 10 seconds
60 seconds
*
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only. The functional operation of the device under these or any other conditions outside of the range listed in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect the reliability of the device.
Outline Dimensions
The outline dimensions of the SOC-3000 PLCC-84 case is shown in Figure 3.
0.045
X 45º
(1.143)
PIN 1
Indicates relative
locations of Pin 1
1.150 (29.20)
Sq.
1.158 (29.41)
1.185 (30.09)
Sq.
1.155 (30.35)
FIGURE 3: MECHANICAL OUTLINE DRAWING
Revision B
Page 6
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Scale Main Board Layout And Assembly Process
Parameters For SOC-3000
1. Pad definition will be according to Figure 4.
2. Solder mask opening should be 3mil (total 6 mil).
3. Board finish may be HAL (hot air leveling), immersion gold over nickel or
immersion.
4. Verify that the SOC-3000 components are packaged in hermetically sealed package.
If the packaging is damaged or has been opened, perform the following drying
procedure to assure that SOC-3000 components are completely dry:
•
Components drying procedure:
Place the SOC-3000 components in their tray and put them into a baking oven
to dry at a temperature of 105ºC for a minimum of 6 hours.
5. Reflow temperature profile should be set according to the paste parameters.
6. Maximum reflow temperature should be less than 225 ºC.
7. Recommended paste: Koki, AIM, Multicore
a.
b.
c.
Type 3
NC
RMA or equivalent
FIGURE 4: PCB BOARD LAYOUT
(Dimensions are in milli inches (mil))
Revision B
Page 7
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
PIN CONFIGURATION
The SOC-3000 pin configuration for LCD and LED displays is presented in Table 1 and
Table 2, respectively, followed by a glossary of terms used in the tables.
General notes on SOC-3000 pin configuration are presented in Table 3, page 15.
The physical pin arrangement is shown in Figure 5, page 15.
The physical pin configuration for an LCD display is shown in Figure 6, page 16,
followed by a quick reference table in Table 4, page 18.
The physical pin configuration for a LED display is shown in Figure 7, page 17,
followed by a quick reference table in Table 5, page 19.
TABLE 1: SOC-3000 PIN CONFIGURATION FOR LCD DISPLAY
PIN
NAME
DESCRIPTION
2nd
DESCRIPTION PULL-UP
RESISTOR
FUNCTION
1
2
3
4
5
6
7
KIN4
Keyboard Controller Input
I.O 15.3
I.O 15.4
I.O 15.5
I.O 15.6
I.O 15.7
I/O, See “I/O
Operation”, page
65
50k
See “Keyboard Controller”, page 31
KIN3
KIN2
KIN1
KIN0
VDD
Digital Power Supply
Buzzer
BUZZER /
P1.7 (CPU)
25k
10k
8
9
P1.5 (CPU) CPU I/O Port
See Note 11
P1.4 (CPU)
10
11
12
13
14
XTAL OUT Frequency Clock Source
XTAL IN
TXD
RXD
Serial Communication Tx
Serial Communication Rx
100k
PWR_OFF / Power Off Control
P3.4/Timer 0
P3.4 (CPU) CPU I/O Ports, or: 50k
P3.4 – Timer 0
15
16
MAIN_DET / Battery/AC power supply detector input P3.5 (CPU)
P3.5 /Timer1
EL /
Electro-luminescent light control
P1.6 (CPU)
P1.6 (CPU) See Note 11
17
18
19
20
21
VLCD
BP1
BP2
BP3
BP4
LCD Display voltage
LCD Display Multiplexer Backplanes, OUT 4.0
I/O See “I/O
Operation”, page
69
See “LCD Controller/Driver”, page 35
OUT 4.1
OUT 4.2
OUT 4.3
Revision B
Page 9
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
PIN
22
NAME
DESCRIPTION
2nd
DESCRIPTION PULL-UP
RESISTOR
FUNCTION
S1
S2
S3
S4
S5
S6
S7
S8
S9
LCD Display Segment
OUT 5.0
OUT 5.1
OUT 5.2
OUT 6.0
OUT 6.1
OUT 6.2
OUT 6.3
OUT 7.0
OUT 7.1
OUT 7.2
OUT 7.3
OUT 8.0
OUT 8.1
OUT 8.2
OUT 8.3
OUT 9.0
OUT 9.1
OUT 9.2
I/O See “I/O
Operation”, page
69
See “LCD Controller/Driver”, page 35
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
OUT 10.0
OUT 11.0
OUT 11.1
OUT 11.2
OUT 11.3
OUT 12.0
OUT 12.1
OUT 12.2
OUT 12.3
OUT 12.4
OUT 13.0
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
PIN
59
NAME
S38
DESCRIPTION
2nd
DESCRIPTION PULL-UP
RESISTOR
FUNCTION
OUT 13.1
OUT 13.2
OUT 13.3
60
61
S39
S40
62
63
64
65
VCC
Power Supply
RESET
GND
Reset
50k
Digital Ground
VDET/
INT0~
Power voltage detector input /
Interrupt 0 Input
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
SIG2+
SIG2–
AGND
SEN–
2nd AD channel input signal +
2nd AD channel input signal –
Analog Ground
Load cell sense input –
Load cell signal input –
Load cell signal input +
Load cell sense input +
Analog power supply
SIG1–
SIG1+
SEN+
AVCC
KOUT7
KOUT6
KOUT5
KOUT4
KOUT3
KOUT2
KOUT1
KOUT0
KIN7
Keyboard Controller Inputs
I.O 14.0
I.O 14.1
I.O 14.2
I.O 14.3
I.O 14.4
I.O 14.5
I.O 14.6
I.O 14.7
I.O 15.0
I.O 15.1
I.O 15.2
I/O See “I/O
Operation”, page
69
50k
See “Keyboard Controller”, page 31
Keyboard Controller Inputs
See “Keyboard Controller”, page 31
KIN6
KIN5
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
TABLE 2: SOC-3000 PIN CONFIGURATION FOR LED DISPLAY
PIN
NAME
DESCRIPTION
2nd
DESCRIPTION PULL-UP
RESISTOR
FUNCTION
1
2
3
4
5
6
7
KIN4
Keyboard Controller Input
I.O 15.3
I.O 15.4
I.O 15.5
I.O 15.6
I.O 15.7
I/O See “I/O
Operation”, page
69
50k
See “Keyboard Controller”, page 31
KIN3
KIN2
KIN1
KIN0
VDD
Digital Power Supply
Buzzer
BUZZER /
P1.7 (CPU)
25k
10k
P1.7=’1’ – ON
P1.7=’0’ – OFF
See Note 10, 11
8
9
P1.5 (CPU)
P1.4 (CPU)
CPU I/O Port.
See Note 11
10 XTAL OUT
11 XTAL IN
12 TXD
Frequency Clock Source
Serial Communication Tx
Serial Communication Rx
Power Off Control
13 RXD
100k
50k
14 PWR_OFF /
P3.4 / Timer 0
P3.4 (CPU) CPU I/O port, or:
P3.4 – Timer 0
P3.5 – Timer 1
See Note 11
15 MAIN_DET /
P3.5 / Timer 1
Battery/AC power supply detector input P3.5 (CPU)
16 EL
Electro-luminescent light control
P1.6 (CPU) See Note 11
17 NC
Not Used
Outputs.
18 OUT 4.0
19 OUT 4.1
20 OUT 4.2
21 OUT 4.3
22 SEG A1
23 SEG B1
24 SEG C1
25 SEG D1
26 SEG E1
27 SEG F1
28 SEG G1
29 SEG DP1
30 SEG A2
31 SEG B2
32 SEG C2
33 SEG D2
OUT 4.0
OUT 4.1
OUT 4.2
OUT 4.3
OUT 5.0
OUT 5.1
OUT 5.2
OUT 6.0
OUT 6.1
OUT 6.2
OUT 6.3
OUT 7.0
OUT 7.1
OUT 7.2
OUT 7.3
OUT 8.0
I/O See “I/O
Operation”, page
69
Display Segment Out,
see “LED Parallel Display Controller
Block Diagram”, page 45
Revision B
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CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
PIN
NAME
DESCRIPTION
Display Segment Out,
2nd
DESCRIPTION PULL-UP
RESISTOR
FUNCTION
Output, I/O See
“I/O Operation”,
page 69
34 SEG E2
35 SEG F2
36 SEG G2
37 SEG DP2
38 SEG A3
39 SEG B3
40 SEG C3
41 SEG D3
42 SEG E3
43 SEG F3
44 SEG G3
45 SEG DP3
46 DIG 1
OUT 8.1
OUT 8.2
OUT 8.3
OUT 9.0
OUT 9.1
OUT 9.2
see “LED Parallel Display Controller
Block Diagram”, page 45.
Display Digit Mux Control
See “LED Parallel Display Controller”,
page 45
47 DIG 2
48 DIG 3
OUT 10.0
OUT 11.0
OUT 11.1
OUT 11.2
OUT 11.3
I/O See “I/O
Operation”, page
69
49 DIG 4
50 DIG 5
51 DIG 6
52 DIG 7
53 OUT 12.0
54 OUT 12.1
55 OUT 12.2
56 OUT 12.3
57 OUT 12.4
Output
See “I/O Operation”, page 69
58 LED_SI_CLK LED Serial Interface Display Module
Clock, Data, Strobe and Blank
OUT 13.0
OUT 13.1
OUT 13.2
OUT 13.3
I/O See “I/O
Operation”, page
69
59 LED_SI_Data
See “LED Serial Interface Display
Controller”, page 49.
60 LED_SI_ST
61 LED_SI_BL
62 VCC
Power Supply
Reset
63 RESET
64 GND
50k
Digital Ground
65 VDET/
INT0~
Power voltage detector input /
Interrupt 0 Input
2nd ADC channel input signal +
2nd ADC channel input signal –
Analog Ground
66 SIG2+
67 SIG2–
68 AGND
69 SEN–
Load cell sense input –
Revision B
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CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
PIN
NAME
DESCRIPTION
Load cell signal input –
2nd
DESCRIPTION PULL-UP
RESISTOR
FUNCTION
70 SIG1–
71 SIG1+
72 SEN+
73 AVCC
74 KOUT7
75 KOUT6
76 KOUT5
77 KOUT4
78 KOUT3
79 KOUT2
80 KOUT1
81 KOUT0
82 KIN7
Load cell signal input +
Load cell sense input +
Analog power supply
Keyboard Controller Output, See
“Keyboard Controller”, page 31
I.O 14.0
I.O 14.1
I.O 14.2
I.O 14.3
I.O 14.4
I.O 14.5
I.O 14.6
I.O 14.7
I.O 15.0
I.O 15.1
I.O 15.2
I/O See “I/O
Operation”, page
69
50k
Keyboard Controller Input, See
“Keyboard Controller”, page 31
83 KIN6
84 KIN5
GLOSSARY OF TERMS
TERM DEFINITION
BP
Backplane
Clock
CLK
DIG
I.O
Digit
Input/Output
Keyboard In
Keyboard Out
KIN
KOUT
P/PWR Power
REG
RX
Register
Receive
SEG
SI
Segment
Serial Interface
Transmit
TX
Revision B
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CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
TABLE 3: NOTES ON SOC-3000 PIN CONFIGURATION
#
COMPONENT
LCD Controller/Driver
LED Controller
REMARKS
1
2
•
Bit programmable
oh @ Io = 1.5mA
Bit programmable
•
•
V
3
4
5
Output Pins
Input Pins
VDET
CMOS–3.3V
CMOS–3.3V
•
•
•
Less than 5V
Threshold level – 2.1V.
The input (on the analog chip) tolerates input voltage
applied while the SOC-3000 is powered off.
6
7
8
9
VDD
3.3V ±5%
VCC
5V ±5%
AVCC
5V ±5%
Keyboard Controller
Bit programmable
10 Buzzer
P1.7 is used as the BUZZER control pin. During power-up
the SOC-3000 asserts 3 pulses on this line.
11 Port 1.x
Manipulation of this pin should be made using BIT mapping
of the port, since bits P1.0-P1.1 are allocated to the bank
select register.
P11
P1 P84
P75
P12
P32
PIN 1
IDENTIFIER
SOC3000
PLCC84
P33
P53
FIGURE 5: SOC-3000 PIN ARRANGEMENT
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
FIGURE 6: SOC-3000 LCD DISPLAY PIN CONFIGURATION
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
FIGURE 7: SOC-3000 LED DISPLAY PIN CONFIGURATION
Revision B
Page 17
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
TABLE 4: SOC-3000 QUICK REFERENCE PIN CONFIGURATION FOR LCD DISPLAY
PIN
1
NAME
KIN4 / I.O 15.3
KIN3 / I.O 15.4
KIN2 / I.O 15.5
KIN1 / I.O 15.6
KIN0 / I.O 15.7
VDD
PIN
NAME
PIN
NAME
PIN
NAME
22 S1 / OUT 5.0
23 S2 / OUT 5.1
24 S3 / OUT 5.2
25 S4 / OUT 6.0
26 S5 / OUT 6.1
27 S6 / OUT 6.2
28 S7 / OUT 6.3
29 S8 / OUT 7.0
30 S9 / OUT 7.1
31 S10 / OUT 7.2
32 S11 / OUT 7.3
33 S12 / OUT 8.0
34 S13 / OUT 8.1
35 S14 / OUT 8.2
36 S15 / OUT 8.3
37 S16 / OUT 9.0
38 S17 / OUT 9.1
39 S18 / OUT 9.2
40 S19
43 S22
44 S23
45 S24
46 S25
47 S26
64 GND
2
65 VDET / INT 0~
66 SIG2+
3
4
67 SIG2–
5
68 AGND
6
48 S27 / OUT 10.0
49 S28 / OUT 11.0
50 S29 / OUT 11.1
51 S30 / OUT 11.2
52 S31 / OUT 11.3
53 S32 / OUT 12.0
54 S33 / OUT 12.1
55 S34 / OUT 12.2
56 S35 / OUT 12.3
57 S36 / OUT 12.4
58 S37 / OUT 13.0
59 S38 / OUT 13.1
60 S39 / OUT 13.2
61 S40 / OUT 13.3
62 VCC
69 SEN–
7
BUZZER / P1.7
P1.5 (CPU)
70 SIG1–
8
71 SIG1+
9
P1.4 (CPU)
72 SEN+
10 XTAL OUT
11 XTAL IN
12 TXD
73 AVCC
74 KOUT7 / I.O 14.0
75 KOUT6 / I.O 14.1
76 KOUT5 / I.O 14.2
77 KOUT4 / I.O 14.3
78 KOUT3 / I.O 14.4
79 KOUT2 / I.O 14.5
80 KOUT1 / I.O 14.6
81 KOUT0 / I.O 14.7
82 KIN7 / I.O 15.0
83 KIN6 / I.O 15.1
84 KIN5 / I.O 15.2
13 RXD
14 PWR_OFF / P3.4 (CPU) /
Timer 0
15 MAIN_DET / P3.5 (CPU)
/ Timer 1
16 EL / P1.6 (CPU)
17 VLCD
18 BP1 / OUT 4.0
19 BP2 / OUT 4.1
20 BP3 / OUT 4.2
21 BP4 / OUT 4.3
41 S20
42 S21
63 RESET
Revision B
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CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
TABLE 5: SOC-3000 QUICK REFERENCE PIN CONFIGURATION FOR LED DISPLAY
PIN
1
NAME
KIN4 / I.O 15.3
KIN3 / I.O 15.4
KIN2 / I.O 15.5
KIN1 / I.O 15.6
KIN0 / I.O 15.7
VDD
PIN
NAME
PIN
NAME
PIN
NAME
22 SEG A1 / OUT 5.0
23 SEG B1 / OUT 5.1
24 SEG C1 / OUT 5.2
25 SEG D1 / OUT 6.0
26 SEG E1 / OUT 6.1
27 SEG F1 / OUT 6.2
28 SEG G1 / OUT 6.3
43 SEG F3
64 GND
2
44 SEG G3
65 VDET / INT 0 ~
66 SIG2+
3
45 SEG DP3
46 DIG 1
4
67 SIG2–
5
47 DIG 2
68 AGND
6
48 DIG 3 / OUT 10.0
49 DIG 4 / OUT 11.0
69 SEN–
7
BUZZER / P1.7
P1.5 (CPU)
70 SIG1–
8
29 SEG DP1 / OUT 7.0 50 DIG 5 / OUT 11.1
71 SIG1+
9
P1.4 (CPU)
30 SEG A2 / OUT 7.1
31 SEG B2 / OUT 7.2
32 SEG C2 / OUT 7.3
33 SEG D2 / OUT 8.0
34 SEG E2 / OUT 8.1
35 SEG F2 / OUT 8.2
36 SEG G2 / OUT 8.3
51 DIG 6 / OUT 11.2
52 DIG 7 / OUT 11.3
53 OUT 12.0
72 SEN+
10 XTAL OUT
11 XTAL IN
12 TXD
73 AVCC
74 KOUT7/I.O 14.0
75 KOUT6/I.O 14.1
76 KOUT5/I.O 14.2
77 KOUT4/I.O 14.3
78 KOUT3/I.O 14.4
79 KOUT2/I.O 14.5
80 KOUT1/I.O 14.6
81 KOUT0/I.O 14.7
82 KIN7/I.O 15.0
83 KIN6/I.O 15.1
84 KIN5/I.O 15.2
54 OUT 12.1
13 RXD
55 OUT 12.2
14 PWR_OFF / P3.4 /
Timer 0
56 OUT 12.3
57 OUT 12.4
15 MAIN_DET / P3.5 /
Timer 1
37 SEG DP2 / OUT 9.0 58 OUT 13.0
38 SEG A3 / OUT 9.1
39 SEG B3 / OUT 9.2
40 SEG C3
59 OUT 13.1
60 OUT 13.2
61 OUT 13.3
62 VCC
16 EL / P1.6
17 Not Connected
18 OUT / OUT 4.0
19 OUT / OUT 4.1
20 OUT / OUT 4.2
21 OUT / OUT 4.3
41 SEG D3
42 SEG E3
63 RESET
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
.
Revision B
Page 20
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
CPU 80C51TBO
The reference source for data given here is “M8051TBO Technical Specifications”, Virtual IP Group,
Inc., Version M8051TS97DF01. Refer to this manual for complete CPU specification.
Features
Advantages
• 8-bit CPU
• Fast running and improved performance
• No wasted clock and memory cycles
• Compatible with standard 80C31
• Four 8-bit I/O ports
• Three 16-bit timers
• On-chip oscillator and clock circuitry
• 256-byte on-chip, 8051-compatible SFR RAM
• 64Kbyte program memory with bank switching
• 4Kbyte XDATA RAM for data memory
• High-speed architecture of 4 cycles/instruction
• Dual data pointers
• Works efficiently with all types of peripheral
devices
• Improved power consumption characteristics
• On-chip Power-On/Reset
Architecture
The CPU block diagram is presented in Figure 8.
Accumulator
B Register
ALU Reg. 2
ALU Reg. 1
PSW
Stack Pointer
ALU
Interrupt
Logic
DPTR1
PC Address Reg.
Address Bus
Buffer
PCIncrement
256 Bytes
SFR 8 RAM
Program Counter
DPTR0
Interrupt Reg.
Instruction
Decoder
Clocks and
Memory Control
Power Control
Register
Reset
Control
Oscillator
DataBus
FIGURE 8: CPU BLOCK DIAGRAM
Revision B
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CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
.
Memory Organization
The SOC-3000 is an 8051-compatible device with an 80C310 memory chip. As with all such
devices, the SOC-3000 has separate address spaces for Program and Data memory. They are:
•
Flash memory – memory space containing non-volatile, in-circuit re-programmable code
and data (such as calibration data). The code in the Flash memory may be in-circuit
programmed at a byte level, although it must first be erased, the erasing being performed
in page blocks. The program memory space can be in-circuit programmed through the
serial port.
•
RAM memory – Random Access memory used as “scratchpad memory” for the software.
Flash (Program & Non-Volatile Data) Memory Mapping and Usage
The 8051-compatible SOC-3000 supports a maximum code space of 64K. Programs larger
than 64K are handled by bank switching to select one of a number of code banks residing at
one physical address.
In the SOC-3000, there is one 32K Common-Program Area mapped from address 0000H to
7FFFH (Figure 9) and three 32K code banks mapped from code address 8000H to FFFFH
(Figure 9). The code banks are selected using bits in a memory-mapped address.
The Flash memory may be dynamically allocated between the Program and the Non-Volatile
Data memory. This eliminates the need of external EEPROM usually used for storing
calibration parameters and other non-volatile variable data.
The Flash memory is built of 4K Bytes of erasable blocks whose boundary is located at 4k
address (multiples of 1000H).
FFFFH
Flash Data
Memory
F800H
ROM
Bank 1
32K
ROM
Bank 2
32K
ROM
Bank 3
32K
8000H
7FFFH
ROM
Common
Area
32K
FFFH
4K
Reserved by
System
0000H
FIGURE 9: SOC-3000 PROGRAM MEMORY MAP
Revision B
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CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Application Program Start Address
The start address of the application program should be located at 1000H, as the first 4kBytes
are reserved for the SOC-3000/I system.
Serial Downloading (In-Circuit Programming)
As part of its embedded boot software the SOC-3000 facilitates serial code and data
download via the standard UART serial port. Serial download mode is automatically entered
upon power-up or reset if one of the following conditions exist:
1. No valid program is programmed in the Flash memory.
2. A request for download process was initiated via the UART during the first 200 ms after
power-up/reset.
Once in this mode, you can download code or data files into the Flash memory, while the
device is located on its target board. The is the PC serial download utility, CybraTech
Cloader executable, is provided together with the device and its documentation and software
library.
The SOC-3000/I may be programmed only if, within 200ms after power-up or RESET, it
establishes communication with the Cloader executable, or if the application program is not
available or not valid (checksum error). Figure 10describes the startup procedure of the
SOC-3000.
Revision B
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CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
.
Power-Up /
Reset
Is
Cloader
Communicating
?
Start
Programming
mode
Yes
No
200 ms
elapsed
?
No
Yes
Is the
Application
Program
OK?
No
Yes
Start Application
Program
FIGURE 10: SOC-3000/I STARTUP PROCEDURE
Using the Flash for Data Memory
The Flash memory may be used for storing non-volatile data. To update the data area while
the program is running, the Flash must be defined as DATA area instead of as CODE area.
CybraTech Flash Manager software manages this process in an efficient and reliable
manner. It provides the means to read, write, erase and update the Flash Data area. A
detailed description of the CybraTech Flash Manager function is included in the SOC-3000
Software Function Library user manual, document number: SOC-0000-SW01-OM.
Revision B
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CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Data Memory Mapping
The SOC-3000 “scratchpad” data memory is stored in 4Kbyte RAM mapped as XDATA, as
shown in Figure 11, in addition to the CPU 256-byte RAM.
8FFFH
Reserved
8C00H
8BFFH
External
RAM
3K
8000H
FIGURE 11: SOC-3000 DATA MEMORY MAP
Memory Bank Select Register
The memory bank select register is implemented using the 80C51TBO Port 1 bits P1.0 –
P1.1. P1.0 is the least significant bit. Manipulation of other Port 1 I/O pins must be carried
out without affecting these bits.
NOTE: The page register is WRITE ONLY! Reading P1.0-P1.1 may result in an
ambiguous result.
CPU SFRs and Configuration Registers (CFR)
The CPU SFRs (Special Function Registers) are compatible with the 8051 instruction set.
For more information, please refer to “M8051TBO Technical Specifications”.
The CPU controls the peripherals and their operating modes through Configuration Registers
(CFR) mapped as XDATA.
The CFR registers for each peripheral are described below in Table 32, page 62.
Instruction Set
All instructions in the 8051-compatible SOC-3000 instruction set perform the same functions
as in the 8051. They identically oversee bit and flag operations and other status functions.
Only the clock configuration differs.
For absolute timing of real time events, the timing of software loops can be calculated.
However, counter/timers default to run at the older 12 clocks per increment. In this way,
timer-based events occur at the standard intervals with software executing at higher speed.
Timers optionally can run at 4 clocks per increment to take advantage of faster processor
operation.
Revision B
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Technical Specification
SOC-3000/i Scale-On-Chip ASIC
.
In the SOC-3000, the MOVX instruction may take only two machine cycles or eight
oscillator cycles, while the “MOV direct, direct” instruction uses three machine cycles or 12
oscillator cycles. Thus, the execution times of the two instructions differ. This is because the
SOC-3000 usually uses one instruction cycle for each instruction byte.
Note that a machine cycle requires just four clocks, and provides one ALE pulse per cycle.
Many instructions require only one cycle, but some require five.
Reset
The Reset signal is generated by an internal circuitry in the ASIC. The signal thresholds are:
RESET Falling edge on Vcc=3.98V.
RESET Rising edge on Vcc=4.19V.
The hystheresis of the RESET signal is set so that normal operation of the internal Flash
memory is guaranteed.
Interrupt Vectors
The interrupt vectors of the SOC-3000/I are shifted compared with the interrupt vectors of a
standard 80C51TBO vectors by an offset of 1000H.
Table 6 details the SOC-3000/I interrupt vectors:
TABLE 6: INTERRUPT VECTORS DESCRIPTION
INTERRUPT SOURCE
FLAG
VECTOR
PRIORITY
LOCATION
External Interrupt 0
IE0
TF0
1003H
100BH
1013H
101BH
1023H
102BH
1 (Highest)
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port
2
3
4
5
6
IE1
TF1
RI + TI
TF2 + EXF2
Timer 2 Overflow
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
ADC CONTROLLER INTERFACE
Features
• Resolution – 20 bit
• Programmable gain –0.5, 0.75, 1, 1.5, 2
• Programmable sample rate of 5, 10 or 20
samples per second
• Voltage detection input and alarm
Controller Registers
ADC Converter (ADC) controller interface includes a semaphore register (one byte), a
control register (two bytes) and a data/status register (four bytes).
The ADC controller registers are defined in Table 7.
TABLE 7: ADC CONTROLLER REGISTERS DESCRIPTION
FUNCTION
ADDRESS
C200H
BIT
7
REMARKS
1 = Enable
Controller Clock Enable
0 =Disable
0xFF = Reset
Read/Write
Read only
Controller RESET
Semaphore Register
Data Registers
C406H
All
0-1
All
E100H
E103H to E106H
E101H to E102H
Control Register
All
Write only
Semaphore Register
The semaphore register bit definitions are shown in Table 8.
TABLE 8: ADC CONTROLLER INTERFACE SEMAPHORE REGISTER BIT DEFINITIONS
ADDRESS
E100H
BIT 7 … BIT 2
Don’t Care
BIT 1
Tx Semaphore
BIT 0 (LSB)
Rx Semaphore
(Controller to ADC Converter) (ADC Converter to Controller)
Control Register
The control register bit definitions and its functions and are given in Table 9, page 28.
Revision B
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CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
.
TABLE 9: ADC CONTROLLER INTERFACE CONTROL REGISTER BIT FUNCTIONS
BYTE # ADDRESS BIT
FUNCTION
SETTINGS
0 = Disable
1 = Enable
1
E101H
0
Interrupt Enable
(LSB)
1-7 Don’t Care
Don’t Care
00 = 20 Hz (default) & F.S=100,000 Counts
01 = 10 Hz & F.S. = 200,000 Counts
10 = 10 Hz& F.S. = 100,000 Counts
11 = 5 Hz& F.S. = 200,000 Counts
2
E102H
0-1 Sample Rate
(bit 0 –
LSB)
000 = 0.50
001 = 0.75
010 = 1.00
011 = 1.50
100 = 2.00
2-4 Gain
111 = Power Down
Power Down
0 = Main (default) channel
1 = Secondary channel
5
ADC Channel
6
7
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Status/Data Registers
The data register bit definitions are shown in Table 10. The bit functions are described
in Table 11.
TABLE 10: ADC CONTROLLER INTERFACE DATA REGISTER BIT DEFINITIONS
BYTE # ADDRESS BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
1
2
3
4
E103H
E104H
E105H
E106H
D7
D6
D5
D13
SR1
0
D4
D12
SR0
0
D3
D11
D19
0
D2
D10
D18
0
D1
D9
D0
D8
D15
D14
G1/PD1 G0/PD0
D17
CH
D16
0
0
G2/PD2
TABLE 11: ADC CONTROLLER INTERFACE DATA REGISTER BIT FUNCTIONS
BIT FUNCTION
Di
ADC Reading Data
D0 = LSB
D19 = MSB
SRi
Sample Rate
Gi/PDi
CH
Gain/Power Down
Active ADC Channel
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Operation
Initialization:
To enable the ADC controller interface:
1. Enable the ADC controller interface clock source in Clock Enable register C200H:
Set C200H, Bit 7 to 1.
2. Reset the ADC controller interface:
Write FF to register C406H.
3. Set the Configuration registers (CFR) address for ADC controller interface function:
CFR address C10CH = 1FH.
4. Enable interrupt:
Set E101H, Bit 0 to 1.
5. Check the semaphore byte at address E100H.
If Receive semaphore bit at E100H is Ready (Bit 0 = 0), signaling the CPU that the
ADC controller can receive data, the CPU performs the following operations:
a. Sets the Transmit semaphore bit at E100H to Busy (Bit 1 = 1) to prevent
transmission of data from the ADC controller.
b. Programs the control register E101–E102H of the ADC controller to initialize
controller operation.
Normal operation:
6. After the ADC controller has been initialized, the following operations are
performed:
a. The CPU resets the Transmit semaphore bit at E100H to Ready (Bit 1 = 0) to
signal the ADC controller that it can now transmit data.
b. The ADC controller sets the Receive semaphore bit at E100H to Busy
(Bit 0 = 1) to prevent further data transmission to the controller.
c. The ADC controller sends ADC converter data to data registers at E103H to
E106H.
7. After sending the data of registers E103H to E106H, the ADC controller resets the
Receive semaphore bit at E100H to Ready (Bit 0 = 0), signaling the CPU that the
controller can now receive new data.
One ADC controller operation cycle is now complete.
Steps 6 through 7 are repeated cyclically.
The ADC internal counts output is dependent upon the input signal, the gain and the
operation mode setting. Table 12 defines the relation between the internal counts output
of the zero signal input of the full-scale signal and the ADC settings.
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
.
TABLE 12: ADC OUTPUT COUNTS VS. ADC SETTINGS
GAIN SAMPLE
ADC
ADC OUTPUT AT
ZERO SIGNAL
INPUT
MAXIMUM
FULL-SCALE
INPUT
ADC OUTPUT
(COUNTS)
RATE * RESOLUTION
MODE *
(IN COUNTS)
(HZ)
(COUNTS)
153,200
153,200
306,400
306,400
153,200
153,200
306,400
306,400
153,200
153,200
306,400
306,400
153,200
153,200
306,400
306,400
153,200
153,200
306,400
306,400
(MILLI-VOLTS)
0.5
0.75
1.0
20
10
10
5
100,000
100,000
200,000
200,000
100,000
100,000
200,000
200,000
100,000
100,000
200,000
200,000
100,000
100,000
200,000
200,000
100,000
100,000
200,000
200,000
10
10
10
10
10
10
10
10
10
10
10
10
6.6
6.6
6.6
6.6
5
205,000
205,000
412,000
412,000
231,000
231,000
464,000
464,000
257,000
257,000
514,000
514,000
257,000
257,000
514,000
514,000
257,000
257,000
514,000
514,000
20
10
10
5
20
10
10
5
1.5
20
10
10
5
2.0
20
10
10
5
5
5
5
* ADC Resolution mode is defined in Table 9, Register E102H, bits 0-1 – Sample Rate.
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
KEYBOARD CONTROLLER
Features
• Supports up to 64 keys (8×8)
Functional Description
Keyboard Controller Matrix Configuration
• Programmable anti-bounce mechanism
The keyboard matrix configuration showing the
8 × 8 matrix is given in Figure 12. The key
values at each junction are in hexadecimal.
(4-18 ms)
• Automatic key matrix scanning
• Automatically detects excessively long or
constant key depression
• When Interrupt mode enabled, generates an
interrupt when any key is pressed or released
K I N 0
K I N 1
0 1
K I N 2
0 2
K I N 3
0 3
K I N 4
0 4
K I N 5
0 5
K I N 6
0 6
K I N 7
0 7
*
K O U T 0
K O U T 1
K O U T 2
K O U T 3
K O U T 4
K O U T 5
K O U T 6
K O U T 7
0 0
1 0
2 0
3 0
4 0
5 0
6 0
7 0
1 1
2 1
3 1
4 1
5 1
6 1
7 1
1 2
2 2
3 2
4 2
5 2
6 2
7 2
1 3
2 3
3 3
4 3
5 3
6 3
7 3
1 4
2 4
3 4
4 4
5 4
6 4
7 4
1 5
2 5
3 5
4 5
5 5
6 5
1 6
2 6
3 6
4 6
5 6
6 6
7 6
1 7
2 7
3 7
4 7
5 7
6 7
7 7
7 5
*
Key values are in hexadecimal.
FIGURE 12: KEYBOARD MATRIX CONFIGURATION
Revision B
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CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Controller Registers
Keyboard controller interface includes a control register (one byte) and a data/status
register (two bytes).
The Keyboard controller registers are defined in Table 13.
TABLE 13: KEYBOARD CONTROLLER REGISTERS DESCRIPTION
FUNCTION
ADDRESS
C200H
BIT
2
REMARKS
Controller Clock Enable
1= Enable
0= Disable
0xFF = Reset
Read only
Write only
C400H
Controller RESET
Data Registers
Control Register
All
All
All
F100H to F101H
F100H
Registers Description
Control Register
The keyboard control register bit definitions, functions, and settings are displayed in
Table 14.
TABLE 14: KEYBOARD CONTROLLER CONTROL REGISTER BIT FUNCTIONS
ADDRESS
F100H
BIT
FUNCTION
SETTINGS
000 = 4 ms
001 = 6 ms
010 = 8 ms
011 = 10 ms
100 = 12 ms
101 = 14 ms
110 = 16 ms
111 = 18 ms
0-2
(bit 0 -LSB)
Anti-Bounce Timeout
0 = Enable
3
Interrupt Enable/Disable
Don’t Care
1 = Disable (default)
4-7
Don’t Care
Data Registers
Keyboard data is stored in two 8-bit registers.
The data register bit functions are shown in Table 15.
Revision B
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CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
NOTE
When Control Register Address F101H, bit 7 is set to 1 (Released), key-code value bits 0
to 6 in address F101H are meaningless.
TABLE 15: KEYBOARD CONTROLLER DATA REGISTER BIT DEFINITIONS
BYTE # ADDRESS
BIT 7
X
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
BIT 0 (LSB)
1
F100H
X
X
X
X
X
X
Key Error
0 = Legal
1 = Error
2
F101H
Release Sign
0 = Pressed
1 = Released
D6
D5
D4
D3
D2
D1
D0
Operation
At power on, the keyboard controller is reset and the scanning rate is set to 10 µs.
Initialization:
To enable the keyboard controller:
1. Enable the keyboard controller clock source in Clock Enable register C200H:
Set C200H, Bit 2 to 1.
2. Reset the keyboard controller:
Write FF to register C400H.
3. Set CFR address for keyboard controller function:
CFR addresses C10DH and C10EH = FF (Table 32, page 62).
This causes the following results:
•
Enables keyboard input pins (1 to 5 and 82 to 84) (Table 32; page 62; Table 1,
page 9; Table 2, page 12)
•
Enables keyboard output pins (74 to 81) (Table 32, Table 1, Table 2)
4. Enable keyboard interrupt:
Set F100H, Bit 3 to 0.
5. Set anti-bounce timeout:
Set F100H, Bits 0, 1 and 2, as shown in Table 14.
Normal Operation:
6. Read keyboard key-code value bits, as follows:
•
Read register F100H, Bit 0:
If 0, key-code value is legal.
If 1, key-code value is illegal (Error).
•
•
Read key code from register F101H, bits 0 to 6:
When key pressed, values are valid.
Read F101H, bit 7:
If 0, key pressed and keyboard values (bits 0 to 6) are valid.
If 1, key released and keyboard values are meaningless.
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
LCD CONTROLLER/DRIVER
Features
Functional Description
The SOC-3000 LCD controller/driver interfaces
to LCD (Liquid Crystal Display) with low
multiplex rates.
• Selectable backplane drive configuration,
static or multiplex drive ratios of 1:2, 1:3 or
1:4
• Selectable display bias configuration, static, or
The controller/driver generates drive signals for
static drive mode (no multiplexing) or
1/2 bias or 1/3 bias
• Internal LCD bias generation with voltage-
multiplexed LCDs with multiplex drive ratios of
1:2, 1:3 or 1:4, depending on the number of
backplane outputs. The driver supports up to four
backplanes, each supporting 40 segments.
follower buffers
• Drives up to 40 segments with the capacity to
generate 20 numeric characters
The LCD Controller/Driver block diagram is
shown in Figure 13.
• 20 × 8-bit memory display data
• User-selected LCD voltages
The driver supports numeric, alphanumeric and
dot matrix display configurations. The number of
characters of each type that can be displayed
depends on the number of backplanes and the
number of segments required per character. The
maximum display capacity for each display
configuration is shown in Table 16.
VDD
Backplane
Display Segment Outputs
Outputs
R
–
+
Display Latch
Shift Register
R
R
LCD Voltage
Selector
–
+
V
LCD
LCD Bias
Generator
FIGURE 13: LCD CONTROLLER/DRIVER BLOCK DIAGRAM
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
TABLE 16: MAXIMUM DISPLAY CAPACITY PER DISPLAY CONFIGURATION
NUMBER OF
SEGMENTS OR
SYMBOLS
NUMERIC
BACKPLANES
(7 SEGMENTS)
4
3
2
1
160
120
80
20
15
10
5
40
LCD Bias Generator
The operative LCD voltage is derived from VDD – VLCD (Figure 13). The three resistors
connected in series between VDD and VLCD in the bias generator function as a voltage
divider to produce 1/2 (for the 1:2 multiplex drive ratio) and 1/3 (for the 1:2, 1:3 and 1:4
multiplex drive ratio) biasing voltages. The bias configuration for each of the multiplex
drive ratios is given in Table 17.
For additional information on LCD drivers refer to LCD driver components datasheets
such as Phillips PCF8756.
TABLE 17: LCD BIAS CONFIGURATIONS
MULTIPLEX DRIVE
MODE
# BACKPLANES
# LEVELS
BIAS
CONFIGURATION
Static
1:2
1
2
2
3
4
2
3
4
4
4
Static
1/2
1:2
1/3
1:3
1/3
1:4
1/3
Drive Mode Waveforms
The waveforms for the Static drive mode are given in Figure 14, page 37.
The waveforms for the 1:2 Multiplex Drive Ratio–1/2 Bias are given in
Figure 15, page 38.
The waveforms for the 1:2 Multiplex Drive Ratio–1/3 Bias are given in
Figure 16, page 39.
The waveforms for the 1:3 Multiplex Drive Ratio are given in Figure 17, page 40.
The waveforms for the 1:4 Multiplex Drive Ratio are given in Figure 18, page 41.
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
T Frame
VDD
Backplane 0
VLCD
VDD
Segment n
On
Driver
Waveforms
VLCD
VDD
Segment n+1
Off
VLCD
+ VOPER
Segment On
0V
LCD Segment
Waveforms
On/Off
– VOPER
+ VOPER
0V
Segment Off
– VOPER
FIGURE 14: STATIC DRIVE MODE WAVEFORMS
Revision B
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CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Backplane 0
Backplane 1
Driver
Waveforms
Segment n
Segment n+1
LCD Segment
Waveforms
On/Off
Segment On
Segment Off
FIGURE 15: 1:2 MULTIPLEX DRIVE RATIO–1/2 BIAS WAVEFORMS
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
T Frame
Backplane 0
Backplane 1
Driver
Waveforms
Segment n
Segment n+1
Segment On
LCD Segment
Waveforms
On/Off
Segment Off
FIGURE 16: 1:2 MULTIPLEX DRIVE RATIO–1/3 BIAS WAVEFORMS
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
T Frame
Backplane 0
Backplane 1
Driver
Waveforms
Backplane 2
Segment n
Segment n+1
Segment n+2
Segment On
LCD Segment
Waveforms
On/Off
Segment Off
FIGURE 17: 1:3 MULTIPLEX DRIVE RATIO WAVEFORMS
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
T Frame
Backplane 0
Backplane 1
Backplane 2
Backplane 3
Driver
Waveforms
Segment n
Segment n+1
Segment n+2
Segment n+3
Segment On
LCD Segment
Waveforms
On/Off
Segment Off
FIGURE 18: 1:4 MULTIPLEX DRIVE RATIO WAVEFORMS
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Registers Description
LCD controller /driver command and data are stored in a 21-byte × 8-bit, static display
RAM with one control register and 20 data registers.
The controller registers are defined in Table 18.
TABLE 18: LCD CONTROLLER/DRIVER REGISTERS DESCRIPTION
FUNCTION
ADDRESS
C200H
BIT
0
REMARKS
Controller Clock Enable
1= Enable
0= Disable
0xFF = Reset
Write only
C401H
Controller RESET
Data Registers
Control Register
All
All
All
C801H to C814H
C800H
Read/Write
Control Register
The control-register bit definitions and functions are displayed in Table 19. The Type
definitions are Static and Dynamic: Static bits update only after an external Reset and
first chip select (first command write cycle). Dynamic bits can be updated at any time.
TABLE 19: LCD CONTROLLER CONTROL REGISTER BIT FUNCTIONS
ADDRESS
C800H
BIT
NAME
UPDATE
FUNCTION
SETTINGS
00 = Static (5 seven-segment
0-1 M0 and M1 After Reset
Bits 0 (M0) and 1 (M1) set
the multiplex drive ratio.
Only
digits)
( 0-
01 = 1:2 (10 seven-segment
LSB)
digits)
10 = 1:3 (15 seven-segment
digits)
11 = 1:4 (20 seven-segment
digits)
0 = 1/2
1 = 1/3
2
3
B
E
After Reset
Only
Sets the bias voltage.
0 = Disable
1 = Enable
Anytime
Sets LCD display
operation.
000 = 52 Hz
100 = 62 Hz
4-6 X0 (LSB),
After Reset
Bits 4 (X0), 5 (X1) and 6
(X2) set the refresh clock
frequency.
001 = 104 Hz 101 = 125 Hz
010 = 156 Hz 110 = 178 Hz
011 = 208 Hz 111 = 250 Hz
X1 and X2 Only
0 = Continuous Data Reading
1= Command Only
7
C
Anytime
Sets the command
operating mode.
Revision B
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CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Data Registers
LCD display data is stored in a 20-byte × 8-bit RAM. The number of registers used
depends on the number of digits displayed, 5, 10, 15 or 20. The data register bit
definitions for a 20-digit display, for which the entire RAM is used, are shown in Table
20.
TABLE 20: LCD CONTROLLER DATA REGISTER BIT DEFINITIONS – 20-DIGIT
DISPLAY
Byte #
Address Bit 7
Bit 6
g
Bit 5
Bit 4
e
Bit 3
d
Bit 2
Bit 1
b
Bit 0
a
1
C801H
C802H
…
DP
DP
…
f
c
2
g
f
e
d
c
b
a
…
20
…
g
…
f
…
e
…
d
…
c
…
b
…
a
C814H
DP
For other displays, Data Registers utilization is as follows:
•
•
•
For 15-digit command, write data to C801H to C80FH
For 10-digit command, write data to C801H to C80AH
For 5-digit command, write data to C801H to C805H
Each byte in the register defines a seven-segment digit and decimal point (DP). Each bit
of a register address corresponds to a segment of each digit, as shown in Figure 19.
When the bit is set to 1, it is on. When it is set to 0, it is off. Figure 19 also shows the
backplane outputs per LCD digit for each multiplex drive ratio.
BP 0
BP 0
BP 0
BP 1
b
BP 0
a
g
a
g
a
g
a
g
b
c
b
b
c
f
f
f
f
BP 1
BP 2
BP 1
e
BP 2
e
e
e
c
c
d
DP
d
DP
d
DP
d
DP
BP 3
Static
1:3 Multiplex
1:4 Multiplex
1:2 Multiplex
FIGURE 19: BACKPLANE OUTPUTS PER LCD DIGIT
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Operation
Initialization:
At power on, the LCD controller performs the following operations:
1. Resets its backplane and segment outputs to VDD.
After power on, the actual operating LCD voltage VOPER is set according to the
multiplexing drive mode and the bias generator.
2. After reset, the LCD pins are routed to the Output function.
To enable the LCD controller:
1. Enable the LCD controller clock source in Clock Enable register C200H:
Set C200H, Bit 0 to 1.
2. Reset the LCD controller:
Write FF to register C401H.
3. Set CFR addresses for LCD controller function:
CFR addresses C101H to C10BH = 00H (Table 32, page 62).
This enables LCD controller output pins (18 to 61) (Table 32, page 62; Table 1,
page 9).
Normal Operation:
4. Write data to LCD data registers C801H to C814H.
5. Set Write command in LCD control register C800H.
6. Repeat steps 4 and 5 for new data.
The trigger for sending the data out to the display interface is:
Programming the control register at address C800H AND writing data to the LCD data
registers (C801H to C814H).
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
LED PARALLEL DISPLAY CONTROLLER
Features
Functional Description
• Supports up to 21 digits (7 segments +
The LED display block diagram showing the
relationship between the 21-digit LED display,
the SOC-3000 LED controller and the data
register is given in Figure 20.
Decimal Point)
• Power-save by LED refresh mechanism
• Programmable-display data registers
The LED Controller timing diagram is shown in
Figure 21.
• Supports common-anode, seven-segment LED
D101
D102
D103
D104
a
D105
D106
D107
Reg. Address
a
a
a
a
a
a
Seg a–1
Seg b–1
Seg c–1
Seg d–1
Seg e–1
Seg f–1
Seg g–1
DP–1
b
c
b
c
b
c
b
c
b
c
b
c
b
c
f
f
f
f
f
f
f
g
d
g
d
g
d
g
d
g
d
g
d
g
d
e
e
e
e
e
e
e
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DIG1
D108
a
DIG2
D109
DIG3
D10A
DIG4
D10B
DIG5
D10C
DIG6
D10D
DIG7
D10E
Reg. Address
a
a
a
a
a
a
Seg a–2
Seg b–2
Seg c–2
Seg d–2
Seg e–2
Seg f–2
Seg g–2
DP–2
b
b
c
b
c
b
c
b
c
b
c
b
c
f
f
f
f
f
f
f
g
g
d
g
d
g
d
g
d
g
d
g
d
e
e
e
e
e
e
e
c
d
DIG1
D10F
a
DIG2
D110
DIG3
D111
DIG4
D112
DIG5
D113
DIG6
D114
DIG7
D115
Reg. Address
a
a
a
a
a
a
Seg a–3
Seg b–3
Seg c–3
Seg d–3
Seg e–3
Seg f–3
Seg g–3
DP–3
b
b
c
b
c
b
c
b
c
b
c
b
c
f
f
f
f
f
f
f
g
g
d
g
d
g
d
g
d
g
d
g
d
e
e
e
e
e
e
e
c
d
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
SOC–3000
FIGURE 20: LED PARALLEL DISPLAY CONTROLLER BLOCK DIAGRAM
Revision B
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July, 2002
CybraTech (2000) Ltd.
SEGMENT
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
500 µs
500 µs
30 µs
30 µs
DIG 1
440 µs
60 µs
DIG 2
440 µs
FIGURE 21: LED PARALLEL DISPLAY CONTROLLER TIMING DIAGRAM
Registers Description
The LED controller registers are defined in Table 21.
TABLE 21: LED PARALLEL DISPLAY CONTROLLER DRIVER REGISTERS
DESCRIPTION
FUNCTION
ADDRESS
C200H
BIT
1
REMARK
Controller Clock Enable
1= Enable
0= Disable
0xFF = Reset
Read only
Write only
Controller RESET
Semaphore Bit
Data Registers
C402H
All
0
D100H
D101H to D115H
All
LED display data is stored in a 21-byte × 8-bit static display RAM. The display RAM
has one Read-only semaphore register containing the semaphore byte and 21 Write-only
data registers.
All 22 bytes (one semaphore byte and 21 data bytes) must be written before any
new data is applied.
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Semaphore Register
The Semaphore register bit definitions are shown in Table 22.
TABLE 22: LED PARALLEL DISPLAY CONTROLLER SEMAPHORE REGISTER BIT
DEFINITIONS
ADDRESS BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
D100H
X
X
X
X
X
X
X
E
Only Bit 0, the Semaphore bit, is active in the LED Controller control register
(Table 23). The semaphore is used to synchronize the access to the control registers.
TABLE 23: LED PARALLEL DISPLAY CONTROLLER SEMAPHORE REGISTER BIT
FUNCTIONS
BIT
0
NAME
E
TYPE
FUNCTION
SETTINGS
0 = Ready
1 = Busy
Read-only
Semaphore bit
Data Registers
LED data is stored in a 21-byte × 8-bit RAM.
The data is organized in three groups of seven digits, as follows:
•
•
•
Group 1: D101H to D107H - multiplexed on SEC A1 to DP1 Pins.
Group 2: D108H to D10EH - multiplexed on SEC A2 to DP2 Pins.
Group 3: D10FH to D115H - multiplexed on SEC A3 to DP3 Pins.
The data register bit definitions for a 21-digit display are shown in Table 24.
TABLE 24: LED PARALLEL CONTROLLER DATA REGISTER BIT DEFINITIONS
GROUP
1
BYTE #
ADDRESS
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(LSB)
1
D101H
DP
DP
DP
DP
DP
DP
DP
DP
DP
g
g
g
g
g
g
g
g
g
f
f
f
f
f
f
f
f
f
e
e
e
e
e
e
e
e
e
d
d
d
d
d
d
d
d
d
c
c
c
c
c
c
c
c
c
b
b
b
b
b
b
b
b
b
a
a
a
a
a
a
a
a
a
2
3 to 7
8
D102H
D103H to D107H
D108H
2
3
9
D109H
10 to 14 D10AH to D10EH
15
16
D10FH
D110H
17 to 21 D111H to D115H
Note:
The trigger for sending the data to the display hardware is writing data to address D115H.
Revision B Page 47 July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Operation
At power-on or reset the LED Parallel display controller is disabled.
Initialization:
To enable the LED Parallel display controller:
1. Enable the controller clock source in Clock Enable register C200H:
Set C200H, Bit 1 to 1.
2. Reset the controller:
Write FF to register C402H.
3. Set CFR addresses for LED Parallel display controller function:
CFR addresses C103H to C109H = 55H,
CFR address C10A = 15H (Table 32, page 62).
These result in the following operations:
•
Enable LED parallel display controller output pins (22 to 52) (Table 32, page
62; Table 2, page 12).
•
Check semaphore bit in LED parallel display controller semaphore register at
address D100H.
Normal Operation:
4. If semaphore bit is Ready (Bit 0 set to 0), write data to Data register addresses
D101H to D115H.
5. Set Write command:
Write 01H to D100H.
The trigger for sending the data out to the display serial interface is:
•
Programming the semaphore register at address D100H AND writing data to the 21
data registers (D101H to D115H).
OR
•
Programming the semaphore register at D100H AND writing data to the last data
register at D115H.
As soon as the controller starts to send the data, it sets the semaphore bit to 1, indicating
that it is busy.
When the controller finishes data output, it resets the semaphore bit to 0, indicating that
it is available for a new operation.
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
LED SERIAL INTERFACE DISPLAY CONTROLLER
Features
Functional Description
• Supports up to 24 digits
The LED Serial Interface display comprises three
groups of eight digits. The controller diagram
showing the division of the 24-byte register into
three eight-byte groups and the operation cycle is
given in Figure 22.
The LED Serial Interface Display Controller
timing diagram is shown in Figure 23. The clock
rate is 2 MHz.
• Serial interface
• Programmable control-signal polarity
• Programmable data registers
• Supports common-anode, seven-segment LED
Digit 8
Digit 7
Digit 6
Digit 5
Digit 4
a
Digit 3
Digit 2
Digit 1
Group 1
a
a
a
a
a
a
a
Seg a
Seg b
Seg c
Seg d
Seg e
Seg f
Seg g
DP
b
c
b
c
b
c
b
c
b
c
b
c
b
c
b
c
f
f
f
f
f
f
f
f
g
d
g
d
g
d
g
d
g
d
g
d
g
d
g
d
e
e
e
e
e
e
e
e
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
Digit 8
Digit 7
Digit 6
Digit 5
Digit 4
a
Digit 3
Digit 2
Digit 1
Group 2
a
a
a
a
a
a
a
Seg a
Seg b
Seg c
Seg d
Seg e
Seg f
Seg g
DP
b
c
b
c
b
c
b
c
b
b
c
b
c
b
c
f
f
f
f
f
f
f
f
g
d
g
d
g
d
g
d
g
d
g
d
g
d
g
d
e
e
e
e
e
e
e
e
c
DP
DP
Digit 8
Digit 7
Digit 6
Digit 5
Digit 4
a
Digit 3
Digit 2
Digit 1
Group 3
a
a
a
a
a
a
a
Seg a
Seg b
Seg c
Seg d
Seg e
Seg f
Seg g
DP
b
c
b
c
b
c
b
c
b
c
b
c
b
c
b
c
f
f
f
f
f
f
f
f
g
d
g
d
g
d
g
d
g
d
g
d
g
d
g
d
e
e
e
e
e
e
e
e
DP
DP
0
0
0
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Cycle 1
Digit 1
Group 1
Group 2
Group 3
1
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
Cycle 8
The controller transmits cycles 1 to 8 continuously.
FIGURE 22: LED SERIAL INTERFACE DISPLAY BLOCK DIAGRAM
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
20 µs
BLANK
/
BLANK
20 µs
t = 400 µs
STROBE
/
STROBE
20 µs
t1 = 8µs
CLOCK
/
CLOCK
DATA
FIGURE 23: LED SERIAL INTERFACE CONTROLLER TIMING DIAGRAM
Registers Description
The LED Serial controller registers description is given in Table 25.
TABLE 25: LED SERIAL CONTROLLER DRIVER REGISTERS DESCRIPTION
FUNCTION
ADDRESS
C200H
BIT
5
REMARKS
Controller Clock Enable
1= Enable
0= Disable
Controller RESET
C403H
D201H
All
0xFF = Reset
Read only
Semaphore register
Data Registers
Group 1
Group 2
D201H to D208H
D209H to D210H
D211H to D218H
Write Only
Write Only
Write Only
Group 3
Control Register
D200H
Read/Write
LED data is stored in a 24-byte × 8-bit static display RAM. The data registers are
divided into three groups, each group containing eight bytes with the segment data for
eight digits. Thus, the LED display can be formatted to display eight, 16 or 24 digits.
The display RAM has one Read/Write control register containing the Command byte and
a Read-only semaphore byte that informs the system if the display is Busy or Ready to
initiate writing of LED data. The semaphore byte address also serves as first address of
the Write-only data register.
The trigger for sending the data out to the display serial interface is programming the
control register at address D200H. As soon as the controller starts to send data, it sets
the semaphore byte to FFH, indicating that it is busy.
The data is sent serially, Group 1 Digit 8 (left-most digit of the first group) most-
significant bit (MSB) first, and continuously until Group 3 Digit 1 least-significant bit
(LSB) last.
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
When the controller has finished data output, it resets the semaphore byte to 0, indicating
that it is available for a new operation.
Control Register
The definitions and functions of the control-register Command-byte bits are displayed in
Table 26.
TABLE 26: LED SERIAL INTERFACE DISPLAY CONTROL REGISTER BIT FUNCTIONS
ADDRESS BIT
NAME
FUNCTION
Command bit
SETTINGS
0 = Command Only
1 = Command + Data
D200H
0
C
X
(LSB)
1
2
N/A
Don’t Care
0 = Negative Logic
1 = Positive Logic
Blank Polarity
Strobe Polarity
Clock Polarity
E
Sets the Blank polarity.
0 = Negative Logic
1 = Positive Logic
3
4
5
6
7
Sets the Strobe polarity.
0 = Negative Logic
1 = Positive Logic
Sets the Clock polarity.
0 = Disable Display
1 = Enable Display
Enables and disables the display.
0 = Close communication
1 = Open communication
Block
Opens communication or blocks
the hardware communication lines.
N/A
N/A
Don’t Care
Semaphore Register
The semaphore byte is located at address D201H, which is the first address of the
Write-only data register. This address is Read-only for the semaphore byte. The
semaphore byte bit definitions are identical. The settings are:
•
Controller is Busy: Bits 0 to 7 set to 1 (FFH).
Controller is Ready: Bits 0 to 7 set to 0 (00H).
•
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Data Registers
The display data is stored in a 24-byte × 8-bit RAM area.
The data register bit definitions for a 21-digit display are shown in Table 27. The
registers are Write-only.
TABLE 27: LED SERIAL INTERFACE DISPLAY DATA REGISTER BIT DEFINITIONS
GROUP DIGIT BYTE ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
#
1
#
(MSB)
(LSB)
#
1
2
3
4
5
6
7
8
9
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
8
8
8
8
8
8
8
D201H
D202H
D203H
D204H
D205H
D206H
D207H
D208H
D209H
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
g
g
g
g
g
g
g
g
g
g
g
g
g
g
g
g
g
g
g
g
g
g
g
g
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
A
a
a
a
a
a
a
a
2
10 D20AH
11 D20BH
12 D20CH
13 D20DH
14 D20EH
15 D20FH
16 D210H
17 D211H
18 D212H
19 D213H
20 D214H
21 D215H
22 D216H
23 D217H
24 D218H
3
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Operation
At power-on or reset the LED Serial Interface display controller is disabled.
Initialization:
To enable the LED Serial Interface display controller:
1. Enable the controller clock source in Clock Enable register C200H:
Set C200H, Bit 5 to 1.
2. Reset the controller:
Write FF to register C403H.
3. Check CFR address for LED serial Interface display controller function:
CFR address C101H = AA (Table 32, page 62).
This results in the following operations:
•
Enables serial controller output pins (58 to 61) (Table 32, page 62)
Check semaphore byte at address D201H.
•
Normal Operation:
4. If semaphore byte is Ready (Bits 0 to 7 set to 0), write data to Data register
addresses D201H to D218H.
5. Set Write command at the controller Control register address D200H.
6. Repeat steps 4 and 5 for new data.
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
PROGRAMMABLE FREQUENCY CONTROLLER
Features
Functional Description
Dividing the 16-MHz frequency source according
to the control register setting generates the CPU
clock frequency.
The CPU clock can be set to 16, 8, 4, 2, 1 or
0.5 MHz.
• Programmable CPU clock frequency: 16, 8, 4,
2, 1 or 0.5 MHz
• Driven by a 16-MHz resonator or crystal
oscillator
Functions
• Generates independent clocks for the CPU and
controllers (ADC converter, display,
keyboard, watchdog timer, etc.)
Switching CPU frequency:
• To switch from the 16-MHz frequency to any
other frequency, program the frequency-
controller control register as shown in
Table 28.
• To switch from any frequency (other than
16 MHz) to another frequency, first switch to
16 MHz and then switch to the desired
frequency.
Clock Generator Block Diagram
The clock generator block diagram is presented in
Figure 24.
16 MHz (Default)
16 MHz
Clock
8 MHz
4 MHz
1/2
1/2
2 MHz
1/2
1 MHz
1/2
0.5 MHz
1/2
FIGURE 24: CLOCK GENERATOR BLOCK DIAGRAM
Revision B
Page 55
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Operation
At Power on or Reset, the CPU frequency clock output is set to 16 MHz.
The clocks for the controllers is fixed and derived directly from the external frequency
source.
The Frequency controller setting derives the CPU clock, as defined in Table 28.
Control Registers Description
The clock frequency is programmed from a single 8-bit control register.
The address of the clock frequency control register is E800H.
The bit settings at E800H that define the clock frequency are given in Table 28.
TABLE 28: CLOCK FREQUENCY CONTROL REGISTER BIT SETTINGS
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(LSB)
CPU CLOCK
E800H
Don’t Care
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
0.5 MHz
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
WATCHDOG TIMER
Functions
Functional Description
The purpose of the watchdog timer is to
generate a CPU reset at specified intervals. If
the SOC-3000 software does not interrupt the
watchdog cycle and instead enters an
The operating parameters of the watchdog
timer are presented in Table 29.
erroneous state, the watchdog time carries out
its CPU reset one second after the software
was supposed to make its interrupt. The
erroneous state may be due to a programming
error. The watchdog may be disabled or re-
triggered via its control register.
TABLE 29: WATCHDOG TIMER OPERATING PARAMETERS
PARAMETER VALUE
Time Constant
Trigger
1 second
By the control register (WDI)
By the control register (ENWD)
Disabled
Enable/Disable
Power Up Mode
Operation
The application software controls the watchdog operation. It is automatically disabled in
the In-circuit Emulator (ICE) mode and after power-up or reset.
The application software should activate the watchdog as soon as it starts normal
operation after power-on or reset conditions.
The watchdog timer should be periodically re-triggered during normal operation, before
the timer expires. Expiration of the watchdog timer resets the CPU.
If required, disabling the watchdog timer clock input can disable the watchdog.
Table 30 describes the operation of the watchdog timer.
TABLE 30: WATCHDOG TIMER COMMAND SEQUENCE
#
COMMAND
ADDRESS
BIT
3
SETTING
1 Enable Watchdog
C200H
1= Enable
0= Disable
2 Re-trigger Timer
F800H
C200H
all
3
FFH
0
3 Disable Watchdog
Control Registers Description
Setting the Clock Enable register (C200H), bit 3 to 1 enables the watchdog timer.
Setting the Clock Enable register (C200H), bit 3 to 0 disables the watchdog timer.
Writing FFH to address F800H re-triggers the watchdog.
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
LOW VOLTAGE DETECTOR
The low voltage detector is a supervisory circuit in which the Power Fail Input (Vdet) is
compared to an internal 2.23 V reference (Figure 25). The comparator output goes low
when the voltage at Vdet is less than or equal to 2.23 V and Bit 1 of register E400H
equals 0.
Vdet is usually driven by an external voltage divider, which senses the unregulated DC
input to the system 5V regulator. The voltage divider ratio can be chosen such that the
voltage at Vdet falls below 2.23 V several milliseconds before the +5V supply falls below
4.75V. INT0 is normally used to interrupt the microprocessor so that data can be stored
in non-volatile memory before VCC falls below 4.75 V and the RESET output goes low.
The Power Fail Comparator output returns to High when Vdet>2.27V.
V
VCC
DC Unreg.
in
REG
Recommended
SOC-3000
Values for Resistors
Vdet
Power Fail Comparator
+
1% 133K R
1
INTØ
1% 100K R
2
INTØ
INTØ
5.19V (Typ.)
5.3V (Typ.)
–
INTØ goes low if Vdet < 2.23V.
FIGURE 25: LOW VOLTAGE DETECTOR
Interrupt Register
The address of the power-supply interrupt register is E400H (Read/Write).
The bit settings at E400H that define the power failure interrupt and flag are given in
Table 31.
TABLE 31: POWER-FAILURE INTERRUPT REGISTER BIT SETTINGS
ADDRESS BIT BIT BIT BIT BIT BIT
BIT 1
BIT 0 (LSB)
7
6
5
4
3
2
POWER FAIL FLAG INTERRUPT ENABLE
0 = If VDET < VREF
1 = Normal
0 = Enabled
1 = Disabled
E400H
Don’t Care
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
CONFIGURATION REGISTERS (CFR)
Programming the configuration registers (CFR) in the CPU sets the SOC-3000 pin functions.
The CFR registers include control and configuration registers that provide the interface
between the CPU and the other on-chip peripherals, such as the keyboard, LED and LCD
controllers and input/output ports. Each peripheral operates as designated in the CFR
registers, where each register may be programmed to perform alternative functions. (See
“Examples of Pin Configuration Programming”, on page 85).
The complete CFR-register bit assignment for all peripherals and input/output and
corresponding PLCC-84 pins are given on the following pages in Table 32.
Revision B
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July, 2002
CybraTech (2000) Ltd.
Technical Specification
NOTES
SOC-3000/i Scale-On-Chip ASIC
BIT SETTINGS PER FUNCTION
TABLE 32: CFR BIT ASSIGNMENT
PLCC-84 REG BIT
PIN
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
ADD.
C101H
7-6 00=LCD Display S40
5-4 00=LCD Display S39
3-2 00=LCD Display S38
1-0 00=LCD Display S37
10=LED-SI-BLANK
11=OUT 13.3 SI = Serial Interface
10=LED-SI- STROBE
10=LED-SI- STROBE
10=LED-SI- CLK
11=OUT 13.2
11=OUT 13.1
11=OUT 13.0 CLK = Clock
C102H
7
6
0=LCD Display S36
0=LCD Display S35
1=OUT 12.4
1=OUT 12.3
5-4 00=LCD Display S34
3-2 00=LCD Display S33
1-0 00=LCD Display S32
7-6 00=LCD Display S31
5-4 00=LCD Display S30
3-2 00=LCD Display S29
1-0 00=LCD Display S28
7-6 00=LCD Display S27
5-4 00=LCD Display S26
3-2 00=LCD Display S25
1-0 00=LCD Display S24
7-6 00=LCD Display S23
5-4 00=LCD Display S22
3-2 00=LCD Display S21
1-0 00=LCD Display S20
7-6 00=LCD Display S19
5-4 00=LCD Display S18
10=OUT 12.2
10=OUT 12.1
10=OUT 12.0
10=OUT 11.3
10=OUT 11.2
10=OUT 11.1
10=OUT 11.0
10=OUT 10.0
C103H
C104H
C105H
C106H
01=LED Display DIG 7
01=LED Display DIG 6
01=LED Display DIG 5
01=LED Display DIG 4
01=LED Display DIG 3
01=LED Display DIG 2
01=LED Display DIG 1
01=LED Display SEG DP3
01=LED Display SEG G3
01=LED Display SEG F3
01=LED Display SEG E3
01=LED Display SEG D3
01=LED Display SEG C3
01=LED Display SEG B3
DIG = Digit
SEG = Segment
DP = Decimal Point
10=OUT 9.2
Revision B
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July, 2002
CybraTech (2000) Ltd.
PLCC-84 REG BIT
Technical Specification
NOTES
SOC-3000/i Scale-On-Chip ASIC
BIT SETTINGS PER FUNCTION
PIN
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
ADD.
3-2 00=LCD Display S17
1-0 00=LCD Display S16
7-6 00=LCD Display S15
5-4 00=LCD Display S14
3-2 00=LCD Display S13
1-0 00=LCD Display S12
7-6 00=LCD Display S11
5-4 00=LCD Display S10
3-2 00=LCD Display S9
1-0 00=LCD Display S8
7-6 00=LCD Display S7
5-4 00=LCD Display S6
3-2 00=LCD Display S5
1-0 00=LCD Display S4
01=LED Display SEG A3
01=LED Display SEG DP2
01=LED Display SEG G2
01=LED Display SEG F2
01=LED Display SEG E2
01=LED Display SEG D2
01=LED Display SEG C2
01=LED Display SEG B2
01=LED Display SEG A2
01=LED Display SEG DP1
01=LED Display SEG G1
01=LED Display SEG F1
01=LED Display SEG E1
01=LED Display SEG D1
01=LED Display SEG C1
01=LED Display SEG B1
01=LED Display SEG A1
10=OUT 9.1
10=OUT 9.0
C107H
11=OUT 8.3
11=OUT 8.2
10=OUT 8.1
11=OUT 8.0
11=OUT 7.3
11=OUT 7.2
11=OUT 7.1
11=OUT 7.0
11=OUT 6.3
C108H
C109H
10=OUT 6.2
10=OUT 6.1
10=OUT 6.0
10=OUT 5.2
10=OUT 5.1
10=OUT 5.0
C10AH 5-4 00=LCD Display S3
3-2 00=LCD Display S2
1-0 00=LCD Display S1
Revision B
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July, 2002
CybraTech (2000) Ltd.
PLCC-84 REG BIT
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
BIT SETTINGS PER FUNCTION
10=OUT 4.3
NOTES
PIN
21
20
19
18
-
ADD.
C10BH 6-5 00=BP4
4-3 00=BP3
BP = Backplane
01=VPP
10=OUT 4.2
2
0=BP2
1-0 00=BP1
C10CH 7-0 FFH
C10DH
1=OUT 4.1
10=OUT 4.0
Must be always 0xFF
KIN = Keyboard In
I.O = Input/Output
5
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0=I.O 15.7
0=I.O 15.6
0=I.O 15.5
0=I.O 15.4
0=I.O 15.3
0=I.O 15.2
0=I.O 15.1
0=I.O 15.0
0=I.O 14.7
0=I.O 14.6
0=I.O 14.5
0=I.O 14.4
0=I.O 14.3
0=I.O 14.2
0=I.O 14.1
0=I.O 14.0
1=KIN0
4
1=KIN1
3
1=KIN2
2
1=KIN3
1
1=KIN4
84
83
82
81
80
79
78
77
76
75
74
1=KIN5
1=KIN6
1=KIN7
C10EH
1=KOUT0
1=KOUT1
1=KOUT2
1=KOUT3
1=KOUT4
1=KOUT5
1=KOUT6
1=KOUT7
KOUT = Keyboard Out
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Technical Specification
SOC-3000/i Scale-On-Chip ASIC
SPECIAL FUNCTION REGISTERS (SFR)
The SOC-3000/i includes Special Function Registers (SFR) that enable the device hardware
controllers and reset them. Each controller description details its specific SFR operation.
This section details all the SFR registers and functions. All these registers are mapped as
XDATA memory area.
Global Configuration Register
Register 0C100H is used as a general enable/disable of pin allocation to all the hardware
controllers in the SOC-3000/i. Upon power-up or reset this register is cleared, disabling all
the hardware controllers. Writing 0xFF to the register activates the allocation of pins to
hardware controller, as defined by programming the CFR registers.
TABLE 33: GLOBAL CFR REGISTER
ADDRESS
C100H
FUNCTION
REMARKS
0x00 – Enable
0xFF - Disable
Enable / Disable pin allocation
Operation
1. Upon power-up or reset, the Global CFR register is set, disabling all pin allocation to the
hardware controllers.
2. Initialize the CFR registers according to the required hardware configuration as described in
section “
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SOC-3000/i Scale-On-Chip ASIC
Configuration Registers (CFR)” page 61.
3. Initialize the hardware controllers.
4. Enable the Global CFR Register: Write 0x00 to address C100H.
Controllers Clock Enable Register
Register C200H controls the clock source to the hardware controllers in the SOC-3000/i.
Each controller operation may be disabled by inhibiting its clock.
TABLE 34: CLOCK ENABLE REGISTER
ADDRESS BIT 7
BIT 6
0
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
PLED
BIT 0
(LSB)
C200H
ADC
SLED
0
WDT
KBD
LCD
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SOC-3000/i Scale-On-Chip ASIC
TABLE 35: CONTROLLERS CLOCK ENABLE REGISTER BIT FUNCTIONS
BIT
NAME
LCD
TYPE
FUNCTION
SETTINGS
0 = Disable
1 = Enable
0
Read-Write Enable LCD display controller clock
(LSB)
1
2
3
PLED
KBD
Read-Write Enable parallel LED display controller 0 = Disable
clock
1 = Enable
Read-Write Enable keyboard controller clock
0 = Disable
1 = Enable
WDT
Read-Write Enable watch-dog timer clock
0 = Disable
1 = Enable
4
5
-
Read-Write None. Set always to 0.
Always 0.
SLED
Read-Write Enables serial LED display controller
0 = Disable
1 = Enable
6
7
-
Read-Write None. Set always to 0.
Always 0.
AD
Read-Write Enables ADC controller clock
0 = Disable
1 = Enable
Controllers RESET Registers
The SFRs listed in Table 36 provides the mechanism to reset the hardware controllers of the
SOC-3000/i.
TABLE 36: CONTROLLERS RESET REGISTER
ADDRESS
C400H
TYPE
FUNCTION
SETTINGS
0xFF = Reset
0xFF = Reset
Write only Keyboard controller reset
Write only LCD display controller reset
C401H
C402H
Write only Parallel LED display controller reset 0xFF = Reset
C403H
Write only Serial LED display controller reset
Write only ADC controller reset
0xFF = Reset
0xFF = Reset
C406H
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SOC-3000/i Scale-On-Chip ASIC
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Technical Specification
SOC-3000/i Scale-On-Chip ASIC
I/O OPERATION
I/O operation is determined by the configuration registers (CFR) programming. The I/O
ports are composed of two groups:
•
•
Byte-Oriented Output Ports –
Data written to the port is byte oriented (writing FFH to the port will set it to HIGH, and
writing 00H to the port will set it to LOW).
Bit-Oriented Input/Output (I/O) Ports –
Data written to the port is byte oriented (FFH–to set the port, 00H–to reset the port).
Data read from the port is bit-oriented (only the port allocated bit is set/reset).
Table 44, the I/O ports groups, addresses and corresponding PLCC-84 pins are described in
Table 37 and Table 38.
TABLE 37: BIT-ORIENTED I/O PORTS ADDRESSES, PIN AND BIT ASSIGNMENT
PLCC-84 PIN I/O PORT NAME
PORT
BIT
ADDRESS ASSIGNMENT
(LSB)
x
5
I.O 15.7
I.O 15.6
I.O 15.5
I.O 15.4
I.O 15.3
I.O 15.2
I.O 15.1
I.O 15.0
I.O 14.7
I.O 14.6
I.O 14.5
I.O 14.4
I.O 14.3
I.O 14.2
I.O 14.1
I.O 14.0
F22A
F22B
F22C
F22D
F22E
F22F
F230
F231
F232
F233
F234
F235
F236
F237
F238
F239
0 0 0 0 0 0 0
x
4
0 0 0 0 0 0
0
x
0 0 0 0 0 0 0
3
x
0 0 0 0 0 0 0
2
x
0 0 0 0 0 0 0
1
x
0 0 0 0 0 0 0
84
83
82
81
80
79
78
77
76
75
74
x
0
0 0 0 0 0 0
x
0 0 0 0 0 0 0
x
0 0 0 0 0 0 0
x
0 0 0 0 0 0
0
x
0 0 0 0 0 0 0
x
0 0 0 0 0 0 0
x
0 0 0 0 0 0 0
x
0 0 0 0 0 0 0
x
0
0 0 0 0 0 0
0 0 0 0 0 0 0
x
TABLE 38: BYTE-ORIENTED OUTPUT PORTS ADDRESSES AND PIN ASSIGNMENT
PLCC-84 PIN
I/O FUNCTION
OUT 13.3
PORT ADDRESS
61
60
59
F205
F206
F207
OUT 13.2
OUT 13.1
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SOC-3000/i Scale-On-Chip ASIC
PLCC-84 PIN
58
I/O FUNCTION
OUT 13.0
OUT 12.4
OUT 12.3
OUT 12.2
OUT 12.1
OUT 12.0
OUT 11.3
OUT 11.2
OUT 11.1
OUT 11.0
OUT 10.0
OUT 9.2
OUT 9.1
OUT 9.0
OUT 8.3
OUT 8.2
OUT 8.1
OUT 8.0
OUT 7.3
OUT 7.2
OUT 7.1
OUT 7.0
OUT 6.3
OUT 6.2
OUT 6.1
OUT 6.0
OUT 5.2
OUT 5.1
OUT 5.0
OUT 4.3
OUT 4.2
OUT 4.1
OUT 4.0
PORT ADDRESS
F208
F209
F20A
F20B
F20C
F20D
F20E
F20F
F210
F211
F212
F213
F214
F215
F216
F217
F218
F219
F21A
F21B
F21C
F21D
F21E
F21F
F220
F221
F222
F223
F224
F225
F226
F227
F228
57
56
55
54
53
52
51
50
49
48
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
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Technical Specification
SOC-3000/i Scale-On-Chip ASIC
8051-COMPATIBLE ON-CHIP PERIPHERALS
This section describes the standard 8051 peripheral devices available to the user. These
functions are fully compatible with the standard 8051 CPUs and are controlled via the
standard 8051 Special Function Registers (SFRs).
Parallel I/O Ports
Some of the parallel I/O ports of the 80C51TBO core are available on the SOC-3000 pins.
Most of the ports are already allocated to specific functions. However, the application design
may require allocating different functions to these pins. Table 39 list the available pins,
80C51 I/O port, default function and special precaution needed when changing the function
of the pin.
TABLE 39: AVAILABLE PINS ON THE 80C51 I/O PORT
PIN #
80C51
PORT
DEFAULT
SPECIAL PRECAUTIONS
FUNCTION
7
8
P1.7
P1.5
P1.4
Buzzer
None
None
None
After power-up the SOC-3000 asserts 3 pulses on this pin
9
14
P3.4 /
Timer 0
Used in CybraTech application for power-off control in low-power
applications
15
16
P3.5 /
Timer 1
None
None
Used in CybraTech application for detecting power source
(AC/Battery)
P1.6
Used in CybraTech application to control LCD electro-luminescent
backlight operation
The I/O ports are controlled and accessible using the 80C51TBO Special Function Registers
as described in its device specification.
Timers/Counters
The 80C51 Timers/Counters external inputs are available for use on SOC-3000 pin #14
(Timer 0) and pin #15 (Timer 1). Using the timers is via the 80C51 Special Function
Registers (SFRs) as described in the 80C51TBO specification.
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Technical Specification
SOC-3000/i Scale-On-Chip ASIC
SOC-3000 INITIALIZATION
At power-up or after RESET the SOC-3000 performs the following procedures:
•
•
•
Disabling all the peripheral controllers of the ASIC.
Setting the CFR and control registers to their default values.
Start the boot program (ROM mask in the chip) that checks if the chip is
programmed or not. If the chip is programmed it starts running the program
starting at address 1000H. Otherwise, it toggles the buzzer signal (pin 7)
HIGH/LOW three times to signal that the chip is erased and waits for software
download via the serial communication port.
To initialize the SOC-3000:
1. Program the SOC-3000 pin configuration in the CFR registers.
•
•
•
For general pin configuration for an LCD display, refer to Table 1, page 9. For a
quick reference, refer to Table 4, page 18.
For general pin configuration for a LED display, refer to Table 2, page 12. For a
quick reference, refer to Table 5, page 19.
For CFR bit assignment, refer to Table 32, page 62.
For examples of CFR bit assignment, refer to “Example of Pin Configuration Programming”,
on page 85.
2. Initialize the peripheral controllers used by the application.
3. Write 0x00 to the global CFR register at address C100H.
This activates all CFR registers and completes SOC-3000 initialization.
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SOC-3000/i Scale-On-Chip ASIC
SOC-3000 HARDWARE DESIGN CONSIDERATIONS AND
PERIPHERAL INTERFACE CONNECTIONS
Load Cell Interface
The SOC-3000 supports a wide range of load-cell connection configurations, each based on
various combinations of the following connection options:
•
•
•
4-wire or 6-wire interface
Up to eight load cells connected in parallel
Load cell impedance range of 350 to 1000 ohms
Individually and in combination, these connection options enable the SOC-3000 to function
on a wide range of application platforms, each having different power consumption and
system configuration requirements, while using the same electronic hardware.
4-Wire and 6-Wire Interfaces
The SOC-3000 interface to the load cell carries the following electrical signals:
•
•
•
•
SIG + (Signal Input +)
SIG – (Signal Input –)
SEN + (Excitation voltage / Sense input +)
SEN – (Excitation voltage / Sense input –)
A typical 4-wire load-cell connection, in which the distance between the load cells and the
SOC-3000 chip is small, as in a standard retail scale, is shown in Figure 26.
However, in platforms requiring long wires between the load cell and the electronic
hardware, such as weighing bridges, the voltage drop over the cables is significant and affects
accuracy.
The 6-wire interface eliminates this error factor by using the sense wires, as shown in Figure
27. The sense wires serve as a reference for the ADC converter, thus eliminating the voltage
drop over the long excitation-voltage wires.
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SOC-3000/i Scale-On-Chip ASIC
Load Cell
Cable
(4-Wires)
Regulated
5 V
Unregulated
Reg.
Power
73
AVcc
72 SEN
+
71 SIG +
SOC-3000
70 SIG -
69 SEN-
AGND
68
FIGURE 26: 4-WIRE LOAD-CELL CONNECTION
Load Cell
Cable
(6-Wires)
Regulated
Reg.
Unregulated
Power
5 V
Sense
Wire
73
AVcc
72 SEN
+
71 SIG +
70 SIG -
SOC-3000
69 SEN-
AGND
68
Sense
Wire
AGND
FIGURE 27: 6-WIRE LOAD-CELL CONNECTION
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Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Load Cells Connected in Parallel
The SOC-3000 may be connected to up to eight load cells connected in parallel. Multiple
load cells are required in heavy load applications, such as weigh bridges, that require from
two to eight load cells.
Load cells connected in parallel typically result in lower output impedance, which decreases
in direct proportion to the number of load cells. This results in a higher excitation current
and higher sensitivity to factors that throw load cells out of balance.
The SOC-3000 eliminates this problem with its high Common Mode Rejection Ratio
(CMRR), which allows the connection of a large number of load cells (up to eight) without
losing measurement accuracy. The multiple load-cell connection is shown in Figure 28.
IMPORTANT
The load cells should be matched before connecting them to the SOC-3000 to ensure the
same initial offset, span and impedance. This will eliminate error factors that are beyond the
control of SOC-3000 electronics.
NOTE
These large weighing platforms may also require a 6-wire interface connection, as described
above, on page 75.
LOADCells
Connection
Regulated
5 V
JUNCTION
BOX
73
AVcc
( ) Output
72 SEN +
*
Trimming
71 SIG +
70 SIG -
69 SEN-
Upto 8
Load Cells
SOC-3000
( ) Zero Offset
*
Trimming
AGND
68
AGND
FIGURE 28: MULTIPLE LOAD-CELL CONNECTION
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Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Load Cell Impedance
Most load cells have output impedance of 350 ohms. However, in power-restricted
applications, load cells of higher impedance, typically a 1000-ohm bridge, are used to reduce
the cell’s power consumption.
The SOC-3000 CMRR minimizes the error resulting from this high bridge impedance and
ensures full and accurate performance under this limiting condition.
The result is economical power consumption without sacrificing weighing accuracy.
Keyboard Interface
The SOC-3000 supports direct connection of a keyboard of up to 64 keys arranged in an 8 ×
8 matrix. The hardware interface with an example of a scale keyboard is shown in Figure 29.
The keyboard controller (“Keyboard Controller”, page 31) automatically scans the matrix by
asserting a high signal on the output lines (KOUT 0 to 7) and reading the input lines (KIN 0
to 7). The key hardware code, which is the code returned by the keyboard controller when
the key is pressed, is shown in Figure 12, page 31.
The keyboard controller has a programmable anti-bounce mechanism, in which different
delays can be programmed to avoid erroneous key activation due to bouncing of the keys.
The delay can be set to a discrete value from 4 to 18 milliseconds, in two-millisecond
increments. For programming the anti-bounce mechanism, see Table 14, page 32.
Scale Keyboard
KOUT7
/
7
4
1
.
*
8
-
+
±
F1
F2
F3
F4
Bsp
T
F5
F6
F7
F8
Esc
Y
KOUT6
9
KOUT5
5
6
3
%
=
C
M
C
E
R
KOUT4
2
M+
O
U
M
KOUT3
0
Enter
E
◊
P
I
KOUT2
Q
A
Z
W
S
X
R
F
V
KOUT1
D
G
H
J
K
L
KOUT0
C
B
N
M
74
75
76
77
78
79
80
8 1 8 2
KIN7
8 3
KIN6
8 4
KIN5
1
2
3
4
5
PIN#
Signal
KIN4
KIN3
KIN2
KIN1
KIN0
FIGURE 29: KEYBOARD INTERFACE
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Technical Specification
SOC-3000/i Scale-On-Chip ASIC
LCD Display Interface
The SOC-3000 interface supports LCD displays as follows:
•
•
•
Up to four backplanes, each driving 40 LCD segments
Static, 1/2-bias and 1/3-bias display options
Electro-luminescent (EL) lighting control
The hardware interface is shown in Figure 30.
The SOC-3000 is equipped with bias generators with voltage-followers buffers that generate
the LCD bias voltages and backplane multiplexing signals. Thus, LCD displays can be
directly connected to the SOC-3000 without any external component.
LCD DISPLAY
Backplane
Multiplexer
Segment Inputs
1
2
40
1
2
3
4
18 19 20 21
22 23
61
S40
PIN #
Signal
(Up to 4 Backplanes)
(Up to 40 Segments)
SOC-3000
FIGURE 30: LCD DISPLAY INTERFACE
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Technical Specification
SOC-3000/i Scale-On-Chip ASIC
LED Display Interface
The SOC-3000 interface supports LED displays as follows:
•
Up to 21 digits each comprising eight segments–seven-segment digit plus Decimal Point
(DP)
•
•
Three digit groups, Weight, Price, and Total
Automatic hardware refresh mechanism to reduce power consumption
The hardware interface is shown in Figure 31.
The LED display is directly connected to the SOC-3000 with the addition of only the LED
display drivers.
Pin 46
.
.
.
.
.
Hi-
Digit
Driver
Current
Drivers
(DY9953)
(ULN2003)
Pin 52
A3-G3,DP3
A2-G2,DP2
A1-G1,DP1
Pin 22
8
8
8
.
.
.
.
.
Segment
Drivers
(ULN2003)
Pin 45
FIGURE 31: LED PARALLEL DISPLAY INTERFACE
External Interrupt Sources
External interrupt sources may be connected to the SOC-3000 using the following pins:
a. Vdet / INT0~.
b. P3.4 / Timer-counter 0 input.
c. P3.5 / Timer-counter 1 input.
Using the Vdet input:
The Vdet input is connected to INT0 of the 80C51TBO core. In battery-operated equipment
this input is connected to the battery voltage divider and used to detect low battery voltage.
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SOC-3000/i Scale-On-Chip ASIC
Other interrupt sources may be connected to this input using open-collector drivers operating
in negative logic mode (‘0’ is active interrupt). A low voltage input triggers the INT0. The
application software applies a mechanism to determine whether the interrupt was generated
by low battery voltage or by other interrupt source.
Using Timer0 and Timer1 inputs:
SOC-3000 pin #14 is connected to the 80C51 Timer 0 input and pin #15 is connected to
Timer1 input.
These inputs may be used for counting or timer operations, or as additional interrupt inputs to
the device.
Using these inputs as interrupt inputs requires that the appropriate timer be set to 0xFE. The
next event causes the counter to increase to 0xFF and triggers the Timer 0 (or timer 1)
interrupt.
I2C-Compatible Interface
The SOC-3000 may supports a 2-wire I2C compatible serial interface. The I2C-compatible
interface shares its pins with the CPU I/O pins (P1.4, P1.5) and is implemented in software.
Table 40 provides the hardware interface information:
TABLE 40: I2C-COMPATIBLE INTERFACE HARDWARE INTERFACE
PIN#
NAME
DESCRIPTION
8
9
SDATA
Serial Data I/O pin
Serial Clock pin
SCLOCK
Power Saving Schemes
SOC-3000/i provides several means for power saving for battery-operated systems:
a. Set the CPU to IDLE or POWERDOWN operating modes – see detailed description in
the M8051TBO Technical Specification, Power Management section.
b. Disable unused hardware controllers – by disabling the controller clock via the
“Controllers Clock Enable Register (C200H)”, see tables 33 and 34.
c. Reduce the CPU frequency to minimum while idle by using the Frequency Controller.
The CPU frequency may be increased on the fly to 16MHz when an interrupt or an event
occurred.
d. Switch the power to the load cell using the I/O pins of the SOC and an external switch.
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Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Grounding and Board Layout Recommendations
As with all high-resolution data converters, special attention must be paid to grounding and to
the PCB layout of SOC-3000 based designs in order to achieve optimum performance from
the Analog-To-Digital Converter.
Four-layer boards are recommended where the outer layers are ground layers covering the
whole surface, and the inner layers are used for routing the signal lines. The same ground
plane should be used for both the digital and analog grounds.
Keep all ground connection as short as possible. Make sure that the return paths of the
signals are as close as possible to the paths that the currents took to reach their destinations.
Avoid digital signals flowing under the analog components area.
Wherever possible, avoid large discontinuities in the ground plane, since they force the return
signals to travel on a longer path. An example of correct implementation is routing all
signals through the inner layers and keeping the outer layers for ground.
If you plans to connect fast logic signals (rise/fall time < 5ns) to any of the SOC-3000 digital
inputs, add a series resistor to each relevant line in order to keep rise and fall times longer
than 5ns at the SOC-3000 input pins. A value of 100 Ω or 200 Ω is usually sufficient to
prevent high-speed signals from capacitive coupling into the SOC-3000 and affecting the
accuracy of the ADC.
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Technical Specification
SOC-3000/i Scale-On-Chip ASIC
IN-CIRCUIT EMULATOR (ICE) SYSTEM
The In-Circuit Emulator (ICE-3000) system provides full emulation of the SOC-3000 device.
It includes a plug-in pod that replaces the SOC-3000 device thus enabling full emulation of
the device in the target board. It emulates the SOC-3000 device in real-time simplifying the
hardware-software integration process.
The ICE-3000 is composed of 3 elements:
a. DS-51 emulator.
b. SOC-3000 Personality Probe.
c. Windows-based software debugger.
The system enables you to access all SOC-3000 device registers and memory locations and
debug the application using free run or breakpoints and single step execution control.
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Technical Specification
SOC-3000/i Scale-On-Chip ASIC
EXAMPLES OF PIN CONFIGURATION PROGRAMMING
The following pages show examples of pin configuration programming, as follows:
•
Example 1 shows a 20-digit LCD display and an 8×8 keyboard.
•
Example 2 shows a 16-digit LCD display, an 8×4 keyboard, 8 output ports and 4 I/O
ports.
•
•
Example 3 shows a 21-digit LED Parallel display, an 8×8 keyboard and 13 output ports.
Example 4 shows the pin programming for all output and I/O ports.
Example 1: Configuring a 20-digit LCD Display and an 8x8
Keyboard
•
20-digit LCD display support implies allocation of the whole LCD driver output pins to
the LCD display, using 4 backplanes and 40 segments. Thus, pins 18-61 should be
assigned to the LCD controller/driver.
•
8x8 keyboard support implies allocation of the whole keyboard I/O pins to the keyboard
controller. Thus, pins 1-5 and 74-84 should be assigned to the keyboard controller.
Table 41 lists the CFR registers affected and their required values.
TABLE 41: EXAMPLE 1: 20-DIGIT LCD DISPLAY, 8×8 KEYBOARD
FUNCTION
LCD Display
CFR REGISTER ADDRESS PORT / SEGMENT
& VALUE
AFFECTED
PINS
C101H = 00H
C102H = 00H
C103H = 00H
C104H = 00H
C105H = 00H
C106H = 00H
C107H = 00H
C108H = 00H
C109H = 00H
C10AH = 00H
C10BH = 00H
S37 – S40
S32 – S36
S28 – S31
S24 – S27
S20 – S23
S16 – S19
S12 – S15
S8 – S11
S4 – S7
58 – 61
53 – 57
49 – 52
45 – 48
41 – 44
37 – 40
33 – 36
29 – 32
25 – 28
22 – 24
18 – 21
S1 – S3
BP1 – BP4
Keyboard Matrix
C10DH = FFH
C10EH = FFH
KIN0 – KIN7
KOUT0 – KOUT7
1 – 5; 82 – 84
74 – 81
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SOC-3000/i Scale-On-Chip ASIC
Example 2: Configuring a 16-digit LCD Display, an 8x4
Keyboard, 8 Output and 4 I/O Ports
•
16-digit LCD display support implies partial allocation of the LCD driver output pins to
the LCD display, using 4 backplanes and 32 segments. Thus, pins 18-52 should be
assigned to the LCD controller/driver.
•
•
•
8x4 keyboard support implies partial allocation of the keyboard I/O pins to the keyboard
controller. Thus, pins 1-5 and 78-84 should be assigned to the keyboard controller.
8 output ports will be implemented using the 8 pins of the LCD driver that are not used
for the display. Thus, pins 53-61 should be assigned as Output ports.
4 I/O ports will be implemented using the 4 pins of the keyboard input matrix that are
not used by the keyboard. Thus, pins 74-77 should be assigned as I/O ports.
Table 42 lists the CFR registers affected and their required values.
TABLE 42: EXAMPLE 2: 16-DIGIT LCD DISPLAY, 8×4 KEYBOARD, 8 OUTPUT, 4 I/O
FUNCTION
CFR REGISTER ADDRESS PORT / SEGMENT
& VALUE
AFFECTED
PINS
LCD Display
C102H = E8H
C103H = 00H
C104H = 00H
C105H = 00H
C106H = 00H
C107H = 00H
C108H = 00H
C109H = 00H
C10AH = 00H
C10BH = 00H
S32
53
S28 – S31
S24 – S27
S20 – S23
S16 – S19
S12 – S15
S8 – S11
S4 – S7
49 – 52
45 – 48
41 – 44
37 – 40
33 – 36
29 – 32
25 – 28
22 – 24
18 – 21
S1 – S3
BP1 – BP4
Keyboard Matrix
Output Ports
I/O Ports
C10DH = FFH
C10EH = F0H
KIN0 – KIN7
KOUT4 – KOUT7
1 – 5; 82 – 84
78 – 81
C101H = FFH
C102H = E8H
P13.0 – P13.3
P12.1 – P12.4
58 –61
54 – 57
C10E = F0H
KOUT4 – KOUT7
P14.0 – P14.3
78 – 81
74 – 77
Revision B
Page 86
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Example 3: Configuring a 21-digit LED Parallel Display, an
8x8 Keyboard and 13 Output Ports
•
21-digit LED parallel display support implies full allocation of the LED parallel display
controller output pins to the LED parallel display. Thus, pins 22-52 should be assigned
to the LED parallel display controller.
•
•
8x8 keyboard support implies full allocation of the keyboard I/O pins to the keyboard
controller. Thus, pins 1-5 and 74-84 should be assigned to the keyboard controller.
13 output ports will be implemented using the available OUTPUT ports available in the
ASIC. Thus, pins 53-61 should be assigned as Output ports.
Table 43 lists the CFR registers affected and their required values.
TABLE 43: EXAMPLE 3: 21-DIGIT LED DISPLAY, 8×8 KEYBOARD, 13 OUTPUT
FUNCTION
CFR REGISTER
PORT / SEGMENT
AFFECTED
PINS
ADDRESS & VALUE
LED Display
C103H = 55H
DIG4 – 7
SEG DP3; DIG1 - 3
SEG D3 – G3
SEG DP2; A3 – C3
SEG D2 – G2
SEG DP1; A2 – C2
SEG D1 – G1
49 – 52
C104H = 55H
C105H = 55H
C106H = 55H
C107H = 55H
C108H = 55H
C109H = 55H
C10AH = 15H
45 – 48
41 – 44
37 – 40
33 – 36
29 – 32
25 – 28
22 – 24
SEG A1 – C1
Keyboard Matrix
Output Ports
C10DH = FFH
C10EH = FFH
KIN0 – KIN7
KOUT0 – KOUT7
1 – 5; 82 – 84
74 – 81
C101H = FFH
C102H = EAH
C10BH = 56H
P13.0 – P13.3
P12.0 – P12.4
P4.0 – P4.3
58 –61
53 – 57
18 – 21
Revision B
Page 87
July, 2002
CybraTech (2000) Ltd.
Technical Specification
SOC-3000/i Scale-On-Chip ASIC
Example 4: Outputs and I/O Ports Programming
•
Output ports support implies full allocation of the LCD display controller output pins to
the OUTPUT function. Thus, pins 18-61 should be assigned to the OUTPUT controller.
•
I/O ports support implies full assignment of the Keyboard controller pins to the I/O
ports. Thus, pins 1 – 5 and 74 – 84 should be assigned to the I/O controller.
TABLE 44: OUTPUT AND I/O PORTS PROGRAMMING
FUNCTION
CFR REGISTER
PORT / SEGMENT
AFFECTED
PINS
ADDRESS & VALUE
OUTPUT ports
C101H = FFH
P13.0 – P13.4
P12.0 – P12.4
P11.0 – P11.3
P10.0
P9.0 – P9.2
P8.0 – P8.3
P7.0 – P7.3
P6.0 – P6.3
P5.0 – P5.2
P4.0 – P4.3
58 – 61
C102H = EAH
C103H = AAH
C104H = 80H
C106H = 2AH
C107H = FCH
C108H = FFH
C109H = EAH
C10AH = 2AH
C10BH = 56H
53 - 57
49 – 52
48
37 – 39
33 – 36
29 – 32
25 – 28
22 – 24
18 - 21
I/O Ports
C10DH = 00H
C10EH = 00H
P15.0 – P15.7
P14.0 – P14.7
1 – 5; 82 - 84
74 - 81
Revision B
Page 88
July, 2002
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