RM3183 [ETC]
Dual ARINC 429 Line Receiver; 双ARINC 429线路接收器
| 型号： | RM3183 |
| 厂家： | 
ETC |
| 描述： | Dual ARINC 429 Line Receiver |
| 文件： | 总12页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Electronics
Semiconductor Division
RM3183
Dual ARINC 429 Line Receiver
clamping diodes. Self-test logic inputs are provided for
internal system tests. These inputs force the outputs to
either a high, a low, or a null state for off-line system tests.
Features
• Converts ARINC levels to serial data
• Adjustable noise filters
• TTL and CMOS compatible outputs
• Built-in test inputs
• Input protection circuitry
• Mil-Std-883B screening available
• 20-pin DIP and LCC packages available
• Dice with Mil visual screening available
Input noise filtering is accomplished with external capaci-
tors. Two are required for each channel and can be adjusted
for best noise immunity at a specific data rate.
Three power supplies are needed plus ground. The input
thresholds depend only on the logic supply, so a wide range
of dual supplies can be accommodated.
Description
The Raytheon RM3183 line receiver is the companion chip
to the RM3182 line driver. Together they provide all the
analog functions needed for the ARINC 429 interface.
Digital data processing involving serial-to-parallel conver-
sion and clock recovery can be accomplished using one of
the ARINC interface ICs available or by discrete or gate
array implementations.
The RM3183 is a dual line receiver designed to meet all
requirements of the ARINC 429 interface specification.
It contains two independent receiver channels which accept
differential input signals and converts them to serial TTL
data.
Input overvoltage protection is provided by special circuitry
including dielectrically-isolated thin-film resistors and
Block Diagram
+VL
9
+VS
11
18
15
In 1A
C1A
C1B
Out 1A
Out 1B
Input
16
Protection
& Level
Shift
In 1B
19
17
12
Cap 1A
Cap 1B
2
Test A
Test B
Test
Interface
20
8
5
Out 2A
Out 2B
C2A
C2B
6
4
In 2A
In 2B
Input
Protection
& Level
Shift
7
3
Cap 2A
Cap 2B
1
14
Gnd
65-3183-01
-VS
Rev. 1.0.0
RM3183
PRODUCT SPECIFICATION
The ARINC inputs must be forced to 0V when using the test
inputs. If the test inputs are not used, they should be
grounded.
Functional Description
The RM3183 contains two discrete ARINC 429 receiver
channels. Each channel contains three main sections: a
resistor-diode input network, a window comparator, and a
logic output buffer stage. The first stage provides overvolt-
age protection and biases the signal using voltage dividers
and current sources which are internally connected to the
The window comparator stage generates two serial data
streams, one having logic 1 states corresponding to ARINC
“High” states (OUTA), and the other having logic 1 states
corresponding to ARINC “Low” states (OUTB). An ARINC
“Null” state at the inputs forces both outputs to logic 0.
Thus, the ARINC clock signal is recovered by applying a
NOR function to OUTA and OUTB.
+V logic supply. This configuration provides excellent
L
input common mode rejection and a stable reference voltage
for the window comparators. Because the threshold for
switching is determined by this circuitry, ±5% tolerance is
recommended for the +V supply. The test inputs will set the
L
outputs to a predetermined state for built-in test capability.
The output stage generates a TTL compatible logic output
capable of driving several gate inputs.
Pin Assignments
LCC
Top View
Ceramic Dip
Top View
20
19
TestB
-V
S
Cap1A
TestA
2
18
17
16
15
In1A
Cap2B
In2B
3
4
5
6
In2B
4
18 In1A
17 Cap1B
16 In1B
15 Out1A
14 GND
Cap1B
In1B
Out2B
In2A
5
6
7
8
Out2B
In2A
Cap2A
Out2A
Out1A
14
13
12
11
GND
NC
Cap2A
Out2A
7
8
9
65-3183-03
+V
L
Out1B
+V
S
NC
10
65-3183-02
Absolute Maximum Ratings
Parameter
Min.
Max.
+20
Units
Supply Voltage
+V
–V
+V
VDC
VDC
VDC
°C
S
S
L
–20
+7
Operating Temperature Range
Storage Temperature Range
Input Voltage Range
-55
-65
+125
+150
±50
°C
V
Output Short Circuit Duration
Internal Power Dissipation
Not protected
900
mW
Lead Soldering Temperature (60 seconds)
+300
°C
2
PRODUCT SPECIFICATION
RM3183
Thermal Characteristics (Still air, soldered into PC board)
Ceramic DIP
LCC
Maximum Junction Temperature
Maximum P T < 50°C
+175°C
1042 mW
60°C/W
+175°C
925 mW
37°C/W
105°C/W
D
A
Thermal Resistance, θJ
Thermal Resistance, θJ
C
C
120°C/W
DC Electrical Characteristics
T = -55°C to +125°C, ±12V ≤ V ±15V, V = +5V, unless otherwise noted
A
S
L
Symbol
Parameter
Conditlons
OUTA = 1
Min.
6.5
Typ.
10
Max.
13
Units
V
V
V
V
V(A)-V(B)
V(A)-V(B)
V(A)-V(B)
V
V
V
V
IH
IL
OUTB = 1
-6.5
-2.5
-10
0
-13
OUTA and OUTB = 0
+2.5
IN
IC
(2)
V(A) and V(B)-GND
Maximum common mode
frequency = 80 kHz
±5
R
R
R
Input resistance, Input A to Input B
Input resistance, Input A to Gnd
Input resistance, B to Gnd
30
19
19
50
25
25
3
kΩ
kΩ
kΩ
pF
pF
pF
I
H
G
C (1, 2)
Input capacitance, A to B
Filter caps disconnected
Filter caps disconnected
Filter caps disconnected
10
10
10
I
(1, 2)
C
C
Input capacitance, A to Gnd
Input capacitance, B to Gnd
3
H
(1, 2)
3
G
Test Inputs (TESTA, TESTB)
V
V
Logic 1 input voltage
Logic 0 input voltage
Logic 1 input current
Logic 0 input current
2.7
V
V
IH
IL
0.0
15
V(A) = 0V
V(B) = 0V
I
IH
I
IL
V
V
= 2.7V
= 0.0V
5
µA
µA
IH
0.5
1.0
IL
Outputs
V
I
I
I
I
= 100 µA
= 2.8 mA
= 100 µA
= 2.0 mA
T = 25°C
4.0
3.5
4.3
4.0
0.02
0.3
40
V
V
OH
OH
OH
OL
OL
A
Full temperature range
V
T = 25°C
A
0.08
0.8
70
V
OL
Full temperature range
V
Tr
Tf
Rise Time
Fall Time
C = 50 pF, T = 25°C
L
ns
ns
ns
A
C = 50 pF, T = 25°C
L
30
70
A
T
Propagation delay
Output low to high
C = 50 pF, f = 400 kHz
800
PLH
L
O
Filter caps = 39 pF
T
Output high to low
T = 25°C
A
320
ns
PHL
3
RM3183
PRODUCT SPECIFICATION
DC Electrical Characteristics (continued)
T = -55°C to +125°C, ±12V ≤ V ±15V, V = +5V, unless otherwise noted
A
S
L
Symbol
Parameter
Conditlons
Min.
Typ.
Max.
Units
Supply Current
I
Test inputs = 0V
±V = 15V, T = 15°C
3.7
3.0
8.7
7.4
9.0
8.6
7.0
6.0
mA
mA
mA
mA
mA
mA
CC
(+V )
S
A
S
±V = 12V, T = 15°C
S
A
I
Test inputs = 0V
Test inputs = 0V
±V = 15V, T = 15°C
15.0
14.0
20.0
18.0
EE
(-V )
S
A
S
±V = 12V, T = 15°C
S
A
I
±V = 15V, T = 15°C
S A
DD
(+V )
L
±V = 12V, T = 15°C
S
A
Notes:
1. With noise filter capacitors disconnected.
2. Guaranteed by design.
Truth Table
Test Inputs
Outputs
ARINC Inputs
V(A) - V(B)
TESTA
TESTB
OUTA
OUTB
Null
0
0
0
0
1
1
0
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
Low
High
V(A) = 0V, V(B) = 0V
V(A) = 0V, V(B) = 0V
V(A) = 0V, V(B) = 0V
4
PRODUCT SPECIFICATION
RM3183
Typical Performance Characteristics
1000
900
12
11
10
9
VL (IDD
)
800
-VS (IEE
)
700
600
500
400
300
200
100
0
TPLH
8
VS
=
15V
VL = +5V
7
TPHL
6
5
+VS (I CC
)
4
3
-60
140
115
140
90
-60
-35 -10
15
40
65
90 115
-35
-10
15
40
65
Temperature (°C)
Temperature (°C)
Figure 1. Propagation Delay vs. Temperature
Figure 2. Supply Current vs. Temperature
C
L
= 50 pF, C
= 39 pF
FILTER
1.00
0.75
0.50
0.25
0
4.5
4.3
4.1
3.9
3.7
3.5
+125°C
+25°C
-55°C
+125°C
+25°C
+55°C
3.0
3.0
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
(mA)
2.0
2.5
I
(mA)
I
OH
OL
Figure 3. Output Voltage Low vs. Output Current
Figure 4. Output Voltage High vs. Output Current
70
3.0
60
TA = +25 C
2.5
2.0
1.5
1.0
0.5
0
TR
TPLH
50
TPHL
40
TF
30
20
10
0
400
-60
-35
-10
15
40
65
90
115 140
0
50
100 150 200
250 300 350
Temperature (°C)
Filter Capacitance (pF)
Figure 5. T and T vs. Temperature
Figure 6. Propagation Delay vs. Filter Capacitance
= 25°C
R
F
T
A
5
RM3183
PRODUCT SPECIFICATION
AC Test Waveforms
+10V
ARINC In
(Differential)
0V
90%
10%
90%
10%
Logic
Out
Logic Out
(A Output)
TPLH
TPHL
TF
TR
65-3183-10
65-3183-16
Figure 7. Propagation Delay
Figure 8. Rise/Fall Times
Test Circuit
+15V
-15V
+5V
µ
µ
µ
0.01 F
0.01 F
0.1 F
VIN1
9
11
18
1
VOUT1
15
50 pF
VIN2
6
VOUT2
12
8
50 pF
RM3183
16
4
VOUT3
VREF
50 pF
VOUT4
5
19
17
3
7
14
50 pF
39pF
39pF 39pF 39pF
Notes:
1. V = 400 kHz square wave, -3.5V to +3.5V.
IN
65-3183-11
2. Set V
Set V
= +3.5 V to test V
= -3.5 V to test V
and V
.
OUT3
REF
REF
OUT1
OUT2
and V
.
OUT4
3. 50 pF load capacitance includes probe and wiring capacitance.
Figure 9. AC Test Schematic Diagram
6
PRODUCT SPECIFICATION
RM3183
The RM3183 can be used with Raytheon’s RM3182 Line
Applications Information
The standard connections for the RM3183 are shown in
Driver to provide a complete analog ARINC 429 interface.
A simple application which can be used for systems requir-
ing a repeater-type circuit for long transmissions or test
interfaces is given in Figure 2. More RM3182 drivers may be
added to test multiple ARINC channels, as shown.
Figure 1. Dual supplies from ±12 to ±15 VDC are recom-
mended for the ±V supplies. Decoupling of all supplies
S
should be done near the IC to avoid propagation of noise
spikes due to switching transients. The ground connections
should be sturdy and isolated from large switching currents
to provide as quiet a ground reference as possible.
An all digital IC is available which forms a complete
receiver system when combined with the RM3183. The
Thomson EF4442 is a four channel ARINC 429 receiver IC
which contains all the digital circuitry required to interface
with an 8-bit processor. Each channel consists of a 32-bit
register, an 8-bit status word comparator, and a 24-bit latch.
A multiplexer and 8-bit data bus buffer form the interface to
the system microprocessor. Figure 3 shows a typical ARINC
application having both transmit and receive functions using
four ICs: the EF4442, the RM3182 driver and two RM3183
dual receivers.
The noise filter capacitors are optional and are added to
provide extra noise immunity by limiting the noise band-
width of the input signal before it reaches the comparator.
Two capacitors are required for each channel and they must
all be the same value. The suggested capacitor value for a
100 KHz operation is 39 pF, which will give a noise band-
width of approximately 800 KHz. For lower data rates, larger
values of capacitance may be used to yield better noise
performance. To get optimum performance, the following
equation should be used to calculate capacitor value for a
specific data rate:
3.95 × 10–6
C = ---------------------------
FO
FO = Data Rate (bits/sec)
7
RM3183
PRODUCT SPECIFICATION
Applications
+5V
+15V
9
11
RM3183
18
16
19
In 1A
In 1B
ARINC
Channel
1
15
12
A
Channel 1
Data Out
To Logic
39 pF
Cap 1A
B
17
Cap 1B
39 pF
39 pF
6
4
In 2A
8
5
ARINC
Channel
2
A
Channel 2
Data Out
To Logic
In 2B
7
3
Cap 2A
B
Cap 2B
39 pF
2
Test A
Test B
Logic
Test
Inputs
20
1
14
65-3183-12
-15V
Figure 9. ARINC Receiver Standard Connections
A
Data (A)
Data (B)
A
OUT
ARINC
Out 1A
Out 2A
In 1A
In 1B
A
B
Test
Channel
1
Test
Channel
Input
B
RM3182
B
OUT
1/2
RM3183
A
Data (A)
Data (B)
OUT
A
B
Test
Channel
2
RM3182
B
OUT
To Additional
Channels
65-3183-13
Figure 10. Repeater Circuit
8
PRODUCT SPECIFICATION
RM3183
Applications (continued)
+5V
VCC
+15V
Inputs
VI
VR
Sync
+V
Clk
S
VSS Mode
+VL
RM3182
AOUT
BOUT
In 1A
In 1B
H0
Out 1A
ARINC
Line Out
ARINC
Channel
0
Data (A)
Data (B)
L0
N1
Out 1B
RM3183
N0
-VS
CB
In 2A
H1
L1
Out 2A
Out 2B
-15V
ARINC
Channel
1
Gnd PE CA
75 pF
In 2B
+VS
-VS
GND
EF4442
75 pF
-15V
Reset
+15V
From
Microprocessor
IRQ
R/W
+VS
-VS
GND
H2
L2
In 1A Out 1A
ARINC
Channel
2
Out 1B
In 1B
Clock
Microprocessor
Data Bus
RM3183
D0 - D8
Out 2A
Out 2B
H3
L3
In 2A
In 2B
ARINC
Channel
3
A0
A1
CS
From
Address
Decoder
+VL
65-3183-14
To +5V
Figure 11. Four-Channel ARINC Receiver Circuit
-15V
10 Ω
1/2 W
+15V
1
RM3183
11
18
16
4
5
6
10K
10K
10K
15
14
10K
8
9
12
10K
10K
10
1/2 W
Ω
10
1/2 W
Ω
65-3183-15
+5V
Figure 12. Burn-In Circuit
+15V
9
PRODUCT SPECIFICATION
RM3183
Mechanical Dimensions
20-Lead Ceramic DIP
Notes:
Inches
Millimeters
Min. Max.
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
Symbol
Notes
Min.
Max.
A
—
.200
.023
.065
.015
1.060
.310
—
.36
1.14
.20
—
5.08
.58
2. The minimum limit for dimension "b2" may be .023(.58mm) for leads
number 1, 10, 11 and 20 only.
b1
b2
c1
D
.014
.045
.008
—
8
2, 8
1.65
.38
3. Dimension "Q" shall be measured from the seating plane to the
base plane.
8
4
4. This dimension allows for off-center lid, meniscus and glass overrun.
25.92
7.87
5. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 20.
E
.220
5.59
4
5, 9
7
e
.100 BSC
.300 BSC
2.54 BSC
7.62 BSC
6. Applies to all four corner's (leads number 1, 10, 11, and 20).
eA
L
7. "eA" shall be measured at the center of the lead bends or at the
.125
.200
.060
—
3.18
5.08
1.52
—
centerline of the leads when "α" is 90°.
Q
s1
α
.015
.005
90°
.38
.13
90°
3
6
8. All leads – Increase maximum limit by .003(.08mm) measured at the
center of the flat, when lead finish is applied.
105°
105°
9. Eighteen spaces.
D
Note 1
E
s1
eA
e
A
Q
c1
α
L
b1
b2
10
RM3183
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
20-Terminal LCC
Notes:
Inches
Millimeters
Symbol
Notes
1. The index feature for terminal 1 identification, optical orientation or
handling purposes, shall be within the shaded index areas shown
on planes 1 and 2. Plane 1, terminal 1 identification may be an
extension of the length of the metallized terminal which shall not be
wider than the B1 dimension.
Min.
Max.
Min.
Max.
A
.060
.050
.022
.006
.342
.100
.088
.028
.022
.358
1.52
1.27
.56
2.54
2.24
.71
3, 6
3, 6
2
A1
B1
2. Unless otherwise specified, a minimum clearance of .015 inch
(0.38mm) shall be maintained between all metallized features (e.g.,
lid, castellations, terminals, thermal pads, etc.).
B3
.15
.56
2, 5
D/E
D1/E1
D2/E2
D3/E3
e
8.69
9.09
.200 BSC
.100 BSC
.358
5.08 BSC
2.54 BSC
— 9.09
3. Dimension "A" controls the overall package thickness. The
maximum "A" dimension is the package height before being solder
dipped.
—
4. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer's option, from that shown on the drawing. The index
corner shall be clearly unique.
.050 BSC
.040 REF
.020 REF
1.27 BSC
1.02 REF
.51 REF
h
4
4
j
5. Dimension "B3" minimum and "L3" minimum and the appropriately
derived castellation length define an unobstructed three
dimensional space traversing all of the ceramic layers in which a
castellation was designed. Dimensions "B3" and "L3" maximum
define the maximum width and depth of the castellation at any point
on its surface. Measurement of these dimensions may be made
prior to solder dripping.
L1
.045
.055
.095
.015
1.14
1.40
2.41
.38
L2
.075
.003
1.91
.08
L3
5
ND/NE
N
5
5
20
20
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
PLANE 2
PLANE 1
A1
E
LID
E3
1
D
D3
(h) X 45°
(j) X 45°
3 PLCS
4
4
A
INDEX
CORNER
E1
E2
B1
e
D2
L3
D1
B3
L2
L1
DETAIL "A"
DETAIL "A"
11
PRODUCT SPECIFICATION
RM3183
Ordering Information
Part Number
RM3183S
Package
Operating Temperature Range
20 Lead Ceramic DIP
-55°C to +125°C
-55°C to +125°C
RM3183L
20 Terminal Leadless Chip Carrier
The information contained in this data sheet has been carefully compiled; however, it shall not by implication or otherwise become part of the
terms and conditions of any subsequent sale. Raytheon’s liability shall be determined solely by its standard terms and conditions of sale.
No representation as to application or use or that the circuits are either licensed or free from patent infringement is intended or implied.
Raytheon reserves the right to change the circuitry and any other data at any time without notice and assumes no liability for errors.
LIFE SUPPORT POLICY:
Raytheon’s products are not designed for use in life support applications, wherein a failure or malfunction of the component can reasonably
be expected to result in personal injury. The user of Raytheon components in life support applications assumes all risk of such use and
indemnifies Raytheon Company against all damages.
Raytheon Electronics
Semiconductor Division
350 Ellis Street
Mountain View, CA 94043
650.968.9211
FAX 650.966.7742
8/97 0.0m
Stock# DS30003183
© Raytheon Company 1997
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