RM2211D [ETC]
FSK Demodulator/Tone Decoder; FSK解调器/解码器音
| 型号： | RM2211D |
| 厂家： | 
ETC |
| 描述： | FSK Demodulator/Tone Decoder |
| 文件： | 总16页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Electronics
Semiconductor Division
RC2 2 1 1
FS K De m o d u la t o r/To n e De c o d e r
Features
Applications
¥ Wide frequency range Ð 0.01 Hz to 300 kHz
¥ Wide supply voltage range Ð 4.5V to 20V
¥ DTL/TTL/ECL logic compatibility
¥ FSK demodulation
¥ Data synchronization
¥ Tone decoding
¥ FSK demodulation with carrier-detector
¥ FM detection
¥ Wide dynamic range Ð 2 mV to 3 V
¥ Carrier detection
RMS
¥ Adjustable tracking range Ð ±1% to ±80%
¥ Excellent temperature stability Ð 20 ppm/°C typical
Description
The RC2211 is a monolithic phase-locked loop (PLL)
system especially designed for data communications. It is
particularly well-suited for FSK modem applications, and
operates over a wide frequency range of 0.01 Hz to 300 kHz.
It can accommodate analog signals between 2 mV and 3V,
and can interface with conventional DTL, TTL and ECL
logic families. The circuit consists of a basic PLL for
tracking an input signal frequency within the passband, a
quadrature phase detector which provides carrier detection,
and an FSK voltage comparator which provides FSK
demodulation. External components are used to indepen-
dently set carrier frequency, bandwidth and output delay.
Block Diagram
Data Filter
Loop Filter
FSK
Data
f-Detector
Output
FSK
Comparator
f
FSK
VCO
Input
f
Preamp
Lock
Detector
Outputs
f-Detector
Lock
Detector
Filter
Lock
Detector
Comparator
65-2211-01
Rev. 1.0.1
PRODUCT SPECIFICATION
RC2211
FSK Data Output (Pin 7)
This output is an open collector stage which requires a
pull-up resistor, R , to +V for proper operation. It can sink
Description of Circuit Controls
Signal Input (Pin 2)
L
S
5 mA of load current. When decoding FSK signals the FSK
data output will switch to a ÒhighÓ or off state for low input
frequency, and will switch to a ÒlowÓ or on state for high
input frequency. If no input signal is present, the logic state
at pin 7 is indeterminate.
The input signal is AC coupled to this terminal. The internal
impedance at pin 2 is 20 kW. Recommended input signal
level is in the range of 10 mV
to 3 V .
RMS
RMS
Quadrature Phase Detector Output, Q (Pin 3)
This is the high impedance output of the quadrature phase
detector, and is internally connected to the input of lock
detector voltage comparator. In tone detection applications,
pin 3 is connected to ground through a parallel combination
FSK Comparator Input (Pin 8)
This is the high impedance input to the FSK voltage
comparator. Normally, an FSK post detection or data Þlter is
connected between this terminal and the PLL phase detector
of R and C (see Figure 1) to eliminate chatter at the lock
D
D
output (pin 11). This data Þlter is formed by R and C of
Figure 1. The threshold voltage of the comparator is set by
detector outputs. If this tone detector section is not used,
pin 3 can be left open circuited.
F
F
the internal reference voltage, V , available at pin 10.
R
Lock Detector Output, Q (Pin 5)
Reference Bypass (Pin 9)
The output at pin 5 is at a ÒhighÓ state when the PLL is out of
lock and goes to a ÒlowÓ or conducting state when the PLL is
locked. It is an open collector output and requires a pull-up
This pin can have an optional 0.1, mF capacitor connected to
the ground.
resistor, R , to +V for proper operation. In the ÒlowÓ state it
L
S
Reference Voltage, V (Pin 10)
can sink up to 5 mA of load current.
R
This pin is internally biased at the reference voltage level,
Lock Detector Complement, Q (Pin 6)
V ; V = +V /2 Ð 650 mV. The DC voltage level at this pin
R
R
S
forms an internal reference for the voltage levels at pin 3, 8,
11 and 12. Pin 10 must be bypassed to ground with a 0.1 mF
capacitor.
The output at pin 6 is the logic complement of the lock
detector output at pin 5. This output is also an open collector
type stage which can sink 5 mA of load current in the low or
ÒonÓ state.
R
B
R
L
510K
(1)
(7)
R
F
+V
S
100K
(8)
(11)
Loop
f-Detector
C
C
F
1
FSK
Output
R
FSK
Comparator
1
Input
Preamp
f
(2)
(12)
Internal
Reference
(10)
VCO
f
0.1 µF
R
0
(14)
C
(13)
(3)
Q
Q
0
0.1 µF
(6)
Input
Signal
Lock
Detector
Outputs
Quad
f-Detector
(5)
Lock
Detector
Comparator
R
D
100K
to 470K
C
D
65-2211-02
Figure 1. Generalized Circuit Connection for FSK and Tone Detection
2
RC2211
PRODUCT SPECIFICATION
2. Internal Reference Voltage, V (measured at pin 10)
R
Loop Phase Detector Output (Pin 11)
This terminal provides a high impedance output for the loop
phase detector. The PLL loop Þlter is formed by R1 and C1
connected to pin 11 (see Figure 1). With no input signal, or
with no phase error within the PLL, the DC level at pin 11 is
+V
æ
Sö
----------
-650 mV
ø
VR
=
è
2
3. Loop Lowpass Filter Time Constant, t
very nearly equal to V . The peak voltage swing available at
R
the phase detector output is equal to ±V .
R
t = R C
1 1
VCO Control Input (Pin 12)
4. Loop Dampening, z:
VCO free running frequency is determined by external
timing resistor, R0, connected from this terminal to ground.
æ
ç
è
ö
C0
1
4
æ ö
÷
--
z =
------
C
è ø
The VCO free running frequency, F is given by:
0
1ø
1
F0 (Hz) = -------------
R0C0
5. Loop Tracking Bandwidth, ±DF/F :
0
Df/F = R0/R1
O
where C is the timing capacitor across pins 13 and 14. For
0
Tracking
Bandwidth
optimum temperature stability R must be in the range of
10 kW to 100 kW (see Typical Performance Characteristics).
0
Df
Df
This terminal is a low impedance point, and is internally
biased at a DC level equal to V . The maximum timing cur-
R
rent drawn from pin 12 must be limited to £3 mA for proper
operation of the circuit.
F
LL
F
F
F
F
1
0
2
LH
65-2211-03
VCO Timing Capacitor (Pins 13 and 14)
6. FSK Data Filter Time Constant, t :
F
VCO frequency is inversely proportional to the external tim-
ing capacitor, C , connected across these terminals. C must
t = R C
F F F
0
0
be non-polarized, and in the range of 200 pF to 10 mF.
7. Loop Phase Detector Conversion Gain, Kf (Kf is the
differential DC voltage across pins 10 and 11, per unit
of phase error at phase-detector input):
VCO Frequency Adjustment
VCO can be Þne tuned by connecting a potentiometer, Rx, in
series with R at pin 12 (see Figure 2).
0
(Ð2) (VR)
kf (in volts per radian) = ---------------------------
p
VCO Free-Running Frequency, F
0
The RC2211 does not have a separate VCO output terminal.
Instead, the VCO outputs are internally connected to the
phase detector sections of the circuit. However, for set-up or
adjustment purposes, the VCO freerunning frequency can be
8. VCO Conversion Gain, K is the amount of change in
0
VCO frequency per unit of DC voltage change at pin 11:
Ð1
K0 (in Hertz per volt) = ---------------------
C0R1VR
measured at pin 3 (with C disconnected) with no input and
D
with pin 2 shorted to pin 10.
9. Total Loop Gain, K :
T
Design Equations
K (in radians per second per volt)= 2 pKfK0
T
See Figure 1 for DeÞnitions of Components.
4
=
-------------
C 0 R 1
1. VCO Center Frequency, F :
0
1
F 0 (Hz) = -------------
R0C0
10. Peak Phase Detector Current, I :
A
VR
I
A (mA) = -------
25
3
PRODUCT SPECIFICATION
RC2211
Pin Assignments
1
2
3
4
5
6
7
+V
Timing Capacitor
Timing Capacitor
Timing Resistor
14
13
12
11
10
9
S
Input
Lock Detector Filter
GND
Loop f-Detector
Q
Q
Reference Voltage Output
Reference Bypass
8
FSK Data Output
FSK Comparator Input
65-2211-04
Absolute Maximum Ratings
Parameter
Min
Max
+20
Unit
Supply Voltage
-20
V
Input Signal Level
3
V
RMS
Storage Temperature Range
Operating Temperature Range
-65
-55
-25
-0
+150
+125
+85
°C
°C
RM2211D
RV2211N
RC2211N
PDIP
°C
+70
°C
Junction Temperature
+125
+175
+300
468
°C
CerDIP
°C
Lead Soldering Temperature (60 sec.)
°C
Max. P T <50°C
PDIP
mW
mW
D
A
CerDIP
1042
Thermal Characteristics
Parameter
14 Lead Plastic DIP
—
14 Lead Ceramic DIP
60°C/W
Therm. Res q
JC
Therm. Res. q
160°C/W
120°C/W
JA
For T > 50°C Derate at
6.5 mW/°C
8.33 mW/°C
A
4
RC2211
PRODUCT SPECIFICATION
Electrical Characteristics
(Test Conditions +V = +12V, T +25°C, R0 = 30 kW, C0 = 0.033 mF. See Figure 1 for component designations.)
S
A
RV/RM2211
Min Typ Max Min
RC2211
Parameters
General
Test Conditlons
Typ Max Units
Supply Voltage2
Supply Current
Oscillator
4.5
20
9.0
4.5
20
11
V
R ³ 10 kW
0
4.0
5.0
mA
Frequency Accuracy
Frequency Stability1
Deviation from f = 1/R C
0 0
±1.0 ±3.0
±1.0
%
0
Temperature Coefficient
Power Supply Rejection
R = ¥
±20
±50
±20
ppm/°C
1
+V = 12 ±1V
0.05
0.2
0.5
0.05
%/V
%/V
S
+V = 5 ±0.5V
0.2
S
Upper Frequency Limit
R = 8.2 kW, C = 400 pF
100
300
300
kHz
Hz
0
0
Lowest Practical Operating
Frequency1
R = 2 MW, C = 50 mF
0.01
0.01
0
0
Timing Resistor, R
Operating Range
0
5.0
15
2000 5.0
100 15
2000
100
kW
kW
Recommended Range
Loop Phase Detector
Peak Output Current
Output Offset Current
Output Impedance
Maximum Swing
Measured at pin 11
±150 ±200 ±300 ±100 ±200 ±300
mA
mA
MW
V
±1.0
1.0
±2.0
1.0
Ref. to pin 10
±4.0 ±5.0
±4.0 ±5.0
Quadrature Phase Detector
Peak Output Current3
Output Impedance
Maximum Swing
Measured at pin 3
100
150
1.0
11
150
1.0
11
mA
MW
V
P-P
Input Preamp
Input Impedance
Measured at pin 2
20
20
kW
mV
Input Signal Voltage
2.0
10
2.0
RMS
Required to Cause Limiting3
Voltage Comparator
Input Impedance
Measured at pins 3 & 8
2.0
100
70
2.0
MW
nA
Input Bias Current
Voltage Gain1
100
R = 5.1 kW
L
55
55
70
dB
Output Voltage Low
Output Leakage Current
Internal Reference
Voltage Level
I
= 3mA
300
0.01
300
0.01
mV
mA
C
V = 12V
0
Measured at pin 10
4.9
5.3
5.7
4.75
5.3
5.85
V
Output Impedance
100
100
W
Notes:
1. Guaranteed by design.
2. Individual applications may need special circuitry to function at <12V.
3. Sample tested.
5
PRODUCT SPECIFICATION
RC2211
1. Calculate PLL center frequency, F
F1 + F2
0
Applications
F0 = -----------------
2
FSK Decoding
Figure 2 shows the basic circuit connection for FSK decod-
ing. With reference to Figures 1 and 2, the functions of
2. Choose a value of timing resistor R to be in the range
0
of 10 kW to 100 kW. This choice is arbitrary. The recom-
external components are deÞned as follows: R and C set
0
0
mended value is R = 20 kW. The Þnal value of R ios
0
0
the PLL center frequency, R sets the system bandwidth, and
1
normally Þnetuned with the series potentiometer, R .
X
C sets the loop Þlter time constant and the loop damping
1
factor. C and R form a one pole post-detection Þlter for the
F
F
3. Calculate value of C from Design Equation No. 1 or
0
FSK data output. The resistor R (510 kW) from pin 7 to pin
B
from Typical Performance Characteristics:
8 introduces positive feedback across FSK comparator to
facilitate rapid transition between output logic states.
C = 1/R F
0 0 0
Recommended component values for some of the most
commonly used FSK bauds are given in Table 1.
4. Calculate R to give a Df equal to the markspace
1
deviation:
+V
S
R = R [F /(F - F )]
1
0
0
1
2
0.1 µF
5. Calculate C to set loop damping. (See Design Equation
1
C
0
VCO
Fine Tune
No. 4)
1
2
3
4
5
6
7
14
13
12
11
0.1 µF
FSK
Input
R
0
Normally, z » 1/2 is recommended
R
5K
Then: C = C /4 for z = 1/2
X
1 0
R
1
0.1 µF
R
RC2211
L
10
+VS 5.1K
6. Calculate Data Filter Capacitance, C :
F
C
1
9
For R = 100 kW, R = 510 kW, the recommended value
F
B
FSK Data
Output
8
of C is:
F
R
F
100K
R
B
3
CF (in mF) = ------------------------
65-2211-05
Baud Rate
510K
CF
Note: All calculated component values except RO can be
rounded off to the nearest standard value, and R0 can
be varied to fine-tune center frequency through a series
Figure 2. Circuit Connectbn for FSK Decoding
potentiometer, R (see Figure 2).
X
Table 1. Recommended Component Values
for Commonly Used FSK Bands
(see Circuit of Figure 2)
Design Example
75 Baud FSK demodulator with mark space frequencies of
1110/1170 Hz:
FSK Band
300 Baud
Component Values
C = 0.039 mF, C = 0.005 mF
0
F
Step 1: Calculate F :
0
F = 1070 Hz
1
C = 0.01 mF, R = 18 kW
1 0
F =(1110+1170)(1/2)= 1140Hz
0
F = 1270 Hz
2
R = 100 kW
1
Step 2: Choose R = 20 kW (18 kW Þxed resistor in series
0
300 Baud
C = 0.022 mF, C = 0.005 mF
0 F
with 5 kW potentiometer)
F = 2025 Hz
1
C = 0.0047 mF, R = 18 kW
1 0
F = 2225 Hz
2
R = 200 kW
1
Step 3: Calculate C from VCO Frequency vs. Timing
0
Capacitor: C = 0.044mF
9
1200 Baud
C = 0.027 mF, C = 0.0022 mF
0 F
F = 1200 Hz
C = 0.01 mF, R = 18 kW
1 0
1
Step 4: Calculate R : R = R (1140/60) = 380 kW
1
1
0
F = 2200 Hz
2
R = 30 kW
1
Step 5: Calculate C : C = C /4 = 0.011 mF
1
1
0
Design Instructions
The circuit of Figure 2 can be tailored for any FSK decoding
application by the choice of Þve key circuit components: R ,
Note: All values except R can be rounded off to nearest
0
standard value.
0
R , C , C and C . For a given set of FSK mark and space
1
0
1
F
frequencies, F and F , these parameters can be calculated as
1
2
follows:
6
RC2211
PRODUCT SPECIFICATION
FSK Decoding with Carrier Detector
+V
S
The lock detector section of the RC2211 can be used as a
carrier detector option for FSK decoding. The recommended
circuit connection for this application is shown in Figure 3.
The open-collector lock detector output, pin 6, is shorted to
the data output (pin 7). Thus, the data output will be disabled
at ÒlowÓ state, until there is a carrier within the detection
band of the PLL, and the pin 6 output goes ÒhighÓ to enable
the data output.
0.1 µF
C
0
VCO
Fine Tune
1
2
3
4
5
6
7
14
13
12
11
0.1 µF
FSK
Inputs
R
0
R
X
C
O
R
1
470K
5K
0.1 µF
RC2211
10
C
1
9
+V
S
8
+V
S
R
L1
+V
S
R
0.1 µF
L2
Logic
Output
C
0
Q
VCO
Logic
Outputs
1
2
3
4
5
6
7
14
13
12
11
0.1 µF
Fine Tune
FSK
Q
Inputs
R
65-2211-07
0
Figure 4. Circuit Connection for Tone Detection
Both logic outputs at pins 5 and 6 are open-collector type
stages, and require external pull-up resistors R and R as
shown in Figure 4.
R
C
X
O
R
1
470K
0.1 µF
5K
RC2211
10
9
C
1
L1 L2
8
5.1K
R
F
+V
S
100K
With reference to Figures 1 and 4, the function of the
external circuit components can be explained as follows:
R and C set VCO center frequency, R sets the detection
Data
Output
510K
CF
0
0
1
65-2211-06
bandwidth, C sets the lowpass-loop Þlter time constant and
1
Note: Data output is "low" when no carrier is present.
the loop dampening factor, and R and R are the respec-
L1 L2
Figure 3. External Connections for
FSK Demodulation with Carrier Detector Capability
tive pull-up resistors for the Q and Q logic outputs.
Design Instructions
The minimum value of the lock detector Þlter capacitance
The circuit of Figure 4 can be optimized for any tone-detec-
tion application by the choice of Þve key circuit components:
C
is inversely proportional to the capture range, ±Df .
D
C
This is the range of incoming frequencies over which the
loop can acquire lock and is always less than the tracking
range. It is further limited by C . For most applications,
R , R , C , C and C . For a given input tone frequency, F ,
0
1
0
1
D
S
these parameters are calculated as follows:
1
DF < DF/2. For R = 470 kW, the approximate minimum
C
D
1. Choose R to be in the range of 15 kW to 100 kW.
0
value of C can be determined by:
D
This choice is arbitrary.
C (mF) ³ 16/capture range in Hz
D
2. Calculate C to set center frequency, f equal to
0
0
F : C = 1/R F .
0 S
S
0
With values of C that are too small, chatter can be observed
D
on the lock detector output as an incoming signal frequency
approaches the capture bandwidth. Excessively large values
3. Calculate R to set bandwidth ±DF (see Design Equa-
1
tion No. 5): R = R (F /DF). Note: The total detection
1
0 0
of C will slow the response time of the lock detector
bandwidth covers the frequency range of F ± DF.
0
D
output.
4. Calculate value of C for a given loop damping factor:
1
C =C /16z2
1
0
Tone Detection
Normally z = 1/2 is optimum for most tone detector
applications, giving C = 0.25 C0.
Figure 4 shows the generalized circuit connection for tone
detection. The logic outputs, Q and Q at pins 5 and 6 are
normally at ÒhighÓ and ÒlowÓ logic states, respectively.
When a tone is present within the detection band of the PLL,
the logic state at these outputs becomes reversed to the
duration of the input tone. Each logic output can sink 5 mA
of load current.
1
Increasing C improves the out-of-band signal rejection,
1
but increases the PLL capture time.
5. Calculate value of Þlter capacitor C . To avoid chatter
D
at the logic output, with R = 470W, C must be:
D
D
C (mF) ³ (16/capture range in Hz)
D
Increasing C slows the logic output response time.
D
7
PRODUCT SPECIFICATION
RC2211
Design Examples
Linear FM Detection
Tone detector with a detection band of 1 kHz ±20 Hz:
The RC2211 can be used as a linear FM detector for a wide
range of analog communications and telemetry applications.
The recommended circuit connection for the application is
shown in Figure 5. The demodulated output is taken from the
loop phase detector output (pin 11), through a post detection
Step 1: Choose R = 20 kW (18 kW in series with 5 kW
0
potentiometer) .
Step 2: Choose C for F = 1 kHz: C = 0.05 mF.
0
0
0
Þlter made up of R and C , and an external buffer ampliÞer.
F
F
This buffer ampliÞer is necessary because of the high
impedance output at pin 11. Normally, a non-inverting unity
gain op amp can be used as a buffer ampliÞer, as shown in
Figure 5.
Step 3: Calculate R : R = (R ) (1000/20) = 1 MW.
1
1
0
Step 4: Calculate C : for z = 1/2, C = 0.25 mF,
1
1
C = 0.013 mF.
0
The FM detector gain, i.e., the output voltage change per unit
of FM deviation, can be given as:
Step 5: Calculate C : C = 16/38 = 0.42 mF.
D
D
Step 6: Fine tune the center frequency with the 5 kW
potentiometer. R .
V
OUT
= R V /100 R Volts/% deviation
1 R 0
X
where V is the internal reference voltage. For the choice of
R
external components R , R , C , C and C , see the section
1
0
0
1
F
0.1 µF
0.1 µF
on Design Instructions.
+VS
(1)
(8)
0.1 µF
(2)
FM
Input
(10)
(4)
(13)
RC2211
CO
C
K
(14)
(12) (11)
R
0
+VS
RF
R
1
100K
CF
C
1
Demodulated
Ouput
65-2211-08
Figure 5. Linear FM Detector
Using RC2211 and an External Op Amp
8
RC2211
PRODUCT SPECIFICATION
Typical Performance Characteristics
10
1.0
0.1
20
R = 5 kWŸ
0
R = 10 kWŸ
0
R = 20 kWŸ
0
15
R = 40 kWŸ
0
R
= 5 kW
0
R = 80 kWŸ
0
R = 160 kW
R
0
= 10 kW
0
10
5
R
> 100 kW
0
0
4
6
8
10 12 14 16 18 20 22 24
100
1K
10K
+VS (V)
FO (Hz)
Figure 6. Supply Current vs. Supply Voltage
(Logic Outputs Open Circuited)
Figure 7. Timing Resistor with Timing
Capacitor vs. VCO Frequency
1K
100
10
1.0
0.5
0
1 MW
R
= 10 kWŸ
= 50 kWŸ
0
0
Ÿ
R
Ÿ
500 kW
50 kW
10 kW
-0.5
-1.0
R
0
= 1 MWŸ
Ÿ
R
0
= 500 kWŸ
Ÿ
0
1
10
0
-50
-25
+25
+50 +75 +100 +125
F
O (Hz)
Temperature (¡C)
Figure 8. Timing Capacitor with Timing
Resistor vs. VCO Frequency
Figure 9. Center Frequency Drift vs. Temperature
1.02
1.01
1.00
0.99
0.98
0.97
Curve
R0
5K
10K
30K
100K
300K
1
2
3
4
5
F
R
O = 1 kHz
10 R0
4
6
8
10 12 14 16 18 20 22 24
-VS (V)
Figure 10. VCO Frequency vs. Supply Voltage
9
PRODUCT SPECIFICATION
RC2211
Schematic Diagram
10
RC2211
PRODUCT SPECIFICATION
Notes:
11
PRODUCT SPECIFICATION
RC2211
Notes:
12
RC2211
PRODUCT SPECIFICATION
Notes:
13
PRODUCT SPECIFICATION
RC2211
Mechanical Dimensions
14-Lead Ceramic DIP Package
Notes:
Inches
Millimeters
Min. Max.
Symbol
Notes
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
Min.
Max.
A
—
.200
.023
.065
.015
.785
.310
—
.36
1.14
.20
—
5.08
.58
2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads
number 1, 7, 8 and 14 only.
b1
b2
c1
D
.014
.045
.008
—
8
2
1.65
.38
3. Dimension "Q" shall be measured from the seating plane to the base
plane.
8
4
19.94
7.87
4. This dimension allows for off-center lid, meniscus and glass overrun.
E
.220
5.59
4
5. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 14.
5, 9
7
e
.100 BSC
.300 BSC
2.54 BSC
7.62 BSC
eA
L
.125
.200
.060
—
3.18
5.08
1.52
—
6. Applies to all four corners (leads number 1, 7, 8, and 14).
Q
s1
a
.015
.005
90¡
.38
.13
90¡
3
6
7. "eA" shall be measured at the center of the lead bends or at the
centerline of the leads when "a" is 90¡.
105¡
105¡
8. All leads – Increase maximum limit by .003 (.08mm) measured at the
center of the flat, when lead finish applied.
9. Twelve spaces.
D
1
7
8
NOTE 1
E
14
s1
eA
e
A
Q
c1
a
L
b1
b2
14
RC2211
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
14-Lead Plastic DIP Package
Notes:
Inches
Millimeters
Min. Max.
Symbol
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Min.
Max.
2. "D" and "E1" do not include mold flashing. Mold flash or protrusions
shall not exceed .010 inch (0.25mm).
A
—
.210
—
—
.38
5.33
—
A1
A2
B
.015
.115
.014
.045
.008
.725
.005
.300
.240
3. Terminal numbers are shown for reference only.
4. "C" dimension does not include solder finish thickness.
5. Symbol "N" is the maximum number of terminals.
2.93
.36
.195
.022
.070
.015
.795
—
4.95
.56
B1
C
1.14
.20
1.78
.38
4
2
D
18.42
.13
20.19
—
D1
E
.325
.280
7.62
6.10
8.26
7.11
E1
e
2
5
.100 BSC
2.54 BSC
eB
L
—
.430
.200
—
10.92
5.08
.115
2.92
N
14
14
D
1
7
E1
D1
8
14
E
e
A
A1
C
L
eB
B1
B
15
PRODUCT SPECIFICATION
RC2211
Ordering Information
Part Number
RC2211N
Package
Operating Temperature Range
0°C to +70°C
N
N
D
D
RV2211N
-25°C to +85°C
RM2211D
-55°C to +125°C
RM2211D/883B
-55°C to +125°C
Notes:
/883B suffix denotes MIL-STD-883, Par 1.2.1 Compliant Devices
N = 14-Lead Plastic DIP
D = 14-Lead Ceramic DIP
The information contained in this data sheet has been carefully compiled; however, it shall not by implication or otherwise become part of the
terms and conditions of any subsequent sale. RaytheonÕs liability shall be determined solely by its standard terms and conditions of sale.
No representation as to application or use or that the circuits are either licensed or free from patent infringement is intended or implied.
Raytheon reserves the right to change the circuitry and any other data at any time without notice and assumes no liability for errors.
LIFE SUPPORT POLICY:
RaytheonÕs products are not designed for use in life support applications, wherein a failure or malfunction of the component can reasonably
be expected to result in personal injury. The user of Raytheon components in life support applications assumes all risk of such use and
indemniÞes Raytheon Company against all damages
Raytheon Electronics
Semiconductor Division
350 Ellis Street
Mountain View CA 94043
415 968 9211
FAX 415 966 7742
12/95 0.0m
Stock#DS20002211
Ó Raytheon Company 1995
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