RD-19230F-203T_技术文档

RD-19230

16-BIT MONOLITHIC TRACKING

RESOLVER-TO-DIGITAL CONVERTER

DESCRIPTION

FEATURES

The RD-19230 is a versatile, low cost, range of ±4 V relative to analog ground.

state-of-the-art 16-bit monolithic Resolver- The velocity scale factor/tracking rate is

to-Digital Converter. This single chip con- programmed with a single resistor. This

verter offers programmable features such converter provides the option of using a

as resolution, bandwidth, velocity output second set of filter components which can

Accuracy up to 2.3 arc minutes

Internal Synthesized Reference

+5 Volt Only Option

•

scaling and encoder emulation.

be used in dual bandwidth or switch on the

fly applications.

Programmable Resolution,

Bandwidth and Tracking Rate

Resolution programming allows selec-

tion of 10, 12, 14, or 16-bit, with accura- The RD-19230 is available with operating

cies to 2.3 min. The parallel digital data temperature ranges of 0° to +70°C and

and the internal encoder emulation sig- -40° to +85°C.

Internal Encoder Emulation with

Independent Resolution Control

•

Differential Resolver Input

Mode

nals (A QUAD B) have independent res-

olution control. Internal encoder emula-

tion will permit inhibiting (freezing) the

APPLICATIONS

Velocity Output Eliminates

Tachometer

parallel digital data without interrupting With its low cost, small size, high accura-

the A and B outputs.

cy, and versatile performance, the RD-

19230 converter is ideal for use in modern

Built-In-Test (BIT) Output,

No 180° Hangup

The internal Synthesized Reference sec- high performance industrial control sys-

tion eliminates errors due to quadrature tems. It is ideal for users who wish to use

voltage and ensures operation with a a resolver input in their encoder based

rotor-to-stator phase shift of up to 45 system. Typical applications include motor

degrees. The velocity output (VEL) can control, machine tool control, robotics, and

be used in place of a tachometer. It has a process control.

-40° to +85°C Operating

Temperature

C

bw

R

b

C

bw/

10

V

E

L

V

E

L

R

b

C

bw

S

J

1

S

J

2

RH

RL BIT

C

bw/

10

VEL2 VEL1

SYNTHESIZED

REFERENCE

SHIFT

SIN

-S

-

+

+S

COS

-C

CONTROL

TRANSFORMER

GAIN

-

DEMODULATOR

VEL

-

+

D1 D0

+

+C

R

V

D1

D0

HYSTERESIS

16 BIT

UP/DOWN

COUNTER

VDDP

PCAP

NCAP

VSSP

-5 V

INVERTER

VCO

&

-VCO

TIMING

R CLK

A GND

VDD

INTERNAL

ENCODER

EMULATION

DATA

LATCH

R SET

GND

VSS

EM

EL

INH

D1 D0

A QUAD B A U/B

UP/DN

CB/ZIP

ZIP_EN

BIT 1 - BIT 16

FIGURE 1. RD-19230 SERIES BLOCK DIAGRAM

1999, 2000 Data Device Corporation

©

TABLE 1. RD-19230 SPECIFICATIONS (CONTINUED)

TABLE 1. RD-19230 SPECIFICATIONS

These specs apply over the rated power supply, temperature, and refer-

ence frequency ranges; 10% signal amplitude variation, and 10% har-

monic distortion.

PARAMETER

UNIT

VALUE

DIGITAL OUTPUTS

Parallel Data (1-16)

10, 12, 14, or 16 parallel lines;

natural binary angle positive

logic (see note 2)

0.25 to 0.75 µs positive pulse

leading edge initiates counter

update. (CB functions with

ZIP_EN pin tied to +5 V or NC)

Logic 1 at all 0’s

(ZIP_EN pin tied to GND)

Logic 0 for BIT condition.

~ ±100 LSB’s of error with a fil-

ter of 500 µs, Loss of Signal

(LOS) less than 500 mV, or

Loss of Reference (LOR) less

than 500 mV

PARAMETER

RESOLUTION

UNIT

VALUE

Bits 10, 12, 14, or 16 (note 1 & 2)

Converter Busy (CB)

(4)

FREQUENCY RANGE

ACCURACY -XX2

-XX3 (note 3)

REPEATABILITY

Hz

47-1k

1k - 4k 4k - 10k

Min

LSB

4 +1 LSB 4 +1 LSB 5 +1 LSB

2 +1 LSB 2 +1 LSB 3 +1 LSB

Zero Index Pulse (ZIP)

Built-In-Test (BIT)

±1

± 2

DIFFERENTIAL LINEARITY LSB

REFERENCE

Type

(+REF, -REF)

Differential

Voltage: differential

single ended

overload

Vp-p ±10 max.

Vp ±5 max.

Vrms ±25 continuous; ±100 transient

Hz DC to 10k

Frequency

A, B

Incremental Encoder Output

50 pF+

Ω

Input Impedance

10M min. || 20 pf

Drive Capability

SYNTHESIZED REFERENCE

±Sig/Ref Phase Shift Correction deg 45 max. from 400 Hz to 10kHz

(note 5)

Logic 0: 1 TTL load, 1.6 mA at

0.4 V max.

Logic 1; 10 TTL loads, -0.4 mA

at 2.8 V min.

Logic 0; 100 mV max. driving

CMOS

Logic 1; +5 V supply minus

100 mV min. driving CMOS

High Z; 10 µA || 5 pF max.

SIGNAL INPUT

Type

(+S, -S, SIN, +C, -C, COS)

Resolver, differential,

groundbased

Voltage: operating

overload

Input impedance

Vrms 2 ±15%

Vrms ±25 continuous

Ω

10M min || 10 pF.

DIGITAL INPUTS

TTL / CMOS Compatible

Inputs

DYNAMIC

CHARACTERISTICS

Resolution

(at maximum bandwidth)

Logic 0 = 0.8 V max.

Logic 1 = 2.0 V min.

Loading = 10 µA max P.U. cur-

rent source to +5 V || 5 pF max.

CMOS transient protected

bits

10

12

14

16

Tracking Rate (min)(note 6)

Bandwidth (Closed Loop)

Ka

A1

A2

A

B

rps

Hz

1152 288

72

18

1200 1200 600

300

2

1/sec

5.7M 5.7M 1.4M 360k

19.5 19.5 4.9 1.2

295k 295k 295k 295k

Inhibit (INH)

Logic 0 inhibits; Data stable with-

in 150 ns

2400 2400 1200

1200 1200 600

600

300

2k

Enable Bits 1 to 8 (EM)

Enable Bits 9 to 16 (EL)

Logic 0 enables; Data stable

within 150 ns

Logic 1 = High Impedance; Data

High Z within 100 ns

2

Acceleration (1 LSB lag)

Settling Time (179° step)

2M

2

500k 30k

20

deg/s

msec

8

50

VELOCITY

CHARACTERISTICS

Polarity

Resolution and Mode

Control (D1 & D0)

(See notes 1 & 2)

Mode D1 D0 Resolution

Positive for increasing angle

±4 (at nominal power supply)

resolver

0

1

0

1

0

1

0

10 bits

12 bits

14 bits

16 bits

8 bits

Voltage Range (Full Scale)

Scale Factor Error

Scale Factor TC

Reversal Error

Linearity

Zero Offset

Zero Offset TC

Load

V

%

10 typ

100 typ

0.75 typ

0.25 typ

5 typ

20 max

200 max

1.3 max

0.50 max

10 max

30 max

8 max

PPM/°C

%

mV

µV/°C

kΩ

LVDT -5V

0

1

-5V

10 bits

12 bits

14 bits

15 typ

-5V -5V

Logic 0 enables ZIP

Logic 1 enables CB

ZIP_EN

POWER SUPPLIES

Nominal Voltage

Voltage Range

Max Volt. w/o Damage

Current

(note 6)

V

%

V

+5 (VDD)

-5 (VSS)

±5

+7

±5

-7

CMOS Compatable Inputs

Logic 0 = 1.5 V max.

Logic 1 = 3.5 V min.

negative voltage = -3.5 V min.

Logic 1 select VEL1 components

Logic 0 select VEL2 components

mA

25 max. (each)

TEMPERATURE RANGE

Operating

-30X

-20X

Storage

SHIFT

UP/DN

°C

0 to +70

-40 to +85

Logic 1 will increase gain by 4

Logic 0 will decrease gain by 4

-5 V gain remains constant

PHYSICAL

CHARACTERISTICS

Size: 64-pin Quad Flat Pack in(mm)

WEIGHT

A QUAD B

Logic 0 enables encoder emulation

Falling edge latches encoder

resolution

0.52 x 0.52 (13.2 x 13.2)

0.018 ( 0.5 )

oz(g)

Data Device Corporation

www.ddc-web.com

RD-19230

2

TABLE 1 notes:

1. Unused data bits are set to logic “0.”

clamps to the ±5 VDC supplies. By performing the following

trigonometric identity, SINθ(COSφ) - COSθ(SINφ) = SIN(θ-φ),

the Control Transformer (CT) compares the analog input signals

( θ ) with the digital output ( φ ), resulting in an error signal pro-

portional to the sin of the angular difference. The CT uses a

combination of amplifiers, switches, logic and capacitors in pre-

cision ratios to perform the calculation.

2. In LVDT mode, Bit 3 is the MSB and resolution is

programmable to 8,10, 12, and 14 bits.

3. Accuracy in LVDT mode is 0.15% + 1 LSB of full scale.

4. In the frequency range of 47Hz to 1kHz, there will be

1 LSB of jitter at quadrant boundaries.

5. The maximum phase shift tolerance will degrade linearly

from 45 degrees at 400 Hz to 30 degrees at 60 Hz.

6. When using the -5V inverter, the V_DDsupply current will

double and V_SSPcan be up to 20% low, or -4V.

7. || = in parallel with.

Note:The error output of the CT is normally sinusoidal, but

in LVDT mode, it is triangular (linear) and can be used to

convert any linear transducer output.

The converter accuracy is limited by the precision of the com-

puting elements in the CT. Instead of a traditional precision

resistor network, this converter uses capacitors with precisely

controlled ratios. Sampling techniques are used to eliminate

errors due to voltage drift and op-amp offsets.

THEORY OF OPERATION

The RD-19230 is a mixed signal CMOS IC containing analog

input and digital output sections. Precision analog circuitry is

merged with digital logic to form a complete high-performance

tracking resolver-to-digital converter. For user flexibility and con-

venience, the converter bandwidth, dynamics, and velocity scal-

ing are externally set with passive components.

The error processing is performed using the industry standard

technique for Type II tracking converters. The DC error is inte-

grated yielding a velocity voltage which in turn drives a voltage

controlled oscillator (VCO). This VCO is an incremental integra-

tor (constant voltage input to position rate output) which, togeth-

er with the velocity integrator, forms a Type II servo feedback

loop. A lead in the frequency response is introduced to stabilize

the loop and another lag at higher frequency is introduced to

reduce the gain and ripple at the carrier frequency and above.

The settings of the various error processor gains and break fre-

quencies are done with external resistors and capacitors so that

the converter loop dynamics can be easily controlled by the user.

FIGURE 1 is the Functional Block Diagram of RD-19230. The

analog conversion electronics require ±5 VDC power supplies,

and the converter contains a charge pump to provide the user

with the option of a single-ended +5 VDC supply. The converter

front-end consists of differential sine and cosine input amplifiers

which are protected up to ±25 V with 2 kΩ resistors and diode

C

R

BW

B

VEL

C

/10

R

V

BW

VEL SJ1

VEL

-VCO

50 pf

C

VCO

CT

R

1

16 BIT

UP/DOWN

COUNTER

RESOLVER

INPUT

(θ)

+

VCO

GAIN

DEMOD

1

±1.25 V

THRESHOLD

-

C

F

S

11 mV/LSB

DIGITAL

OUTPUT

(φ)

H = 1

FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1

3

Data Device Corporation

www.ddc-web.com

RD-19230

TRANSFER FUNCTION AND BODE PLOT

GENERAL SETUP CONDITIONS

The dynamic performance of the converter can be determined

from its Transfer Function Block Diagrams and Bode Plots (open

and closed loop). These are shown in FIGURES 2, 3, and 4.

DDC has external component selection software which consid-

ers all the criteria below. In a simple fashion, it asks the key sys-

tem parameters (carrier frequency, resolution, bandwidth, and

tracking rate) needed to derive the external component values.

The open loop transfer function is as follows:

The following recommendations should be considered when

installing the RD-19230 R/D converter:

S

A²

S²

+1

(_B)

Open Loop Transfer Function =

S

1) In setting the bandwidth (BW) and Tracking Rate (TR) (select-

ing five external components), the system requirements need to

be considered. For the greatest noise immunity, select the mini-

mum BW and TR the system will allow. Selecting a f_BWthat is

too low relative to the maximum application tracking rate can cre-

ate a spin-around condition in which the converter never settles.

The relationship to insure against this condition is detailed in

TABLE 2.

+1

(_10B)

where A is the gain coefficient and A²=A₁A₂

and B is the frequency of lead compensation.

The components of gain coefficient are error gradient, integrator

gain, and VCO gain. These can be broken down as follows:

TABLE 2. TRACKING/BW RELATIONSHIP

- Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod

with 2 Vrms input)

RPS (MAX)/BW

RESOLUTION

1

10

12

14

16

Cs Fs

1.1 CBW

- Integrator Gain =

- VCO Gain =

volts per second per volt

LSBs per second per volt

0.50

0.25

0.125

1

1.25 RV CVCO

where: Cs = 10 pF

2) Power supplies are ±5 VDC. For lowest noise performance it

is recommended that a 0.1 µF or larger cap be connected from

each supply to ground near the converter package.

Fs = 67 kHz when R CLK = 30 kΩ

CVCO = 50 pF

R_V, R_B, and C_BWare selected by the user to set velocity scaling

and bandwidth.

3) Resolver inputs and velocity output are referenced to AGND.

This pin should be connected to GND near the converter pack-

age. Digital currents flowing through ground will not disturb the

analog signals.

(CRITICALLY DAMPED)

GAIN = 4

2A

VELOCITY

OUT

ω (rad/sec)

10B

OPEN LOOP

B

A

-6 db/oct

ERROR PROCESSOR

VCO

(B = A/2)

CT

S

B

A

S

+ 1

1

A

S

DIGITAL

POSITION

OUT (φ)

+

2

RESOLVER

INPUT

(θ)

e

GAIN = 0.4

S

10B

+ 1

-

2 A

π

f_BW= BW (Hz) =

H = 1

2A

2

2 A

ω (rad/sec)

CLOSED LOOP

FIGURE 3. TRANSFER FUNCTION

BLOCK DIAGRAM #2

FIGURE 4. BODE PLOTS

Data Device Corporation

www.ddc-web.com

RD-19230

4

4) This device has several high impedance amplifier inputs

(+C, -C, +S, -S, -VCO, VEL SJ1, and VEL SJ2) that are sensitive

to noise coupling. External components should be connected as

close to the converter as possible.

4 V

- Rv =

= 97655 Ω

10 rps x 2¹⁶x 50 pF x 1.25 V

3.2 x 67 kHz x 10⁸

- Compute CBW (pF) =

= 21955 pF

97655 x 100 Hz²

5) Setup of bandwidth and velocity scaling for the optimized crit-

ically damped case should proceed as follows:

0.9

- Compute RB =

= 410 kΩ

21955 x 10 ^-12x 100 Hz

- Select the desired f BW (closed loop) based on overall

system dynamics.

TABLE 3. MAX TRACKING RATE (MIN) IN RPS

- Select f

≥ 3.5f BW

carrier

RESOLUTION

R SET

R CLK

(Ω)

10

12 14 16

1152 288 72 18

1728 432 108 27

- Select the applications tracking rate (in accordance with TABLE 3),

and use appropriate values for R SET and R CLK

30k** or open

30k

20k

15k

23k

Full Scale Velocity Voltage

2304 576

*

- Compute Rv =

resolution

Tracking Rate (rps) x 2

x 50 pF x 1.25 V

* Not recommended.

** The use of a high quality thin-film resistor will provide better temperature

stability than leaving open.

3.2 x Fs (Hz) x 10⁸

- Compute CBW (pF) =

Rv x (f BW)²

- Where Fs = 67 kHz for R CLK = 30 KΩ

100 kHz for R CLK = 20 KΩ

+5V

125 kHz for R CLK = 15 KΩ

33

58

27

V^DD

0.9

CBW x f BW

- Compute RB =

VDD

VDDP

26

PCAP

CBW

- Compute

10

+

RD-19230

10 µF/10V

24

NCAP

23

16

V^SSP

V^SS

As an example:

17

VSS

47 µF/10V

Calculate component values for a 16 bit converter with 100Hz

bandwidth, a tracking rate of 10 RPS and a full scale velocity

of 4 Volts.

+

25

22

GND

AGND

FIGURE 5. -5V INVERTER CONNECTIONS

Data Device Corporation

www.ddc-web.com

RD-19230

5

INPUT TRANSFORMERS

6) Using the -5V Inverter will eliminate the need for a -5 V sup-

ply. Refer to FIGURE 5. for the necessary connections.

Refer to TABLE 5 to select the proper transformer for Reference,

Synchro and Resolver inputs.

When using the built-in -5 V inverter, the maximum tracking rate

should be scaled for a full-scale velocity output of 3.5 V max.

Note: Use of the -5 V inverter is not recommended for appli-

cations that require the highest BW and Tracking Rates.

TABLE 5. TRANSFORMERS

INPUT

SIGNAL

TYPE

INPUT

VOLTAGE

(Vrms)

INPUT

FREQUENCY

(HZ)

FIGURE

on

PAGE

PART

NUMBER

Synchro

11.8

90

400

60

52034

52035

52036

52037

52038

B-426*

52039**

24133**

6 on pg 7

7 on pg 7

8 on pg 8

9 on pg 8

TABLE 4. CARRIER FREQUENCY (MAX)

IN KHZ

RESOLUTION

R SET

R CLK

Resolver

Reference

Synchro

11.8

(Ω)

10

12

10

14

7

16

5

26

30k** or open

30k

20k

15k

23k

10

*

7

90

10

*

Reference

Synchro

Reference

* Not recommended.

** The use of a high quality thin-film resistor will provide better temperature

stability than leaving open.

Reference

60

*

Beta Transformer

** 60 Hz synchro transformers are active (require ±15V DC power supplies) and

are available in two temperature ranges; -1: -55° to +125° and -3: 0° to + 70°.

HIGHER TRACKING RATES AND CARRIER

FREQUENCIES.

Maximum tracking rate is limited by the velocity voltage satura-

tion (nominally 4 V) and the maximum internal clock rate (nomi-

nally 1,333,333 Hz for R CLK = 30k). To achieve higher tracking

rates, a higher internal counting rate must be programmed by

setting RCLK to a value less than 30k. See TABLE 4. for the

appropriate values.

The Rv resistor and an internal 50pF cap are configured as an

integrating circuit that resets to zero after a count occurs in either

direction. This circuit acts as a VCO with velocity as its input and

CB as its output. The Rv resistor and an internal 50pF cap deter-

mine the maximum rate of the VCO. Rv must be chosen such

that the maximum rate of the VCO is less than the maximum

internal clock rate. Choose the tracking rate in accordance with

TABLE 3 to insure this relationship. The rates shown in TABLE

3 are based on ~90% of the nominal internal clock rate.

The relationship between the velocity voltage and the VCO rate

is given by:

1

Velocity Voltage

VCO Frequency

=

(Rv x 50 pF x 1.25)

Data Device Corporation

www.ddc-web.com

RD-19230

6

0.61 MAX

(15.49)

0.61 MAX

(15.49)

0.15 MAX

(3.81)

0.09 MAX

(2.29)

0.30 MAX

(7.62)

0.09 MAX

(2.29)

0.15 MAX

(3.81)

1

3

T1A

8

4

7

5

6

11 12

14 15

0.81 MAX

(20.57)

T1B

0.600

(15.24)

10

9

20 19 18 17 16

0.115 MAX

(2.92)

SIDE VIEW

0.100 (2.54) TYP

TOL NON CUM

BOTTOM VIEW

TERMINALS

0.025 –0.001 (6.35 –0.03) DIAM

0.125 (3.18) MIN LENGTH

SOLDER PLATED BRASS

PIN NUMBERS FOR REF. ONLY

Dimensions are shown in inches (mm).

T1A

1

6

-SIN

S1

S3

5

3

10

+SIN

SYNCHRO

INPUT

RESOLVER

OUTPUT

T1B

11

16

20

-COS

15

+COS

S2

FIGURE 6. TRANSFORMER LAYOUT AND SCHEMATIC (SYNCHRO INPUT - 52034/52035)

0.61 MAX

(15.49)

0.61 MAX

(15.49)

0.15 MAX

(3.81)

0.09 MAX

(2.29)

0.30 MAX

(7.62)

0.09 MAX

(2.29)

0.15 MAX

(3.81)

1

3

T1A

8

4

5

6

11 12

14 15

0.81 MAX

(20.57)

T1B

0.600

(15.24)

10

9

7

20 19 18 17 16

0.115 MAX

(2.92)

SIDE VIEW

0.100 (2.54) TYP

TOL NON CUM

BOTTOM VIEW

TERMINALS

0.025 –0.001 (6.35 –0.03) DIAM

0.125 (3.18) MIN LENGTH

SOLDER PLATED BRASS

PIN NUMBERS FOR REF. ONLY

Dimensions are shown in inches (mm).

T1A

1

6

-SIN

S1

S3

3

10

+SIN

RESOLVER

INPUT

RESOLVER

OUTPUT

T1B

11

16

20

-COS

S4

S2

15

+COS

FIGURE 7. TRANSFORMER LAYOUT AND SCHEMATIC (RESOLVER INPUT - 52036/52037/52038)

Data Device Corporation

www.ddc-web.com

RD-19230

7

CASE IS BLACK AND

NON-CONDUCTIVE

0.25

(6.35)

MIN.

0.61 MAX

(15.49)

0.32 MAX

(8.13)

1.14 MAX

(28.96)

0.125 MIN

(3.17)

0.09 MAX

(2.29)

0.15 MAX

(3.81)

+

•

S3

S1

+15 V

+S

*

(+15 V) (-R)

*

1

2

9

3

T1A

8

5

6

0.600

(15.24)

0.81 MAX

(20.57)

1.14 MAX

(28.96)

0.85 ±0.010

(21.59 ±0.25)

52039

or

24133

10

7

0.105 (2.66)

SIDE VIEW

0.100 (2.54) TYP

TOL NON CUM

BOTTOM VIEW

(RH)

S2

•

(RL)

(V)

V

•

(+R)

+C

•

(-Vs)

-Vs

•

TERMINALS

*

0.025 ±0.001 (6.35 ±0.03) DIAM

0.125 (3.18) MIN LENGTH

SOLDER-PLATED BRASS

+

(BOTTOM VIEW)

0.42

(10.67)

MAX.

0.13 ±0.03

(3.30 ±0.76)

Dimensions are shown in inches (mm).

0.21 ±0.3

(5.33 ±0.76)

0.175 ±0.010 (4.45 ±0.25)

NONCUMULATIVE

TOLERANCE

0.040 ±0.002 DIA. PIN.

SOLDER PLATED BRASS

1

6

INPUT

OUTPUT

5

10

The mechanical outline is the same for the synchro input trans-

former (52039) and the reference input transformer (24133),

except for the pins. Pins for the reference transformer are shown

in parenthesis ( ) below. An asterisk * indicates that the pin is

omitted.

FIGURE 9. 60 HZ SYNCHRO AND REFERENCE

TRANSFORMER DIAGRAMS

(SYNCHRO INPUT - 52039 / REFERENCE INPUT - 24133)

FIGURE 8. TRANSFORMER LAYOUT AND SCHEMATIC

(REFERENCE INPUT - B-426)

TYPICAL INPUTS

FIGURES 10 through 14 illustrate typical input configurations.

EXTERNAL

REFERENCE

LO HI

6

1

B-426

10

5

RH

RL

RESOLVER INPUT OPTION

S1

-S SIN

+S

-R +R

1

10

TIA

S3

S4

6

3

+C

-C

RD-19230

11

15

20

TIB

S2

COS

AGND

16

52036(11.8V)

OR

52037(26V)

OR

GND

52038(90V)

OR

SYNCHRO INPUT OPTION

RH

RL

S1

+S

1

3

10

S3

TIA

TIB

6

5

+C

20

11

S2

15

16

52034(11.8V)

OR

52037(90V)

FIGURE 10. TYPICAL TRANSFORMER CONNECTIONS

Data Device Corporation

www.ddc-web.com

RD-19230

8

EXTERNAL

REF

LO HI

R

1

2

4

R

3

RL RH

See Note 3.

+S

-S

S3

S1

SIN

COS

-C

+C

See Note 3.

S2

S4

A GND

GND

RESOLVER

Notes:

1) Resistors selected to limit Vref peak to between 1.5 V and 4 V.

2) External reference LO is grounded, then R3 and R4 are not

needed, and -R is connected to GND.

3) 10k ohms, 1% series current limit resistors are recommended.

FIGURE 11. TYPICAL CONNECTIONS, 2 V RESOLVER, DIRECT INPUT

R

1

-S

SIN

S3

S1

+S

R

2

R

1

S2

S4

+C

2

A GND

GND

-C

COS

2

R

2

=

X Volt

R + R

1

2

R + R should not load the Resolver; it is recommended to use a R = 10 kΩ

1

2

R + R Ratio erros will result in Angular errors,

1

2

2 cycle, 0.1% Ratio error = 0.029 Peak Error.

FIGURE 12. TYPICAL CONNECTIONS, X- VOLT RESOLVER, DIRECT INPUT

Data Device Corporation

www.ddc-web.com

RD-19230

9

SIN

3

R

f

R

i

-S

1

6

-

S1

S3

2

5

+S

+

f

4

RESOLVER

INPUT

A GND

COS

13

R

i

-C

15

16

7

-

S4

S2

+C

+

8

10

R

f

12

CONVERTER

S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to GND at the converter.

For DDC-49530: R = 70.8 KΩ, 11.8 V input, synchro or resolver.

i

For DDC-49590: R = 270 KΩ, 90 Volt input, synchro or resolver.

i

Maximum additional error is 1 minute.

When using discrete resistors: Resolver L-L voltage =

R

i

f

x 2 Vrms, where R ≥ 6 kΩ

f

FIGURE 13. DIFFERENTIAL RESOLVER INPUT, USING DDC-49530 (11.8 V) OR DDC-49590 (90 V)

SIN

3

R

f

R

i

-S

1

6

-

S1

S3

2

5

R

i

+S

+

R

f

4

A GND

SYNCHRO

INPUT

COS

14

R

i

16

7

R /

f

3

8

15

-C

15

-

R /2

i

+C

10

9

+

S2

R /

f

3

11

CONVERTER

S1, S2, S3 should be triple twisted shielded; RH and RL should be twisted shielded;

In both cases the shield should be tied to GND at the converter.

11.8 Volt input = DDC-49530: R = 70.8 KΩ, 11.8 V input, synchro or resolver.

i

90 Volt input = DDC-49590: R = 270 KΩ, 90 Volt input, synchro or resolver.

i

Maximum additional error is 1 minute.

When using discrete resistors: Resolver L-L voltage =

R

i

f

x 2 Vrms, where R ≥ 6 kΩ

f

FIGURE 14. SYNCHRO INPUT, USING DDC-49530 (11.8 V) OR DDC-49590 (90 V)

Data Device Corporation

www.ddc-web.com

RD-19230

10

UP/DN

DC INPUTS

As noted in TABLE 1, on page 2, the RD-19230 will accept DC

inputs. It is necessary to set the REF input to DC by tying RH to

+5 V and RL to GND or -5 \/.

The UP/DN input selects the gain of the amplifier driving the de-

selected set of bandwidth components. UP/DN has three input

states. See TABLE 6 to relate input to gain.

VELOCITY TRIMMING

TABLE 6. PRECHARGE AMPLIFIER

GAIN PROGRAMMING

RD-19230 specifications for velocity scaling, reversal error, and

offset are listed in TABLE 1. Velocity scaling and offset are exter-

nally trimmable for applications requiring tighter specifications

than those available from the standard unit. FIGURE 15 shows

the setup for trimming these parameters with external pots. It

should also be noted that when the resolution is changed, VEL

Scaling is also changed.

UP/DN

Logic 1

Logic 0

-5 V

GAIN

4

1/4

1

BENEFIT OF SWITCHING RESOLUTION ONTHE FLY

OPTIONAL BANDWIDTH COMPONENTS

Switching resolution on the fly can be used in applications that

require high resolution for accurate position control, and tracking

rates or settling times that are faster than the high resolution

mode will allow.

The RD-19230 provides the option of using a second set of

bandwidth components. The second set of components can be

used for switch-on-the-fly or dual-bandwidth applications. The

SHIFT and UP/DN inputs are used when switching bandwidth

components, and their operation is described below. Refer to the

block diagram, FIGURE 1, on page 1.

The RD-19230 can track four times faster for each step down in

resolution (i.e., a step from 16 bits to 14 bits). The velocity out-

put will be scaled down by a factor of four with each step down

in resolution. For example, if the velocity output is scaled such

that 4 Volts = 10 RPS in 16 bit resolution, then the same con-

verter will output 1 Volt for 10 RPS in 14 bit resolution. To avoid

glitches in the velocity output, the second set of bandwidth com-

ponents can be pre-charged to the expected voltage, and

switched in using the SHIFT input at the same time the resolu-

tion is changed. This will allow for a smooth velocity transition,

resulting in reduced errors and minimal settling time after the

change.

SHIFT

The SHIFT pin is an input that chooses between the VEL1 and

VEL2 bandwidth components. This pin has an internal pull-up to

+5V. When the SHIFT pin is left open, or a logic 1 is applied, the

VEL1 components are selected. When a Logic 0 is applied, the

VEL2 components are selected. The deselected set of band-

width components are driven by an amplifier, with programmable

gain, that follows the velocity amplifier. This amplifier can be

used to pre-charge the deselected set of components to the volt-

age level that is expected after a change in resolution. (See

description on BENEFIT OF SWITCHING RESOLUTION ON

THE FLY.)

FIGURE 17, on page 12, shows the way the converter behaves

during a change in resolution while tracking at a constant veloc-

ity. The first illustration shows the benefits of switching in pre-

charged components while changing resolution. The second

illustration shows the result without the benefits of switching on

the fly.

+5 V

100 R

V

The signals that have been recorded are:

1) VEL: velocity output pin on the RD-19230

2

100 kΩ

-VCO

(OFFSET)

-5 V

0.8 R

V

RD-19230

2) ERROR: this is the analog representation of the error between

the input and the output of the RD-19230

0.4 R (SCALING)

V

1

3) D0: an input resolution control line to the RD-19230

4) BIT: built-in-test output pin of the RD-19230

VEL

FIGURE 15. VELOCITY TRIMMING

Data Device Corporation

www.ddc-web.com

RD-19230

11

When this system uses the switch resolution on the fly imple-

mentation, the velocity signal immediately assumes the pre-

charged level of the second set of components, resulting in small

errors and reduced settling times. Notice that the BIT output,

in FIGURE 17, does not indicate a fault condition.

(UP/DN logic 1), the gain should be set to 1/4. The gain of the

pre-charge amplifier should be programmed prior to switching

the resolution of the converter, allowing enough time for the com-

ponents to settle to the pre-charged level. This time will depend

on the time constant of the bandwidth components being

charged. If switching is limited to two adjacent resolutions (i.e.,

14 and 16) then the pre-charge amplifier can be set up to con-

tinuously maintain the appropriate velocity voltage on the dese-

lected components, resulting in the fastest possible switching

times. See FIGURE 16 for an example of the input wiring con-

nections necessary for switching on the fly between 14 and 16

bit resolution.

When this system type does not use the switch resolution on the

fly implementation, large errors and increased settling times

result. The errors exceed 100 LSBs causing the BIT to flag for a

fault condition.

SWITCH ONTHE FLY IMPLEMENTATION

DUAL BANDWIDTHS

The following steps detail switching resolution on the fly.

1) The SHIFT pin should be controlled synchronously with the

change in resolution. When shift is logic high, the VEL1 compo-

nents will be selected. When shift is logic 0, the VEL2 compo-

nents will be selected.

With the second set of BW component pins, the user can set two

bandwidths for the RD-19230 and choose between them. To use

two bandwidths, proceed as follows:

2) The second set of BW components (C_BW2, R_B2, C_BW2/10

should typically be of the same value as the first set (C_BW1, R_B1

_BW1/10,) and should be installed on VEL₂and VEL SJ₂.

)

,

With Switch Resolution on the Fly Implemented

C

VEL ^0V

Note: Each set of bandwidth components must be chosen to

insure that the tracking rate to BW ratio (listed in TABLE 2,

on page 4) is not exceeded for the resolution in which it will

be used.

-5V

0°

ERROR

5V

D0

3) UP/DN will program the direction of the gain. If the resolution

is increasing (UP/DN logic 0), the gain of the pre-charge amplifi-

er should be set to four. If the resolution is decreasing

0V

5V

BIT

0V

ERROR = 13.6 LSBs per box

Without Switch Resolution on the Fly Implemented

VEL ^0V

+5V

-5V

D1

0°

ERROR

RD-19230

5V

D0

0V

D0

58

5V

SHIFT

27

UP/DN

BIT

0V

ERROR = 1500 LSBs per box

FIGURE 17. BENEFIT OF SWITCHING

RESOLUTION ON THE FLY

FIGURE 16. INPUT WIRING - SWITCHING ON THE FLY

BETWEEN 14 AND 16 BIT RESOLUTION

Data Device Corporation

www.ddc-web.com

RD-19230

12

1) Tie UP/DN to pin -5V.

The Converter Busy (CB) signal indicates that the tracking con-

verter output angle is changing 1 LSB. As shown in FIGURE 20,

output data is valid 50 nS maximum after the middle of the CB

pulse. CB pulse width is 1/40 F_S, which is nominally 375 ns.

2) Choose the two bandwidths following the guidelines in the

General Setup Considerations; the R_Vresistor must be the same

value for both bandwidths.

INTERNAL ENCODER EMULATION

3) Use the SHIFT pin to choose between bandwidths. A logic 1

selects the VEL1 components and a logic 0 selects the VEL2

components.

The RD-19230 can be programmed to encoder emulation mode

by connecting the A_QUAD_B input to GND. The U/B output pin

becomes B (LSB XOR LSB + 1). The A (LSB + 1) and B output

signals can be used in control systems that are designed to inter-

face with incremental optical encoders. To enable the Zero Index

pulse, ZIP_EN should be tied to GND.

INHIBIT, ENABLE, AND CB TIMING

The Inhibit (INH) signal is used to freeze the digital output angle

in the transparent output data latch while data is being trans-

ferred. Application of an Inhibit signal does not interfere with the

continuous tracking of the converter. As shown in FIGURE 18,

angular output data is valid 150 ns maximum after the applica-

tion of the negative inhibit pulse.

The resolution of the incremental outputs is latched from the D0

and D1 inputs on the low going edge of A_QUAD_B. The resolu-

tion of the parallel data outputs may be changed any time after

the encoder resolution is latched (see FIGURE 23, on page 14).

Output angle data is enabled onto the tri-state data bus in two

bytes. Enable MSBs (EM) is used for the most significant 8 bits

and Enable LSBs (EL) is used for the least significant 8 bits. As

shown in FIGURE 19, output data is valid 150 ns maximum after

the application of a negative enable pulse. The tri-state data bus

returns to the high impedance state 100 ns maximum after the

rising edge of the enable signal.

Note: The encoder resolution must be less than or equal to

the resolution of the parallel data outputs. Refer to

FIGURE 21.

The timing of the A, B and ZIP (or North Reference Pole [NRP])

output is dependent on the rate of change of the

synchro/resolver position (rps or degrees per second) and the

encoder resolution latched into the RD-19230 (refer to

FIGURE 22). The calculations for the timing are:

n = encoder resolution latched into RD-19230

t = 1 / ( 2ⁿ* Velocity(RPS))

INHIBIT

T = 1 / ( Velocity(RPS))

150 nsec max

DATA

VALID

FIGURE 18. INHIBIT TIMING

250 to 750 nsec

CB

ENABLE

50 nsec

100 nsec MAX

HIGH Z

150 nsec MAX

DATA

VALID

DATA

VALID

DATA

VALID

DATA

HIGH Z

DATA

FIGURE 19. ENABLE TIMING

FIGURE 20. CONVERTER BUSY TIMING

Data Device Corporation

www.ddc-web.com

RD-19230

13

SYNTHESIZED REFERENCE

BUILT-IN-TEST (BIT)

The synthesized reference section of the RD-19230 eliminates

errors due to phase shift between the reference and signal

inputs. Quadrature voltages in a resolver or synchro are by def-

inition the resulting 90° fundamental signal in the nulled out error

voltage (e) in the converter. Due to the inductive nature of syn-

chros and resolvers, their output signals lead the reference input

signal (RH and RL). When an uncompensated reference signal

is used to demodulate the control transformer’s output, quadra-

ture voltages are not completely eliminated. As shown in

block diagram, FIGURE 1, on page 1, the converter synthesizes

its own internal reference signal based on the SIN and COS sig-

nal inputs. Therefore, the phase of the synthesized (internal) ref-

erence is determined by the signal input, resulting in reduced

quadrature errors.

The BIT output is active low, and will be asserted during the

following three error conditions:

Loss of Signal (LOS) - Sin and Cos inputs both less than 500mV.

Loss of Reference (LOR) - Reference Input less than 500 mV.

Excessive Error - This error is detected by monitoring the

demodulator output, which is proportional to the difference

between the analog input and digital output. When it exceeds

approximately 100 LSBs (in the selected resolution), BIT will be

asserted. This condition can occur any time the analog input

changes at a rate in excess of the maximum tracking rate.

During power up, the converter may see a large difference

between the sin/cos inputs and the digital output angle held in its

counter. BIT will be asserted until the converter settles within

~ 100 LSB’s of the final result.

RD-19230

1 MSB

2

3

4

5

6

7

8

9

10

11

12

13

14

15

BIT 16 LSB

1

0

1

2

1

4

1

6

A

B

FIGURE 21. INCREMENTAL ENCODER EMULATION RESOLUTION CONTROL

B(X- or LSB & LSB+1)

A (LSB+1)

2t

DATA

D0/D1

VALID

50 nsec

A QUAD B

ZIP (NRP)

t

T

359.95

0

FIGURE 23. TIMING FOR INCREMENTAL ENCODER

EMULATION RESOLUTION CONTROL

FIGURE 22. INCREMENTAL ENCODER EMULATION

Data Device Corporation

www.ddc-web.com

RD-19230

14

LVDT MODE

As shown in TABLE 1, on page 2, the RD-19230 unit can be

made to operate as an LVDT-to-digital converter. In this mode the

RD-19230 functions as a ratiometric tracking linear converter.

When linear AC inputs are applied from a LVDT the converter

operates over one quarter of its range. This results in two less

bits of resolution for LVDT mode than are provided in resolver

mode.

Data output of the RD-19230 is Binary Coded in LVDT mode.The

most negative stroke of the LVDT is represented by ALL ZEROS

and the most positive stroke of the LVDT is represented by ALL

ONES.The most significant 2 bits (2 MSBs) may be used as over-

range indicators. Positive overrange is indicated by code “01” and

negative overrange is indicated by code “11“ (see TABLE 7).

TABLE 7. 12-BIT LVDT OUTPUT CODE FOR FIGURE 25

LDVT output signals need to be scaled to be compatible with the

converter input. FIGURE 25 is a schematic of an input scaling

circuit applicable to 3-wire LVDTs. The value of the scaling con-

stant “a” is selected to provide an input of 2 Vrms at full stroke of

the LVDT. The value of scaling constant “b” is selected to provide

an input of 1 Vrms at null of the LVDT. Suggested components

for implementing the input scaling circuit are a quad op-amp,

such as a OP11 type, and precision thin-film resistors of 0.1%

tolerance. FIGURE 24 illustrates a 2-wire LVDT configuration.

LVDT OUTPUT

MSB

LSB

+ over full travel

+ full travel -1 LSB

+0.5 travel

+1 LSB

null

- 1 LSB

-0.5 travel

- full travel

- over full travel

01

00

11

xxxx

1111

1100

1000

0111

0100

0000

xxxx

1111

0000

1111

0000

xxxx

1111

0000

0001

0000

1111

0000

xxxx

C₁

SIN

aR

-S

2 WIRE LVDT

R

-

R

+S

REF IN

R

+

FS = 2 V

aR

C₂

COS

bR

R

2R

-C

R

-

2R

+C

+

2 V

R

bR

+RH

-RL

C

= C , set for phase lag = phase lead through the LVDT.

2

1

FIGURE 24. 2-WIRE LVDT DIRECT INPUT

Data Device Corporation

www.ddc-web.com

RD-19230

15

aR

SIN

-S

R

V

B

-

R'

+S

+

R'

aR

bR

R

2R'

COS

-C

R

-

V

A

R'

R/2

2R'

+

+C

+RH

-RL

bR

Notes:

1. R' ≥ 10 kΩ

2. Consideration for the value of R is LVDT loading.

1

null

1

b =

a =

=

V_A

V_B

null

RDC-19230

INPUT

LVDT

OUTPUT

2

2V

SIN

(V_A- V_B) _max

V

A

1V

a

SIN = 1+ (V_A- V_B)

2

V

B

COS

+FS

NULL

-FS

NULL

a

COS = 1- (V_A- V_B)

2

FIGURE 25. 3-WIRE LVDT SCALING CIRCUIT

Data Device Corporation

www.ddc-web.com

RD-19230

16

TABLE 8. RD-19230 PINOUTS

#

1

NAME

#

NAME

VSS (-5V)

#

NAME

VDD (+5V)

N/C

#

NAME

VEL

-VCO

SJ1

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

Bit 8

2

TP3 (test point)

R CLK

R SET

ENM

Bit 16

3

Bit 9

A (LSB + 1)

TP4 (test point)

N/C

4

SJ2

Bit 2

5

SHIFT

Bit 10

Bit 3

6

VEL2

AGND

VSSP

TP5 (test point)

ZIP_EN

TP6 (test point)

ENL

7

TP1 (test point)

Bit 11

Bit 4

8

VEL1

NCAP

GND

9

TP2 (test point)

N/C

10

11

12

13

14

15

16

+C

PCAP

VDDP

BIT

Bit 12

Bit 5

VDD (+5V)

UP/DN

D0

COS

-C

Bit 13

Bit 6

+S

U/B

D1

SIN

A_QUAD_B

CB (ZI)

Bit 1

Bit 14

Bit 7

INH

-S

RH

VSS (-5V)

Bit 15

RL

Notes:

1. See FIGURE 5 for +5 V only operation.

0.078+0.004

-0.002

2.00+0.10

(

)

-0.05

17

32

0.096MAX

(2.45MAX)

16

33

0.0098MIN,0.0197MAX

(0.25MIN,0.50MAX)

0.0197

(0.50)

0.520±0.010

(13.2±0.25)

RD-19230FX

-XXX

0.394±0.004

(10.00±0.10)

Date Code

pin1

48

0.0098MIN,0.0197MAX

(0.25MIN,0.50MAX)

0.096MAX

(2.45MAX)

49

64

0.394±0.004

(10.00±0.10)

0.007MAX

(0.17MAX)

0.008

(0.22)

0.520±0.010

(13.2±0.25)

0.035+0.006

-0.004

0.88+0.15

(

)

-0.10

Dimensions shown are in inches (millimeters)

FIGURE 26. RD-19230 MECHANICAL OUTLINE

17

Data Device Corporation

www.ddc-web.com

RD-19230

TABLE 9. FRONT-END THIN-FILM RESISTOR NETWORKS

(SEE FIGURE 27)

DDC-49530, DDC-57470 RESISTOR VALUES (11.8 V INPUTS)

SYMBOL

ABS

VALUE

TOL

(%)

REL TO

REL

VALUE

TOL TCR(PPM)

(%)

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

70.8 k

0.1

25

R1

R4

12 k

0.02

2

R1

70.8 k

35.4 k

R1

16

R11

15

R10

14

R9

13

12

R8

11

R7

10

R6

9

R6

6.9282 k 0.02

5.0718 k 0.02

R6

R11

R1

5.0718

6.9282 k 0.02

70.8 k 0.02

0.02

R1

R2

R3

R4

R5

DDC-49590 RESISTOR VALUES (90 V INPUTS)

270 k 0.1

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

25

2

1

2

3

4

5

6

7

8

R1

R4

6 k

0.02

6 k

R1

270 k

135 k

R1

R6

3.4641 k 0.02

2.5359 k 0.02

3.4641 k 0.02

R6

R11

R1

270 k

0.02

FIGURE 27. (DDC-49530, DDC-49590, DDC-57470)

LAYOUT AND RESISTOR VALUES (SEE TABLE 9)

0.870 MAX

(22.10)

.405

7˚

45˚

0.250 ±0.005

(6.35 ±0.13)

0.299

(7.6)

0.101

(2.6)

0.406

(10.3)

0.320 - 0.300

(8.13 - 7.62)

0.014

(.36)

0.13 ±0.005

(3.30 ±0.13)

0.342

(8.7)

0.009

(0.23)

0.092

(2.3)

0.015 ±0.009

(0.38 ±0.23)

0.020 MIN

(0.51)

0.125 MIN

(3.18)

0.075 ±0.015

(1.91 ±0.38)

0.018 ±0.003

(0.46 ±0.08)

0.016

(0.40)

+0.025

0.325

0.050

(1.27)

-0.015

0.100 TYP

(2.54)

+0.64

(8.26

)

-0.38

DIMENSIONS SHOWN ARE IN INCHES (MM).

FIGURE 28. 16-PIN THIN-FILM RESISTOR NETWORK

DIP MECHANICAL OUTLINE

FIGURE 29. 16-PIN THIN-FILM RESISTOR NETWORK

FLAT-PACK MECHANICAL OUTLINE

(DDC-57470)

(DDC-49530, DDC-49590)

Data Device Corporation

www.ddc-web.com

RD-19230

18

ORDERING INFORMATION

RD-19230FX-X X X X

Supplemental Process Requirements:

T = Tape and Reel (50 pc. min. order)

Accuracy:

2 = 4 min + 1 LSB

3 = 2 min + 1 LSB

Reliability:

0 = Standard DDC Procedures

Operating Temperature Range:

2 = -40° to +85°C

3 = 0° to +70°C

THIN-FILM RESISTOR NETWORKS:

DDC-49530 = 11.8 V inputs DIP package

DDC-57470 = 11.8 V inputs Flat-pack package

DDC-49590 = 90 V inputs DIP package

COMPONENT SELECTION SOFTWARE:

Component selection software can be downloaded from our website ( www.ddc-web.com )

Data Device Corporation

www.ddc-web.com

RD-19230

19

The information in this data sheet is believed to be accurate; however, no responsibility is

assumed by Data Device Corporation for its use, and no license or rights are

granted by implication or otherwise in connection therewith.

Specifications are subject to change without notice.

105 Wilbur Place, Bohemia, New York 11716-2482

For Technical Support - 1-800-DDC-5757 ext. 7225

Headquarters - Tel: (631) 567-5600 ext. 7225, Fax: (631) 567-7358

West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988

Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610

United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264

Ireland - Tel: +353-21-341065, Fax: +353-21-341568

France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425

Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089

Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689

World Wide Web - http://www.ddc-web.com

PRINTED IN THE U.S.A.

E-01/01-250

20


型号：	RD-19230F-203T
厂家：	ETC
描述：	Converter 变流器\n
文件：	总20页 (文件大小：154K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RD-19230F-203T [ETC]

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