QL4016-1CG256M/883_技术文档

Military QuickRAM

90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM

Military QuickRAM

D

EVICE

H

IGHLIGHTS

FEATURES

Features

Device Highlights

Total of 316 I/O pins

High Performance and High Density

■ 308 bi-directional input/output pins, PCI-compliant for

■ Up to 90,000 Usable PLD Gates with 316 I/Os

5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades

■ 300 MHz 16-bit Counters, 400 MHz Datapaths, 160+

■ 8 high-drive input/distributed network pins

MHz FIFOs

■ 0.35um four-layer metal non-volatile CMOS process for

smallest die sizes

Eight Low-Skew Distributed Networks

■ Two array clock/control networks available to the logic

cell flip-flop clock, set and reset inputs - each driven by

an input-only pin

High Speed Embedded SRAM

■ Up to 22 dual-port RAM modules, organized in user-

■ Six global clock/control networks available to the logic

cell F1, clock, set and reset inputs and the input and I/O

register clock, reset and enable inputs as well as the

output enable control - each driven by an input-only or

I/O pin, or any logic cell output or I/O cell feedback

configurable 1,152-bit blocks

■ 5ns access times, each port independently accessible

■ Fast and efficient for FIFO, RAM, and ROM functions

Easy to Use / Fast Development Cycles

■ 100% routable with 100% utilization and complete

High Performance

pin-out stability

■ Input + logic cell + output total delays under 6 ns

■ Data path speeds exceeding 400 MHz

■ Counter speeds over 300 MHz

■ Variable-grain logic cells provide high performance and

100% utilization

■ Comprehensive design tools include high quality Verilog/

VHDL synthesis

■ FIFO speeds over 160+ MHz

Military Reliability

■ Mil-STD-883 and Miil Temp Ceramic

Advanced I/O Capabilities

■ Interfaces with both 3.3 volt and 5.0 volt devices

■ Mil Temp Plastic - Guaranteed -55°C to 125°C

■ PCI compliant with 3.3V and 5.0V buses for -1/-2

speed grades

■ Full JTAG boundary scan

■ Registered I/O cells with individually controlled clocks

and output enables

Usable

Gates

Max

I/O

Qualification

Level

Supply

Voltage

Device

Package

84CPGA

84PLCC

100CQFP

144CPGA

208PQFP

208CQFP

70

82

118

174

M, /883

M

M, /883

M

3.3 V

QL4016

11,520 RAM Bits

8,000-

16,000

QL4036

16,128 RAM bits

16,000-

25,000

M, /883

208PQFP

208CQFP

240PQFP

256CPGA

456PBGA

174

207

223

316

M

M, /883

M

M, /883

M

3.3V

QL4090

25,344 RAM bits

36,000-

60,000

M = Military Temperature (-15 to +125 degrees C)

/888 = MIL STD 883

TABLE 1: Selector Table

Rev A

8-37

Military QuickRAM

P

RODUCT

SUMMARY

Product Summary

The QuickRAM family of ESPs (Embedded Standard

Products) offers FPGA logic in combination with

Dual-Port SRAM modules. QuickRAM is a 90,000

usable PLD gate ESPs. QuickRAM ESPs are fabri-

cated on a 0.35mm four-layer metal process using

QuickLogic’s patented ViaLink technology to provide

a unique combination of high performance, high

density, low cost, and extreme ease-of-use.

able in plastic 84-PLCC, 208-PQFP, 240-PQFP and

456-PBGA packages and in ceramic 100, 208-

CQFP and 84, 144, 256-CPGA.

Software support for the complete QuickRAM family

is available through two basic packages. The turnkey

QuickWorks^package provides the most complete

ESP software solution from design entry to logic syn-

thesis, to place and route, to simulation. The Quick-

Tools^TMfor Workstations package provides a solution

for designers who use Cadence, Exemplar, Mentor,

Synopsys, Synplicity, Viewlogic, Veribest, or other

third-party tools for design entry, synthesis, or simu-

lation.

QuickRAM contains up to 1,584 logic cells and 22

dual port RAM modules. Each RAM module has

1,152 RAM bits, for a total of up to 25,344 bits.

RAM Modules are Dual Port (one read port, one

write port) and can be configured into one of four

modes: 64 (deep) x18 (wide), 128x9, 256x4, or

512x2. With a maximum of 316 I/Os, and is avail-

Pinout Diagram 84-Pin PLCC

PINOUT

DIAGRAM 84-PIN PLCC

QuickRAM

QL4016-1PL84M

TABLE 2: 84-pin PLCC

8-38

38

Rev A

Preliminary

Military QuickRAM

PINOUT

DIAGRAM 100-PIN CQFP

Pinout Diagram 100-Pin CQFP

Pin #76

Pin #1

QuickRAM

QL4016-1CF100M

Pin #51

Pin #26

100 CQFP Pinout Table

100

TQFP

100

TQFP

100

TQFP

100

TQFP

Function

1

I/O

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

TDI

I/O

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

I/O

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

TCK

STM

I/O

2

3

I/O

4

I/O

5

I/O

6

I/O

7

I/O

8

I/O

9

GND

I/O

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GND

I/O

GND

I/O

GCLK / I

ACLK / I

VCC

GCLK / I

VCC

I/O

GCLK / I

ACLK / I

VCC

GCLK / I

VCC

I/O

GND

I/O

GND

I/O

VCCIO

I/O

VCCIO

I/O

TRSTB

TMS

I/O

TDO

Rev A

8-39

Military QuickRAM

PINOUT

DIAGRAMS

208-Pin PQFP/CQFP

Pin #157

Pin #1

QuickRAM

QL4090-1PQ208M

Pin #105

Pin #53

Pin #1

240-Pin PQFP

Pin #157

QuickRAM

QL4090-1PQ240M

Pin #105

Pin #53

8-40

40

Rev A

Preliminary

Military QuickRAM

PINOUT

TABLE

PQFP/CQFP 240/208 Pinout Table

240

208

Function

240

208

Function

240

208

Function

240

208

Function

240

208

Function

PQFP PQFP

1

208

1

I/O

51

52

53

54

55

56

57

58

59

60

NC

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

NC

84

85

86

87

88

89

90

91

92

93

94

95

96

97

43

44

45

46

47

48

NC

49

50

51

52

53

54

NC

55

56

NC

57

58

59

60

61

62

63

64

NC

65

66

67

NC

68

69

70

NC

71

NC

72

73

74

NC

75

76

77

78

79

80

81

82

83

GND

I/O

98

84

85

I/O

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

NC

125

126

127

128

NC

I/O

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

168

169

NC

I/O

2

99

3

2

I/O

100

101

102

103

104

105

106

107

108

109

110

NC

86

I/O

GND

I/O

4

3

I/O

87

I/O

170

171

172

173

174

175

NC

I/O

5

4

I/O

88

I/O

6

5

I/O

89

I/O

129

130

131

132

133

134

135

136

NC

GCLK / I

ACLK / I

VCC

GCLK / I

VCC

I/O

7

NC

6

I/O

90

I/O

8

I/O

91

I/O

9

7

I/O

92

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

8

I/O

NC

93

I/O

9

I/O

176

177

178

179

NC

I/O

10

11

12

13

14

NC

15

16

17

18

19

20

NC

21

22

23

24

25

26

27

28

29

30

31

32

NC

33

NC

34

35

36

NC

37

38

39

NC

40

41

42

VCC

I/O

94

I/O

GND

I/O

TDI

I/O

95

GND

I/O

GND

I/O

96

I/O

111

NC

97

VCC

I/O

137

NC

I/O

98

GND

I/O

180

181

182

NC

I/O

NC

99

I/O

138

139

140

141

142

NC

I/O

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

100

NC

101

NC

102

NC

103

104

105

NC

106

107

108

109

NC

110

111

112

113

114

115

116

117

NC

118

119

120

121

NC

122

123

124

I/O

GND

VCC

I/O

183

184

185

186

187

188

NC

I/O

GND

I/O

VCC

I/O

143

144

145

NC

I/O

VCCIO

I/O

TRSTB

TMS

I/O

VCC

I/O

GND

I/O

146

147

148

149

150

151

152

153

154

155

156

157

158

NC

I/O

189

190

191

192

193

194

NC

I/O

GND

I/O

GCLK / I

ACLK / I

VCC

GCLK / I

VCC

I/O

195

196

197

198

NC

I/O

GND

I/O

VCC

I/O

181

182

183

184

185

186

187

188

189

190

191

192

193

TCK

STM

I/O

GND

I/O

199

200

201

202

203

204

205

206

207

GND

I/O

GND

I/O

VCC

I/O

159

160

161

162

163

164

165

166

NC

I/O

VCC

I/O

GND

I/O

GND

I/O

VCC

I/O

TDO

I/O

VCC

I/O

VCCIO

I/O

167

I/O

Rev A

8-41

Military QuickRAM

PINOUT

DIAGRAM 84-PIN CPGA

Pinout Diagram 84-Pin CPGA

QuickRAM

QL4016-1CG84M

84-Pin CPGA Pinout Table

84 CPGA Function 84 CPGA Function 84 CPGA Function 84 CPGA Function

A1

I/O

B11

I/O

F9

I/O

K2

I/O

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

I/O

C1

C2

VCC

I/O

F10

F11

G1

G2

G3

G9

G10

G11

H1

I/O

K3

K4

K5

K6

K7

K8

K9

K10

K11

L1

I/O

C5

VCC

ACLK / I

GND

I/O

GCLK / I

I/O

C6

I/O

C7

VCCIO

GND

I/O

C10

C11

D1

I/O

TCK

I/O

D2

I/O

TDO

I/O

D10

D11

E1

I/O

H2

I/O

TMS

I/O

H10

H11

J1

VCC

I/O

L2

TDI

I/O

L3

I/O

E2

I/O

L4

I/O

E3

GND

VCCIO

I/O

J2

TRSTB

GND

ACLK / I

VCC

STM

I/O

L5

I/O

GCLK / I

I/O

E9

J5

L6

I/O

E10

E11

F1

J6

L7

I/O

J7

L8

I/O

J10

J11

K1

L9

I/O

F2

I/O

L10

L11

I/O

F3

I/O

8-42

42

Rev A

Preliminary

Military QuickRAM

PINOUT

DIAGRAMS

144 & 256-PIN CPGA

S

Pinout Diagrams 144 & 256-Pin CPGAs

QuickRAM

QL4036-1CG144M

144-Pin CPGA

1 2 3 4 5 6 7 8 9 10 11121314151617181920

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

QuickRAM

QL4090-1CG256M

E

D

C

B

A

256-Pin CPGA

Rev A

8-43

Military QuickRAM

PINOUT

TABLE 144-PIN CPGA

Pinout Table 144-Pin CPGA

144

CPGA

144

CPGA

144

CPGA

144

CPGA

Function

A1

I/O

C7

I/O

H13

ACLK / I

N10

I/O

A2

A3

I/O

C8

C9

GND

I/O

H14

H15

J1

I/O

GCLK / I

VCC

I/O

N11

N12

N13

N14

N15

P1

GND

I/O

A4

I/O

C10

C11

C12

C13

C14

C15

D1

I/O

A5

I/O

J2

I/O

A6

I/O

TCK

I/O

J3

I/O

A7

I/O

J13

J14

J15

K1

I/O

A8

I/O

P2

I/O

A9

I/O

GND

GCLK / I

I/O

P3

TDI

I/O

A10

A11

A12

A13

A14

A15

B1

GND

I/O

P4

D2

I/O

K2

P5

I/O

D3

I/O

K3

I/O

P6

I/O

VCC

I/O

D13

D14

D15

E1

I/O

K13

K14

K15

L1

I/O

P7

I/O

P8

I/O

P9

VCCIO

I/O

P10

P11

P12

P13

P14

P15

R1

B2

TDO

I/O

E2

VCC

I/O

L2

I/O

B3

E3

L3

GND

I/O

B4

I/O

E13

E14

E15

F1

GND

I/O

L13

L14

L15

M1

M2

M3

M13

M14

M15

N1

I/O

B5

I/O

VCC

I/O

TRSTB

I/O

B6

I/O

B7

VCCIO

I/O

B8

F2

I/O

R2

I/O

B9

I/O

F3

I/O

R3

VCC

I/O

B10

B11

B12

B13

B14

B15

C1

I/O

F13

F14

F15

G1

I/O

R4

I/O

R5

I/O

GCLK / I

GND

I/O

R6

GND

I/O

STM

I/O

R7

G2

N2

I/O

R8

I/O

G3

I/O

N3

I/O

R9

I/O

G13

G14

G15

H1

VCC

GCLK / I

I/O

N4

I/O

R10

R11

R12

R13

R14

R15

I/O

C2

I/O

N5

I/O

C3

I/O

N6

I/O

C4

I/O

N7

I/O

C5

GND

I/O

H2

N8

GND

I/O

C6

H3

ACLK / I

N9

TMS

8-44

44

Rev A

Preliminary

Military QuickRAM

PINOUT

TABLE 256-PIN CPGA

Pinout Table 256-Pin CPGA

256

CPGA

256

CPGA

256

CPGA

256

CPGA

256

CPGA

Function

CPGA

Function

A1

A2

VCC

I/O

C4

C5

I/O

VCC

I/O

VCC

I/O

STM

I/O

E19

E20

F1

I/O

VCC

I/O

L2

L3

GCLK / I

GND

I/O

T17

T18

T19

T20

U1

I/O

VCC

I/O

VCC

GND

I/O

GND

I/O

GND

TMS

I/O

V20

W1

I/O

A3

VCC

I/O

C6

L4

W2

I/O

A4

C7

F2

GND

I/O

L17

L18

L19

L20

M1

M2

M3

M4

M17

M18

M19

M20

N1

GCLK / I

I/O

W3

I/O

A5

I/O

C8

F3

W4

I/O

A6

I/O

C9

F4

I/O

VCC

ACLK / I

VCC

I/O

U2

W5

GND

I/O

A7

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

D1

F17

F18

F19

F20

G1

I/O

U3

W6

A8

I/O

GND

I/O

U4

W7

I/O

A9

I/O

U5

W8

I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B1

GND

I/O

U6

W9

I/O

U7

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

Y1

I/O

G2

I/O

U8

GND

I/O

G3

I/O

U9

I/O

G4

I/O

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

V1

VCCIO

I/O

G17

G18

G19

G20

H1

I/O

N2

I/O

GND

I/O

N3

I/O

D2

I/O

N4

I/O

TCK

I/O

D3

H2

I/O

N17

N18

N19

N20

P1

I/O

TRSTB

I/O

D4

H3

I/O

B2

I/O

D5

H4

I/O

TDI

I/O

B3

I/O

D6

H17

H18

H19

H20

J1

I/O

GND

I/O

Y2

B4

GND

I/O

D7

I/O

Y3

I/O

B5

D8

I/O

P2

I/O

Y4

VCC

I/O

B6

I/O

D9

I/O

P3

VCC

I/O

V2

Y5

B7

I/O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

E1

I/O

P4

V3

Y6

I/O

B8

VCCIO

I/O

J2

I/O

P17

P18

P19

P20

R1

GND

I/O

V4

Y7

I/O

B9

J3

GND

I/O

V5

Y8

I/O

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

C1

VCC

I/O

J4

I/O

V6

Y9

I/O

J17

J18

J19

J20

K1

I/O

V7

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

I/O

GND

I/O

VCC

GND

VCC

ACLK / I

VCC

GND

GCLK / I

I/O

V8

I/O

R2

I/O

V9

I/O

R3

GND

I/O

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

I/O

R4

I/O

VCC

I/O

K2

R17

R18

R19

R20

T1

I/O

K3

VCC

I/O

GND

I/O

K4

VCC

I/O

E2

K17

K18

K19

K20

L1

I/O

E3

I/O

E4

GCLK / I

T2

I/O

C2

I/O

E17

E18

T3

I/O

C3

TDO

T4

VCC

Rev A

8-45

Military QuickRAM

PINOUT

DIAGRAM 456-PIN PBGA

Pinout Diagram 456-Pin PBGA

QuickRAM

QL4090-1PB456CM

456 Pin PBGA

TOP

PIN A1

CORNER

Bottom

8-46

46

Rev A

Preliminary

Military QuickRAM

PINOUT

TABLE 456-PIN PBGA

Pinout Table 456-Pin PBGA

456

Function

456

B26

C1

Function

STM

I/O

TDO

I/O

TCK

I/O

GND

I/O

NC

456

D25

D26

E1

Function

I/O

456

H4

Function

456

M14

M15

M16

M22

M23

M24

M25

M26

N1

Function

GND/THERM

NC

A1

I/O

VCCIO

I/O

A2

I/O

H5

NC

A3

C2

I/O

H22

H23

H24

H25

H26

J1

NC

A4

C3

E2

I/O

A5

C4

E3

I/O

NC

A6

C5

E4

I/O

A7

C6

E5

GND

VCC

GND

NC

I/O

A8

C7

E6

I/O

A9

C8

E7

J2

I/O

GCLK/I

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

B1

C9

E8

J3

I/O

N2

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

E9

GND

I/O

J4

NC

N3

I/O

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

J5

GND

N4

GCLK/I

GND

VCC

GND

NC

J22

J23

J24

J25

J26

K1

NC

N5

VCC

NC

N11

N12

N13

N14

N15

N16

N22

N23

N24

N25

N26

P1

GND/THERM

GND

I/O

K2

I/O

GND

NC

K3

I/O

K4

I/O

GND

VCC

GND

I/O

K5

VCC

I/O

K22

K23

K24

K25

K26

L1

GND

I/O

P2

I/O

P3

I/O

B2

I/O

P4

I/O

B3

D2

I/O

L2

I/O

P5

NC

B4

D3

F2

I/O

L3

I/O

P11

P12

P13

P14

P15

P16

P22

P23

P24

P25

P26

R1

GND/THERM

NC

B5

D4

F3

I/O

L4

I/O

B6

D5

F4

NC

L5

NC

B7

D6

F5

VCC

NC

L11

L12

L13

L14

L15

L16

L22

L23

L24

L25

L26

M1

GND/THERM

NC

B8

D7

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

NC

F22

F23

F24

F25

F26

G1

B9

D8

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

D9

I/O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

I/O

GCLK / I

I/O

G2

I/O

ACLK / I

I/O

G3

I/O

G4

I/O

R2

I/O

G5

NC

I/O

R3

I/O

G22

G23

G24

G25

G26

H1

GND

I/O

ACLK / I

GCLK/I

I/O

R4

NC

M2

R5

NC

I/O

M3

R11

R12

R13

R14

R15

R16

GND/THERM

(Cont’d on next page)

I/O

M4

NC

I/O

M5

GND

I/O

GND

I/O

M11

M12

M13

GND/THERM

H2

I/O

H3

I/O

Rev A

8-47

Military QuickRAM

PBGA 456 Pinout Table

(continued from previous page)

456

R22

R23

R24

R25

R26

T1

Function

456

Y1

Function

I/O

456

AC6

Function

NC

456

AE5

Function

I/O

NC

VCC

NC

Y2

I/O

AC7

I/O

NC

AE6

I/O

Y3

I/O

AC8

AE7

I/O

Y4

I/O

AC9

AE8

GCLK / I

Y5

I/O

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AD1

I/O

NC

AE9

I/O

Y22

GND

I/O

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AF1

T2

I/O

Y23

T3

I/O

Y24

I/O

VCCIO

NC

T4

I/O

Y25

I/O

T5

VCC

Y26

I/O

T11

T12

T13

T14

T15

T16

T22

T23

T24

T25

T26

U1

GND/THERMAL

AA1

AA2

AA3

AA4

AA5

AA22

AA23

AA24

AA25

AA26

AB1

I/O

NC

GND/THERMAL

I/O

GND/THERMAL

NC

GND/THERMAL

NC

I/O

NC

GND/THERMAL

VCC

NC

GND/THERMAL

GND

I/O

GND

I/O

NC

I/O

TMS

I/O

AB2

I/O

U2

I/O

AB3

I/O

AD2

U3

I/O

AB4

I/O

AD3

I/O

TRSTB

I/O

TDI

I/O

AF2

U4

I/O

AB5

GND

VCC

NC

AD4

AF3

U5

GND

NC

AB6

AD5

AF4

U22

U23

U24

U25

U26

V1

AB7

AD6

AF5

I/O

AB8

NC

AD7

AF6

I/O

AB9

NC

AD8

AF7

I/O

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AC1

AC2

AC3

AC4

AC5

VCC

GND

NC

AD9

AF8

I/O

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AE1

AF9

I/O

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

V2

I/O

V3

I/O

GND

VCC

I/O

V4

NC

V5

NC

V22

V23

V24

V25

V26

W1

GND

NC

VCC

GND

NC

I/O

VCC

GND

I/O

W2

I/O

W3

I/O

W4

I/O

W5

NC

I/O

W22

W23

W24

W25

W26

NC

I/O

NC

AE2

I/O

GND

I/O

AE3

I/O

AE4

8-48

48

Rev A

Preliminary

Military QuickRAM

Pin Descriptions

DESCRIPTIONS

Function

Description

Hold HIGH during normal operation. Connects to serial

PROM data in for RAM initialization. Connect to VCC if

unused.

TDI/RSI

Test Data In for JTAG /

RAM init. Serial Data In

Hold LOW during normal operation. Connects to serial

PROM reset for RAM initialization. Connect to GND if

unused.

TRSTB/RRO

Active low Reset for JTAG /

RAM init. reset out

Hold HIGH during normal operation. Connect to VCC if

not used for JTAG.

TMS

Test Mode Select for JTAG

Test Clock for JTAG

Hold HIGH or LOW during normal operation. Connect to

VCC or ground if not used for JTAG.

TCK

Connect to serial PROM clock for RAM initialization. Must

be left unconnected if not used for JTAG or RAM

initialization.

TDO/RCO

Test data out for JTAG /

RAM init. clock out

Must be grounded during normal operation.

Can be configured as either or both.

STM

Special Test Mode

I/ACLK

High-drive input and/or

array network driver

Can be configured as either or both.

I/GCLK

High-drive input and/or

global network driver

Use for input signals with high fanout.

Can be configured as an input and/or output.

Connect to 3.3V supply.

I

High-drive input

I/O

Input/Output pin

VCC

VCCIO

Power supply pin

Connect to 5.0 volt supply if 5 volt input tolerance is

required, otherwise connect to 3.3V supply.

Input voltage tolerance pin

Connect to ground.

GND

Ground pin

Available on 456-PBGA only. Connect to ground plane on

PCB if heat sinking desired. Otherwise may be left

unconnected.

GND/THERM

Ground/Thermal pin

Ordering Information

QL 4090 - 1 PQ208 M

QuickLogic

device

Operating Range

M = Military

M/883 = MIL STD 883

QuickRAM device

part number

4016

Package Code

PL84 = 84-pin PLCC

CG84=84-pin CPGA

CF100 = 100-pin CQFP

CG144=144-pin CPGA

PQ208 = 208-pin PQFP

CF208 = 208-pin CQFP

PQ240 = 240-pin PQFP

CG256=256-pin CPGA

CG456=456-pin PBGA

4036

4090

Speed Grade

0 = quick

1 = fast

2 = faster

Rev A

8-49

Military QuickRAM

ABSOLUTE MAXIMUM RATINGS

VCC Voltage...........................-0.5 to 4.6V

DC Input Current...................... 20 mA

ESD Pad Protection.................... 2000V

Storage Temperature .......-65°C to +150°C

Lead Temperature ...........................300°C

VCCIO Voltage .......................-0.5 to 7.0V

Input Voltage..............-0.5 to VCCIO+0.5V

Latch-up Immunity................... 200 mA

OPERATING RANGE

Symbol

Parameter

Military

Max

Unit

Min

3.0

-55

VCC

VCCIO

TA

Supply Voltage

3.6

5.5

V

°C

I/O Input Tolerance Voltage

Ambient Temperature

Case Temperature

TC

125

2.03

1.64

1.37

-0 Speed Grade 0.42

-1 Speed Grade 0.42

-2 Speed Grade 0.42

K

Delay Factor

DC CHARACTERISTICS

Symbol

VIH

VIL

Parameter

Conditions

Min

Max

Unit

V

Input HIGH Voltage

Input LOW Voltage

Output HIGH Voltage

0.5VCC VCCIO+0.5

-0.5

2.4

0.3VCC

VOH

IOH = -12 mA

V

0.9VCC

V

µA

pF

mA

µA

IOH = -500 µA

IOL = 8 mA [1]

IOL = 1.5 mA

VOL

Output LOW Voltage

0.45

0.1VCC

10

-180

210

5

II

IOZ

CI

I or I/O Input Leakage Current

VI = VCCIO or GND

-10

3-State Output Leakage Current VI = VCCIO or GND

Input Capacitance [2]

IOS

Output Short Circuit Current [3]

VO = GND

VO = VCC

-15

40

ICC

ICCIO

D.C. Supply Current [4]

D.C. Supply Current on VCCIO

VI, VIO = VCCIO or GND 0.50 (typ)

0

100

Notes:

[1] Military devices have 8 mA IOL specifications.

[2] Capacitance is sample tested only. Clock pins are 12 pF maximum.

[3] Only one output at a time. Duration should not exceed 30 seconds.

[4] Maximum ICC is 5 mA for all military grade devices. For AC conditions, contact QuickLogic

customer engineering.

8-50

50

Rev A

Preliminary

Military QuickRAM

QL4016

AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00)

(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)

Logic Cells

Propagation Delays (ns)

Symbol

tPD

tSU

tH

tCLK

tCWHI

tCWLO

tSET

tRESET

tSW

Parameter

Fanout [6]

3

1

2

4

8

Combinatorial Delay [7]

Setup Time [7]

Hold Time

Clock to Q Delay

Clock High Time

Clock Low Time

Set Delay

Reset Delay

Set Width

Reset Width

1.4

1.7

0.0

0.7

1.2

1.0

0.8

1.9

1.8

1.7

0.0

1.0

1.2

1.3

1.1

1.9

1.8

1.9

1.7

0.0

1.2

1.5

1.3

2.2

1.7

0.0

1.5

1.2

1.8

1.6

1.9

1.8

3.2

1.7

0.0

2.5

1.2

2.8

2.6

1.9

1.8

1.9

1.8

tRW

Input-Only/Clock Cells

Propagation Delays (ns)

Symbol

Parameter

High Drive Input Delay

High Drive Input, Inverting Delay

Input Register Set-Up Time

Input Register Hold Time

Input Register Clock To Q

Input Register Reset Delay

Input Register Clock Enable Setup Time

Fanout [6]

1

2

3

4

8

12

24

TIN

TINI

1.5

1.6

3.1

0.0

0.7

0.6

2.3

1.6

1.7

3.1

0.0

0.8

0.7

2.3

1.8

1.9

3.1

0.0

1.0

0.9

2.3

1.9

2.0

3.1

0.0

1.1

1.0

2.3

2.4

2.5

3.1

0.0

1.6

1.5

2.3

2.9 4.4

3.0 4.5

3.1 3.1

0.0 0.0

2.1 3.6

2.0 3.5

2.3 2.3

TISU

TIH

TlCLK

TlRST

TlESU

TlEH

Input Register Clock Enable Hold Time

0.0

0.0 0.0

Notes:

[6] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as speci-

fied in the Operating Range.

[7] These limits are derived from a representative selection of the slowest paths through the QuickRAM

logic cell including typical net delays. Worst case delay values for specific paths should be determined

from timing analysis of your particular design.

Rev A

8-51

Military QuickRAM

QL4016 Clock Cells

Propagation Delays (ns)

Loads per Half Column [8]

Symbol

Parameter

Array Clock Delay

Global Clock Pin Delay

Global Clock Buffer Delay

1

2

3

4

8

10

1.6

0.7

1.2

11

1.7

0.7

1.3

tACK

tGCKP

tGCKB

1.2

0.7

0.8

1.2

0.7

0.8

1.3

0.7

0.9

1.3

0.7

0.9

1.5

0.7

1.1

I/O Cell Input Delays

Propagation Delays (ns)

Symbol

Parameter

Fanout [6]

1

2

3

4

8

10

tI/O

Input Delay (bidirectional pad)

Input Register Set-Up Time

1.3

3.1

0.0

0.7

0.6

2.3

0.0

1.6

3.1

0.0

1.0

0.9

2.3

0.0

1.8

3.1

0.0

1.2

1.1

2.3

0.0

2.1

3.1

0.0

1.5

1.4

2.3

0.0

3.1

0.0

2.5

2.4

2.3

0.0

3.6

3.1

0.0

3.0

2.9

2.3

0.0

TISU

TIH

Input Register Hold Time

TlOCLK

TlORST

TlESU

TlEH

Input Register Clock To Q

Input Register Reset Delay

Input Register clock Enable Set-Up Time

Input Register Clock Enable Hold Time

I/O Cell Output Delays

Propagation Delays (ns)

Output Load Capacitance (pF)

Symbol

Parameter

30

50

75

100

3.6

3.7

2.8

3.1

150

4.7

4.8

3.9

4.2

TOUTLH

TOUTHL

TPZH

Output Delay Low to High

2.1

2.2

1.2

1.6

2.0

1.2

2.5

2.6

1.7

2.0

3.1

3.2

2.2

2.6

Output Delay High to Low

Output Delay Tri-state to High

Output Delay Tri-state to Low

Output Delay High to Tri-State [9]

Output Delay Low to Tri-State [9]

TPZL

TPHZ

TPLZ

Notes:

[6] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as

specified in the Operating Range.

[8] The array distributed networks consist of 40 half columns and the global distributed networks consist of

44 half columns, each driven by an independent buffer. The number of half columns used does not

affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to

11 loads per half column.

[9] The following loads are used for tPXZ:

tPHZ

Ω

1K

5 pF

Ω

1K

tPLZ

5 pF

8-52

52

Rev A

Preliminary

Military QuickRAM

QL4036

AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00)

(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)

Logic Cells

Propagation Delays (ns)

Symbol

tPD

tSU

tH

tCLK

tCWHI

tCWLO

tSET

tRESET

tSW

Parameter

Fanout [5]

3

1

2

4

8

Combinatorial Delay [6]

Setup Time [6]

Hold Time

Clock to Q Delay

Clock High Time

Clock Low Time

Set Delay

Reset Delay

Set Width

Reset Width

1.4

1.7

0.0

0.7

1.2

1.0

0.8

1.9

1.8

1.7

0.0

1.0

1.2

1.3

1.1

1.9

1.8

1.9

1.7

0.0

1.2

1.5

1.3

2.2

1.7

0.0

1.5

1.2

1.8

1.6

1.9

1.8

3.2

1.7

0.0

2.5

1.2

2.8

2.6

1.9

1.8

1.9

1.8

tRW

Input-Only/Clock Cells

Propagation Delays (ns)

Symbol

Parameter

High Drive Input Delay

High Drive Input, Inverting Delay

Input Register Set-Up Time

Input Register Hold Time

Input Register Clock To Q

Input Register Reset Delay

Input Register Clock Enable Setup Time

Fanout [5]

1

2

3

4

8

12

24

TIN

TINI

1.5

1.6

3.1

0.0

0.7

0.6

2.3

1.6

1.7

3.1

0.0

0.8

0.7

2.3

1.8

1.9

3.1

0.0

1.0

0.9

2.3

1.9

2.0

3.1

0.0

1.1

1.0

2.3

2.4

2.5

3.1

0.0

1.6

1.5

2.3

2.9 4.4

3.0 4.5

3.1 3.1

0.0 0.0

2.1 3.6

2.0 3.5

2.3 2.3

TISU

TIH

TlCLK

TlRST

TlESU

TlEH

Input Register Clock Enable Hold Time

0.0

0.0 0.0

Notes:

[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C. Multi-

ply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the

Operating Range.

[6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell

including typical net delays. Worst case delay values for specific paths should be determined fromtiming

analysis of your particular design.

Rev A

8-53

Military QuickRAM

QL4036 Clock Cells

Propagation Delays (ns)

Loads per Half Column [7]

Symbol

Parameter

Array Clock Delay

Global Clock Pin Delay

Global Clock Buffer Delay

1

2

3

4

8

10

1.6

0.7

1.2

12

1.7

0.7

1.3

15

1.8

0.7

1.4

tACK

tGCKP

tGCKB

1.2

0.7

0.8

1.2

0.7

0.8

1.3

0.7

0.9

1.3

0.7

0.9

1.5

0.7

1.1

I/O Cell Input Delays

Propagation Delays (ns)

Symbol

Parameter

Fanout [5]

1

2

3

4

8

10

tI/O

Input Delay (bidirectional pad)

Input Register Set-Up Time

1.3

3.1

0.0

0.7

0.6

2.3

0.0

1.6

3.1

0.0

1.0

0.9

2.3

0.0

1.8

3.1

0.0

1.2

1.1

2.3

0.0

2.1

3.1

0.0

1.5

1.4

2.3

0.0

3.1

0.0

2.5

2.4

2.3

0.0

3.6

3.1

0.0

3.0

2.9

2.3

0.0

TISU

TIH

Input Register Hold Time

TlOCLK

TlORST

TlESU

TlEH

Input Register Clock To Q

Input Register Reset Delay

Input Register clock Enable Set-Up Time

Input Register Clock Enable Hold Time

I/O Cell Output Delays

Propagation Delays (ns)

Output Load Capacitance (pF)

Symbol

Parameter

30

50

75

100

3.6

3.7

2.8

3.1

150

4.7

4.8

3.9

4.2

TOUTLH

TOUTHL

TPZH

Output Delay Low to High

2.1

2.2

1.2

1.6

2.0

1.2

2.5

2.6

1.7

2.0

3.1

3.2

2.2

2.6

Output Delay High to Low

Output Delay Tri-state to High

Output Delay Tri-state to Low

Output Delay High to Tri-State [8]

Output Delay Low to Tri-State [8]

TPZL

TPHZ

TPLZ

Notes:

[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as

specified in the Operating Range.

[7] The array distributed networks consist of 56 half columns and the global distributed networks consist of

60 half columns, each driven by an independent buffer. The number of half columns used does not

affect clock buffer delay. The array clock has up to 12 loads per half column. The global clock has up

to 15 loads per half column.

[8] The following loads are used for tPXZ:

tPHZ

Ω

1K

5 pF

Ω

1K

tPLZ

5 pF

8-54

54

Rev A

Preliminary

Military QuickRAM

QL4090

AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00)

(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)

Logic Cells

Propagation Delays (ns)

Symbol

tPD

tSU

tH

tCLK

tCWHI

tCWLO

tSET

tRESET

tSW

Parameter

Fanout [5]

3

1

2

4

8

Combinatorial Delay [6]

Setup Time [6]

Hold Time

Clock to Q Delay

Clock High Time

Clock Low Time

Set Delay

Reset Delay

Set Width

Reset Width

1.4

1.7

0.0

0.7

1.2

1.0

0.8

1.9

1.8

1.7

0.0

1.0

1.2

1.3

1.1

1.9

1.8

1.9

1.7

0.0

1.2

1.5

1.3

2.2

1.7

0.0

1.5

1.2

1.8

1.6

1.9

1.8

3.2

1.7

0.0

2.5

1.2

2.8

2.6

1.9

1.8

1.9

1.8

tRW

Input-Only/Clock Cells

Propagation Delays (ns)

Symbol

Parameter

Fanout [5]

1

2

3

4

8

12

24

TIN

TINI

High Drive Input Delay

1.5

1.6

3.1

0.0

0.7

0.6

2.3

0.0

1.6

1.7

3.1

0.0

0.8

0.7

2.3

0.0

1.8

1.9

3.1

0.0

1.0

0.9

2.3

0.0

1.9

2.0

3.1

0.0

1.1

1.0

2.3

0.0

2.4

2.5

3.1

0.0

1.6

1.5

2.3

0.0

2.9 4.4

3.0 4.5

3.1 3.1

0.0 0.0

2.1 3.6

2.0 3.5

2.3 2.3

0.0 0.0

High Drive Input, Inverting Delay

Input Register Set-Up Time

Input Register Hold Time

Input Register Clock To Q

Input Register Reset Delay

TISU

TIH

TlCLK

TlRST

TlESU

TlEH

Input Register Clock Enable Setup Time

Input Register Clock Enable Hold Time

Notes:

[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as

specified in the Operating Range.

[6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic

cell including typical net delays. Worst case delay values for specific paths should be determined from

timing analysis of your particular design.

Rev A

8-55

Military QuickRAM

QL4090 Clock Cells

Propagation Delays (ns)

Loads per Half Column [7]

10 12 14

Symbol

Parameter

1

2

3

4

8

16

18

2

20

2.1

0.7

1.7

TACK

Array Clock Delay

1.2 1.2 1.3 1.3 1.5 1.6 1.7 1.8 1.9

0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7

0.8 0.8 0.9 0.9 1.1 1.2 1.3 1.4 1.5

TGCKP

TGCKB

Global Clock Pin Delay

Global Clock Buffer Delay

0.7

1.6

I/O Cell Input Delays

Propagation Delays (ns)

Symbol

Parameter

Fanout [5]

1

2

3

4

8

10

tI/O

Input Delay (bidirectional pad)

Input Register Set-Up Time

1.3

3.1

0.0

0.7

0.6

2.3

0.0

1.6

3.1

0.0

1.0

0.9

2.3

0.0

1.8

3.1

0.0

1.2

1.1

2.3

0.0

2.1

3.1

0.0

1.5

1.4

2.3

0.0

3.1

0.0

2.5

2.4

2.3

0.0

3.6

3.1

0.0

3.0

2.9

2.3

0.0

TISU

TIH

Input Register Hold Time

Input Register Clock To Q

TlOCLK

TlORST

TlESU

TlEH

Input Register Reset Delay

Input Register clock Enable Set-Up Time

Input Register Clock Enable Hold Time

I/O Cell Output Delays

Propagation Delays (ns)

Output Load Capacitance (pF)

Symbol

Parameter

30

50

75

100

3.6

3.7

2.8

3.1

150

4.7

4.8

3.9

4.2

TOUTLH

TOUTHL

TPZH

Output Delay Low to High

2.1

2.2

1.2

1.6

2.0

1.2

2.5

2.6

1.7

2.0

3.1

3.2

2.2

2.6

Output Delay High to Low

Output Delay Tri-state to High

Output Delay Tri-state to Low

Output Delay High to Tri-State [8]

Output Delay Low to Tri-State [8]

TPZL

TPHZ

TPLZ

Notes:

[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as spec-

ified in the Operating Range.

[7] The array distributed networks consist of 88 half columns and the global distributed networks consist of

92 half columns, each driven by an independent buffer. The number of half columns used does not

affect clock buffer delay. The array clock has up to 18 loads per half column. The global clock has up

to 20 loads per half column.

[8] The following loads are used for tPXZ:

tPHZ

1KΩ

5 pF

1KΩ

tPLZ

5 pF

8-56

56

Rev A

Preliminary

Military QuickRAM

RAM Cell Synchronous Write Timing

Propagation Delays (ns)

Fanout

Symbol

TSWA

THWA

TSWD

THWD

TSWE

THWE

TWCRD

Parameter

1

2

3

4

8

WA Setup Time to WCLK

WA Hold Time to WCLK

WD Setup Time to WCLK

WD Hold Time to WCLK

WE Setup Time to WCLK

WE Hold Time to WCLK

WCLK to RD (WA=RA) [5]

1.0

0.0

1.0

0.0

1.0

0.0

5.0

1.0

0.0

1.0

0.0

1.0

0.0

5.3

1.0

0.0

1.0

0.0

1.0

0.0

5.6

1.0

0.0

1.0

0.0

1.0

0.0

5.9

1.0

0.0

1.0

0.0

1.0

0.0

7.1

RAM Cell Synchronous Read Timing

Propagation Delays (ns)

Fanout

Symbol

Parameter

1

2

3

4

8

TSRA

THRA

TSRE

THRE

TRCRD

RA Setup Time to RCLK

RA Hold Time to RCLK

RE Setup Time to RCLK

RE Hold Time to RCLK

RCLK to RD [5]

1.0

0.0

1.0

0.0

4.0

1.0

0.0

1.0

0.0

4.3

1.0

0.0

1.0

0.0

4.6

1.0

0.0

1.0

0.0

4.9

1.0

0.0

1.0

0.0

6.1

RAM Cell Asynchronous Read Timing

Propagation Delays (ns)

Fanout

Symbol

RPDRD

Parameter

RA to RD [5]

1

3.0

2

3

4

8

5.1

3.3

3.6

3.9

Notes:

[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as

specified in the Operating Range.

Rev A

8-57

Military QuickRAM

8-58

58

Rev A

Preliminary


型号：	QL4016-1CG256M/883
厂家：	ETC
描述：	90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM 90000可使用的PLD门QuickRAM结合性能，密度和嵌入式RAM 栅
文件：	总22页 (文件大小：578K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

QL4016-1CG256M/883 [ETC]

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