PLLCORE90 [ETC]
Phase-Locked Loop ; 锁相环\n
ETC 
AMI5LG Gate Array
AMI5LS Standard Cell
PLLCORExxx
®
AMERICAN MICROSYSTEMS, INC
November 1998
AMI5LG & AMI5LS CMOS
Description
The PLLCORExxx is a phase locked loop building block. This cell contains a voltage
controlled oscillator (VCO), an internal loop filter, and a digital phase frequency
detector. The PLLCORExxx is available in AMI5L standard cells and gate arrays.
Customer supplied delay and divider blocks, as well as an external reference clock, are
required for a complete PLL circuit that will lock a VCO generated clock signal to a
multiple of the reference clock frequency. The clock dividers, delay logic, and test
logic are built of standard cells or gate array core cells as soft megacell blocks.
The ‘xxx’ refers to the center frequency of the VCO.
Features
• Internal loop filter saves external loop filter components
• Loop filter time constants are pin programmable
• Output Duty Cycle of 50% +/- 10%
Specifications (Vdd = 3.3V +/- 10%,Tj=-55-140c)
CELL
PLLCORE60
Fmin (MHz) Fmax (MHz)
40
50
80
PLLCORE75
100
PLLCORE90
PLLCORE120
PLLCORE170
60
80
110
120
160
220
Jitter performance data is not yet available. Use of the internal loop filter is expected to
result in jitter perfomance at the 1-3ns level. Use of an external loop filter is expected to
improve the jitter perfomance. Jitter perfomance will depend on the actual ASIC circuit
implementation.
Page 1 of 4
AMI5LG Gate Array
AMI5LS Standard Cell
PLLCORExxx
®
AMERICAN MICROSYSTEMS, INC
November 1998
AMI5LG & AMI5LS CMOS
Logic Symbol
PLLCORExxx
tstcppad
vcoclk
refclk
sysclk
lf<3:0>
pd
rn
tstvcopad
Pin Description
Signal
Signal Description
LF<3:0>
Control inputs to program loop filter
PD
Power down input from core to place PLL in low power mode (asserted high)
Reference clock from core supplied by chip pad cell or core logic
Reset signal from core to reset PLL and discharge loop filter (asserted low)
System clock to core (when TSTE = 1, SYSCLK = TSTCLK)
VCO output to divider logic or to PLL test logic this signal should not be used for a core clock
External test pin: output from charge pump
REFCLK
RN
SYSCLK
VCOCLK
TSTCPPAD
TSTVCOPAD
PLLVDDPAD
PLLVSSPAD
External test pin: analog input to VCO
External pin: provides isolated PLL Vdd supply
External pin: provides isolated PLL Vss supply
Equivalent Gates
PLL Block
Test logic
PLLCORE
PLL Pads
Equivalent Gates
61.4
Corner Cell
2 I/O Pads+ 2 Power Pads
Page 2 of 4
AMI5LG Gate Array
AMI5LS Standard Cell
PLLCORExxx
®
AMERICAN MICROSYSTEMS, INC
November 1998
VCO Center Frequency
AMI5LG & AMI5LS CMOS
Please contact the factory to specify the center frequency required for your
application if the available cells do not fit your requirement.
Frequency vs. Voltage Characteristics
These tables show the variation of the VCO over minimum, typical, and maximum
process and temperature conditions. This data can be used to determine the VCO
transfer function for loop analysis and to provide test data for VCO testing.
V (VCO)
PLLCORE 60
PLLCORE 75
MIN TYP MAX
VCO
0.5V
1.5V
2.5V
MIN
TYP
22
MAX
8
41
10
68
24
45
54
84
135
176
256
316
172
225
330
405
111
V (VCO)
PLLCORE 90
PLLCORE 120
PLLCORE 170
TYP MAX
VCO
0.5V
1.5V
2.5V
MIN
12
TYP
25
MAX MIN TYP MAX MIN
52
18
38
78
22
52
107
756
924
82
197
257
378
469
107
176
287
378
567
695
149
228
379
497
121
Page 3 of 4
AMI5LG Gate Array
AMI5LS Standard Cell
PLLCORExxx
®
AMERICAN MICROSYSTEMS, INC
November 1998
AMI5LG & AMI5LS CMOS
For more information:
Please refer to the AMI Phase Locked Loop Application Note for information on the
following topics.
•
• Clock divider placement
• PLL pad locations
• PLL truth tables
• Loop filter programming
• Sample application
• Test logic requirements
• Test methodology
• Test pattern requirements
Author: Brian Kauffmann
email: libdev-support@poci.amis.com
Page 4 of 4
相关型号：
©2020 ICPDF网 联系我们和版权申明